The subject of research in this paper is multiple-valued (MV) memory cell—particularly the morphology of boundary surface of five-valued memory. By accepting the values of parasitic accumulation elements on the chip, very complicated morphology of the boundary surfaces occurs, which separates various attractors from each other. This is due to the occurrence of undesirable oscillations—a stable limit cycles, which makes it impossible to control memory. These dynamic attractors are so dominant that their regions of attraction even surround regions of attraction of static attractors—required logic levels of memory. Therefore, in the realization of the MV memory on the chip is necessary to know the values of the parasitic elements, because their presence may cause a malfunction of the memory. In this case, only calculation and displaying the boundary surface provides exact answers related to operation of the MV memory.

Multiple-valued logic (MVL) compared to the binary logic has the advantage that in circuits with MVL, according to [

While in the 80s of the last century MVL memories were designed based on MOS transistors [

In order to control any memory, not only just MVL memory, exact investigation of dynamic properties of the elementary memory is necessary. It is not possible without the knowledge of the morphological characteristics of the boundary surface (BS) that separates the regions of attraction of particular attractors. BS is used not only in memories [

Circuit of the MV elementary memory is shown in Figure

Ternary memory circuit.

The first ternary memories consisting of RTDs were analyzed in [

Monge’s projection of the cross-section (in singularity N1) of the boundary surfaces, stable limit cycles, and unstable limit cycle for considered

For a color distinction of particular regions of attraction in Figure

the green, gray, and red colors represent regions of attraction for stable singularities S1, S2, and S3;

yellow, purple, and blue colors represent regions of attraction of undesired SLCs—L1, L2, and L3.

Marks on SLCs as a cross and dot in a circle represent the intersection of L1, L2, and L3 through corresponding current (plane

The line denoted that EG1 graphically proves if BS is calculated correctly, because element of BS passing through unstable singularity N1 is tangent plane of green and gray regions of attraction just in N1. More information on the elements of singularities can be found in [

Circuit in Figure

The expressions (

Expression (

(a) Projection of the

Projection of the

As in the case of ternary memory [

Since all unstable singularities for the RTD parameters (

The projections of cross-sections into

They are labeled as L1–L10, and colored regions are symmetrically distributed around the linear projection of

BS morphology of both cases is shown in Figures

The projections of cross-sections into

Since the change of

This work is the result of the project implementation: KEGA no. 005TUKE-4/2012—“Automated checking system based on modern information technology.”