Journal of Electrical and Computer EngineeringVolume 2011 (2011), Article ID 670508, 6 pagesdoi:10.1155/2011/670508

Research Article

New Low-Power Tristate Circuits in Positive Feedback Source-Coupled Logic

Kirti Gupta,¹ Ranjana Sridhar,¹ Jaya Chaudhary,¹ Neeta Pandey,¹ and Maneesha Gupta²

¹Electronics and Communication Department, Delhi Technological University, New Delhi, India²Electronics and Communication Division, Netaji Subhas Institute of Technology, New Delhi, India

Received 31 March 2011; Revised 29 June 2011; Accepted 24 July 2011

Academic Editor: Mohamad Sawan

Copyright © 2011 Kirti Gupta et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Abstract.

Two new design techniques to implement tristate circuits in positive feedback source-coupled logic (PFSCL) have been proposed. The first one is a switch-based technique while the second is based on the concept of sleep transistor. Different tristate circuits based on both techniques have been developed and simulated using 0.18 μm CMOS technology parameters. A performance comparison indicates that the tristate PFSCL circuits based on sleep transistor technique are more power efficient and achieve the lowest power delay product in comparison to CMOS-based and the switch-based PFSCL circuits.

1. Introduction

Nowadays, due to the remarkable growth in portable consumer electronics, the demand for low power and high speed computing circuits is on the rise. High speed microprocessors are the key elements used for data processing in these devices. An increase in the processor speed leads to an excessive power dissipation in portable devices which use batteries as the power sources. So, it is necessary to explore design techniques that reduce power consumption in such systems at high operating speeds. At the circuit level, the traditional CMOS logic style fails to simultaneously satisfy the speed and power requirements of these applications [1] and a different logic style is required [2–8].

Among the possible topologies, PFSCL is the most suitable logic style for designing systems with optimum balance between speed and power dissipation [8–12]. A PFSCL style is derived from the single-ended source-coupled logic in which a positive feedback is introduced that significantly increases the speed as compared to traditional SCL circuits [8]. This improvement in speed can be traded off to reduce the power consumption of the circuits [9–11]. Thus, this logic style can be easily adopted in the design of high speed and high computing circuits for portable devices.

In this paper, PFSCL has been used to develop different tristate circuits that are extensively used in high speed microprocessors and clock/data recovery systems to implement multiplexers, phase detectors, and buses [13, 14]. Two different design techniques have been used to implement tristate circuits in PFSCL. The first one is a switched based technique while the second one uses the concept of sleep transistor.

This paper is organized as follows. The architecture and the operation of PFSCL gates are described in Section 2. The design techniques to develop PFSCL-based tristate circuits are presented in Section 3. In the subsequent Section 4, the proposed tristate circuits are implemented and simulated using 0.18 μm CMOS technology parameters. Finally, the conclusions are drawn in the last section

2. PFSCL Circuits

The basic circuit of a PFSCL inverter is shown in Figure 1. It consists of a source-coupled nMOS transistor pair, M1-M2 biased by the constant current source, and a pMOS load transistor M3 [8–12]. The output of the gate is taken from the drain of pMOS active load, M3. A positive feedback is introduced in PFSCL by connecting the output of the gate to the input to transistor M2. This circuit works on the current steering principle. For a high input voltage , the bias current is steered to M1 that produces a low output at the gate and at the same time makes the transistor M2 off. Similarly, a low input voltage makes M1 off such that it gives a high gate output and turns M2 on. The positive feedback in these circuits reduces the aspect ratio of the nMOS transistor significantly in comparison to traditional single-ended SCL gates for similar values of design constraints. This results in reduced nMOS parasitic capacitances and allows significant speed improvement, which can be traded off to achieve a low power design [10].

Figure 1: Basic PFSCL inverter/buffer.

Figure 2 shows different PFSCL-based basic gates, namely, NOR and NAND. The circuit for a NOR gate Figure 2(a) consists of two nMOS transistors M1 and M2, coupled to the current source along with the positive feedback transistor M3. When both or either of the two inputs A and B is high, M1 or M2 or both together conduct such that the bias current is steered through them and a low gate output is produced. The low gate output turns off transistor M3 through positive feedback. The (optional) pMOS transistor M5 is inserted to generate the complement of the output, and is substituted by a short circuit when it is not needed [9]. The above NOR gate topology has low transistor count as compared to source-coupled gates. The NOR gate topology can be extended to implement NAND gate by using De Morgan law and then taking the output from the drain of optional pMOS transistor (M5) [9] as shown in Figure 2(b).

(a)

(b)

Figure 2: Different PFSCL gates; (a) 2-input NOR, (b) 2-input NAND.

3. Proposed PFSCL Tristate Circuits

A tristate gate is a type of logic gate that produces either high or low voltage level when enabled or have high impedance state when disabled. A tristate buffer implemented in CMOS logic style [15] is shown in Figure 3. A high output level indicates that the output is sourcing current from the positive power terminal while a low output denotes the output is sinking current to the negative power terminal (or zero voltage). High impedance implies that the output is effectively disconnected from the circuit. These CMOS-based circuits are not efficient at high speeds. So two different techniques based on switch transistor and sleep transistor have been used to develop PFSCL tristate circuits for high speed operations.

Figure 3: Tristate CMOS buffer.

3.1. Switch-Based PFSCL Tristate Circuits

In a basic PFSCL gate, there is a direct path from the outputs to the positive supply which cannot be turned off. That is why, it is necessary to isolate the output from the power supply so as to produce a high impedance state for tristate logic. An effective way is to add a MOS transistor switch in series with the output node. The circuit for a tristate buffer/inverter is shown in Figure 4(a). The circuit consists of the basic PFSCL gate (M1–M4) and an additional pMOS switch (M5) connected in series with the output. The circuit behaves as a regular buffer/inverter for low value of Enable whereas its output is driven into high impedance for high Enable value. The circuit has the same static power dissipation as that of the basic PFSCL buffer/inverter. Similarly, the circuit diagrams of switch-based PFSCL NOR and NAND tristate circuits have been developed which is shown in Figures 4(b) and 4(c), respectively.

(a)

(b)

(c)

Figure 4: Switch-based PFSCL tristate circuits; (a) buffer/inverter (b) 2-input NOR, (c) 2-input NAND.

3.2. Sleep Transistor-Based PFSCL Circuits

In this technique, the basic concept of sleep transistor has been extended to obtain a low-power tristate PFSCL gate. The gate output has been isolated from the positive supply by inserting a sleep transistor [15] in series with the power supply of the circuit. The circuit diagram of a tristate PFSCL buffer/inverter is shown in Figure 5(a), wherein the source and gate of the sleep transistor, M5, is connected to power supply and the Enable input, respectively. The drain of M5 is connected to the basic PFSCL buffer/inverter such that it acts as a virtual supply voltage terminal. For low value of enable, the sleep transistor M5 is on so that power supply is connected to the PFSCL buffer/inverter and the circuit behaves as a regular buffer/inverter. For high voltage level, sleep transistor M5 is off and in turn disconnects the power supply so that no current flows in the circuit and high impedance state is produced at the output. In this case, the proposed circuit has less static power dissipation than the basic PFSCL buffer/inverter and basically depends on the time duration for which the sleep transistor is on.

(a)

(b)

(c)

Figure 5: Sleep transistor based PFSCL tristate circuits, (a) buffer/inverter, (b) 2-input NOR, and (c) 2- input NAND.

Thus, the proposed technique provides low power PFSCL tristate circuits. Similarly, the circuit diagrams of sleep transistor based PFSCL NOR and NAND tristate circuits are shown in Figures 5(b) and 5(c).

4. Simulation Results

Different PFSCL tristate logic gates such as buffer, NOR, and NAND gates have been implemented by using switch-based and sleep transistor techniques. All the gates are simulated using 0.18 μm CMOS technology parameters. The design have been targeted for high speed as it consumes substantial power. Under this condition, the design parameters such as the voltage swing, the bias current, and the power supply for the gate have been taken as 400 mV, 90 A, and 1.8 V, respectively, as outlined in [11]. The performance of the circuits obtained by the two techniques is compared with CMOS circuits in terms of power delay through simulations. The simulation results of the circuits in Figures 3, 4 and 5 are listed in Tables 1, 2 and 3 respectively.

Table 1: CMOS Tristate gates.

Gate
(ns)
Power dissipation (W)
Power delay product (fJ)

Inverter
0.065
16.2
1.053

NAND
0.078
16.2
1.2636

NOR
0.087
16.2
1.4094

Table 2: PFSCL Tristate gates based on switch transistor technique.

Gate
(ns)
Power dissipation (W)
Power delay product (fJ)

Inverter
0.145
16.2
2.349

NAND
0.575
16.2
9.315

NOR
0.395
16.2
6.399

Table 3: PFSCL Tristate gates based on sleep transistor technique.

Gate
(ns)
Power Dissipation (W)
Power delay product (fJ)

Inverter
0.105
8.1
0.85

NAND
0.148
8.1
1.199

NOR
0.107
8.1
0.867

It may be observed from Tables 1–3 that the power delay product values for PFSCL tristate circuit based on sleep transistor are better as compared to CMOS and switch-based PFSCL tristate circuits. Further, the overall power dissipation decreases by a percentage equal to the duty cycle of the Enable signal used to drive the circuit into the high impedance state in PFSCL sleep-based tristate circuit. The same behavior is not seen in CMOS and the switch-based PFSCL tristate circuits. Also, at hundreds of MHz frequencies, the dynamic power dissipation of CMOS circuits which increases proportionally with frequency is much greater than power dissipation of a comparable PFSCL circuit.

It may also be noted that in a case where multiple gates of switch-based PFSCL tristate circuits are connected to the same output node, the power dissipation increases by a factor equal to the number of gates attached to the node. This situation does not occur in sleep-based PFSCL and CMOS tristate circuits where only one of the gates is on. Therefore, in such a case, sleep-based PFSCL tristate circuits are the most appropriate choice

5. Conclusion

In this paper, two new design techniques to implement tristate PFSCL circuits have been proposed. The techniques are based on MOS switch and sleep transistor concepts. Different tristate circuits based on both techniques have been developed and simulated using 0.18 μm CMOS technology parameters. A performance comparison of the proposed circuits with the conventional CMOS circuit indicates that the tristate PFSCL circuits based on sleep transistor technique are more power efficient and have minimum power delay product values than the conventional CMOS and the switch based PFSCL ones.

References

D. J. Allstot, S. H. Chee, S. Kiaei, and M. Shrivastawa, “Folded source-coupled logic vs. CMOS static logic for low-noise mixed-signal IC's,” IEEE Transactions on Circuits and Systems I, vol. 40, no. 9, pp. 553–563, 1993.

A. P. Chandrakasan and R. W. Brodersen, Low Power Digital CMOS Design, Kluwer Academic Publishers, Boston, Mass, USA, 1995.

J. Yuan and C. Svensson, “New single clock CMOS latches and flip-flops with improved speed and power savings,” IEEE Journal of Solid-State Circuits, vol. 32, pp. 62–69, 1997.

U. Ko, P. T. Balsara, and W. Lee, “Low-power design techniques for high-performance CMOS adders,” IEEE Transactions on Very Large Scale Integration Systems, vol. 3, no. 2, pp. 327–333, 1995.

C. Nagendra, M. J. Irwin, and R. M. Owens, “Area-time-power tradeoffs in parallel adders,” IEEE Transactions on Circuits and Systems II, vol. 43, no. 10, pp. 689–702, 1996.

J. Kundan and S. M. Rezaul Hasan, “Enhanced folded source-coupled logic technique for low-voltage mixed-signal integrated circuits,” IEEE Transactions on Circuits and Systems II, vol. 47, no. 8, pp. 810–817, 2000.

M. Alioto and G. Palumbo, “Power-delay trade-offs in SCL gates,” in IEEE International Symposium on Circuits and Systems, pp. 249–252, May 2002.

M. Alioto, A. Fort, L. Pancioni, S. Rocchi, and V. Vignoli, “Positive-feedback source-coupled logic: a delay model,” in Proceedings of IEEE International Symposium on Cirquits and Systems, pp. 641–644, May 2004.

M. Alioto, L. Pancioni, S. Rocchi, and V. Vignoli, “Modeling and evaluation of positive-feedback source-coupled logic,” IEEE Transactions on Circuits and Systems I, vol. 51, no. 12, pp. 2345–2355, 2004.

M. Alioto, A. Fort, L. Pancioni, S. Rocchi, and V. Vignoli, “An approach to the design of PFSCL gates,” in IEEE International Symposium on Circuits and Systems (ISCAS '05), pp. 2437–2440, May 2005.

M. Alioto, L. Pancioni, S. Rocchi, and V. Vignoli, “Power-delay-area-noise margin trade-offs in positive-feedback source-coupled logic gates,” IEEE Transactions on Circuits and Systems. I, vol. 54, no. 9, pp. 1916–1928, 2007.

M. Alioto, L. Pancioni, S. Rocchi, and V. Vignoli, “Exploiting hysteresys in MCML circuits,” IEEE Transactions on Circuits and Systems II, vol. 53, no. 11, pp. 1170–1174, 2006.

D. Rennie and M. Sachdev, “Comparative robustness of CML phase detectors for clock and data recovery circuits,” in 8th International Symposium on Quality Electronic Design (ISQED '07), pp. 305–310, March 2007.

M. Shoji, CMOS Digital Circuit Technology, Prentice-Hall, Englewood Cliffs, NJ, USA, 1988.

N. Weste and K. Eshraghian, Principles of CMOS VLSI Design: A System Perspective, Addison-Wesley, Reading, Mass, USA, 1986.