Journal of Electrical and Computer Engineering

Volume 2013 (2013), Article ID 145314, 9 pages

http://dx.doi.org/10.1155/2013/145314

Research Article

Divide-by-Three Injection-Locked Frequency Dividers with Direct Forcing Signal

Antonio Buonomo and Alessandro Lo Schiavo

Seconda Università degli Studi di Napoli, Via Roma 29, 81031 Aversa, Italy

Received 9 April 2013; Accepted 14 June 2013

Academic Editor: Jose Silva-Martinez

Copyright © 2013 Antonio Buonomo and Alessandro Lo Schiavo. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Abstract.

Divide-by-three frequency dividers with direct forcing signal are analyzed, and the actual locking mechanism underlying their operation is highlighted. In particular, it is shown that the locking mechanism cannot be explained with the mixing between signals, as commonly made in the literature. An analytical procedure based on the averaging method is developed for solving the equation describing such dividers, and the first approximation to the oscillation in the locked states is predicted. The amplitude and phase of the output voltage in steady state as well as the locking range are derived in terms of the circuit parameters, obtaining useful design guidelines. The derived results are shown to be very close to SPICE simulations for a 0.13 um RF-CMOS process.

1. Introduction

Frequency dividers are key building blocks of RF integrated circuits, as they allow us to scale down the high frequency of the signal from the voltage controlled oscillator (VCO) to a relatively low frequency required for the phase locking in a Phase-Locked Loop (PLL). As an alternative to the widely used digital dividers, based on Current-Mode Logic (CML) flip flops [1], and to Miller dividers [2], some topologies of -CMOS analog dividers have been devised that allow higher operation frequencies with lower power consumption. These dividers are called Injection-Locked Frequency Dividers (ILFDs) as they rely on the well-known phenomenon of subharmonic synchronization (or injection-locking) that happens in a basic differential oscillator perturbed by an external periodic signal [3].

In applications, ILFDs with division ratios greater than two are often needed to reduce the overall power consumption and the chip area that the cascade of dividers with a low division ratio involves. Therefore, frequency dividers, able to divide by 3, 4, and more, were recently designed which, in addition, feature a wide locking range () needed in practical PLLs. Moreover, the division by an odd number, and in particular for three, can be a particularly advantageous solution in some designs, as in multiband frequency synthesizers [4, 5]. In particular, the use of a divide-by-three ILFD enables a simple architecture for dual-band operation, when the ratio between the frequencies is three, as it happens for W and K bands [6]. For this reason, designing low-voltage divide-by-three ILFDs with a wide locking range has become a topic of relevant interest [7–9].

To perform the divide-by-three function, a variety of designs suitable for operation at high frequencies have been proposed, which include particular circuit arrangements aimed mainly at widening the lock range. They are basically made by a differential oscillator and an injection circuit providing a current signal that perturbs the oscillator. In divide-by-three ILFDs with direct forcing of the injection signal, the current signal is injected directly in the oscillator across the -tank and the locking takes place according to a mechanism different from the mixing between signals [10], usually invoked to explain the process of frequency division [11–13]. The purpose of this work is to complete the investigation in [10] with the aim to provide useful results for the design of these dividers. Using the behavioral model introduced in [10], which consists of a nonlinear differential equation of the second order, and the procedure of solution of that equation, based on the method of averaging, we were able to find the amplitude and phase of the output voltage in steady state, and the locking range in explicit form as a function of the relevant circuit parameters. Then, the dependence of the circuit performances on the circuit parameters is investigated. The application of the derived formulas leads to results that are in good agreement with SPICE simulations for a 0.13 um RF-CMOS process. A preliminary review of the preexisting results is also given in order to show how their limitations are overcome by presented results.

2. Principles of Operation of Divide-by-Three Circuits

The first analog frequency divider based on a mixer and a band-pass filter (BPF) was proposed by Miller and its block diagram is shown in Figure 1(a) [2]. It is easy to verify that it can operate as a divide-by-two frequency divider. Upon multiplication of the input and output signals, the mixer generates components at and , where is the frequency of the output signal. If the former component is suppressed by the low-pass filter but the latter is not, then and, hence, .

(a)

(b)

(c)

Figure 1: (a) Model of the Miller divide-by-two ILFD [2]. (b) Model of a divide-by-three ILFD based on a divide-by-two ILFD [7]. (c) Model of a divide-by-three ILFD based on a frequency multiplier [8].

The combined effect of a mixing nonlinearity and of a band-pass filter has become the common characteristic of all divide-by-two injection-locked frequency dividers used in practical applications [14, 15]. General models to analyze injection-locked frequency dividers were presented in papers [11, 12], which implicitly assume that the divider operation is based on a mixing effect.

Divide-by-three circuits have been developed starting from the approach used for divide-by-two frequency dividers, even if some modifications were needed in order to obtain a division by a number different from two. The approach in [7] is based on the model in Figure 1(b) and employs a divide-by-two frequency divider in the feedback loop. The mixer generates components at and . The component is filtered out by the band-pass filter and the component is injected into the divide-by-two frequency divider. Thus, the output frequency can be derived as and, hence, . Consequently, the output frequency is locked at one-third of the input frequency.

However, the most widely used approach to realize a divide-by-three frequency divider exploits a circuit nonlinearity to produce a second harmonic of the output voltage, as shown in Figure 1(c) [8]. In this case, the input signal at frequency is mixed with the feedback signal at frequency to produce harmonic components at frequency . However, only the desired component at frequency passes through the band-pass filter, while all other harmonic terms are suppressed. Thus, leads to . Many improvements have been proposed in the literature, mainly aimed at widening the locking range through the use of additional inductors, even if in all the cases an input nonlinearity is present that performs a mixing between the input and the feedback signals.

Here, we show that a divide-by-three circuit can operate according to a different principle of operation, that does not employ a mixing between the input and the output signals, as it happens when a forcing signal is directly applied to the -tank. In the model in Figure 2, the input signal is added to the feedback signal and passes, even if attenuated, through the band-pass filter. Thus, the output signal has a frequency component at frequency in addition to its main component at frequency . If the feedback nonlinearity is a cubic polynomial, the feedback signal will have a component at frequency , which will pass through the filter. Thus, imposing , it results .

Figure 2: Model of a divide-by-three injection-locked frequency divider with a direct application of the forcing signal.

Note that the model in Figure 2 can be seen as a particular case of the general model of ILFDs, presented in [11] and shown in Figure 3(a), when the nonlinearities are set equal to and , and represents the transfer function of a band-pass filter, usually made of an -tank. Taking into account that the model in Figure 3(a) is equivalent to the circuit in Figure 3(b), let us simulate this circuit with , and , in order to verify that the proposed model is useful to implement a divide-by-three ILFD. The signal waveforms in Figure 4(a) show that the output signal, , has a fundamental component equal to one-third of the input frequency, and, thus, the circuit operates as a divide-by-three ILFD. Its frequency spectrum in Figure 4(b) confirms the presence of a third harmonic in the output signal, that is a component at frequency in addition to its main component at frequency .

(a)

(b)

Figure 3: (a) General model of an injection locked frequency divider and (b) its representation as forced -tank [11].

Figure 4: SPICE simulations of the circuit in Figure 3(b) with , ,  mA/V,  mA/V²,  mA/V²,  nH,  Ω,  fF,  V,  GHz. (a) Time waveforms of the input and output signals. (b) Frequency spectrum of the output signal. (c) Arnold tongues obtained by simulating the circuit in Figure 3(b) with and with .

Model in Figure 3(b) gives us also the possibility of easily comparing the case when the injection nonlinearity includes a mixing nonlinearity and the case when a mixing is not present. To this end, we calculated the locking ranges for the divide-by-three mode of operation of the equivalent circuit in Figure 3(b) with (corresponding to the block diagram in Figure 2), and then with (corresponding to the block diagram in Figure 1(c)). The results reported in Figure 4(c) not only show that both circuits can operate as a divide-by-three ILFD but also using the same value of , the locking range of the circuit without mixing, that is, , is wider than the other one. Thus, we can conclude that dividers can be efficiently realized without performing a mixing between the input and the output signals.

3. Circuit Analysis and Design

The divide-by-three circuit in Figure 5 performs the frequency division without involving a mixing between the input and output signals, but is characterized by the direct application of the forcing signal on the tank of the oscillator. The circuit is formed by the parallel connection of an -tank, an active circuit consisting of two complementary pairs of cross-coupled devices (Figure 6(a)) and an injection circuit consisting of two complementary MOS switches (Figure 6(b)). Thus, the current of the -tank consists of a component due to the active part and a component due to the injection circuit. In general, the current depends not only on the synchronization signal but also on the voltage and thus is written in the form .

Figure 5: Circuit diagram of a divide-by-three -CMOS frequency divider with a direct forcing signal.

(a)

(b)

Figure 6: (a) Active part of the ILFD in Figure 5; (b) injection circuit of the ILFD in Figure 5.

Analytical expressions of the functions and can be determined by assuming that the ILFD operates under a small-injection regime, so that the current applied to the -tank can be written as with and . SPICE simulations of the circuits in Figure 6 for show that the current can be well approximated by a cubic polynomial (Figure 7(a)) [16, 17]. On the other hand, the function , calculated through a finite difference approximation, can be modeled by a constant function (Figure 7(b)). Thus, the current applied to the -tank can be written as

and the circuit in Figure 5 is amenable to the block diagram in Figure 8, where is the -tank transfer function, and to the equivalent circuit in Figure 3(b). As the block diagram in Figure 8 is reducible to the diagram in Figure 2, we conclude that the circuit in Figure 6 is able to operate as a divide-by-three ILFD.

(a)

(b)

Figure 7: Current-voltage characteristics of the circuits in Figure 6. (a) Total current for . (b) Voltage-controlled transconductance . SPICE simulations are obtained by using BSIM3 transistor models (MOSIS-IBM 8RF 0.13  technology), with  V. Analytical models are obtained by using polynomial approximations and .

Figure 8: Block diagram of the injection locked frequency divider in Figure 5.

The main design parameter of a frequency divider is the locking range, which can be analytically related to the circuit parameters as shown below. The circuit in Figure 3(b) is described by

where is the resonant frequency of the -tank. Assuming that the circuit operates as a divide-by-three ILFD under the action of the signal , we seek a solution of (2) in the form where is the first harmonic of and the sum of the remaining harmonics. Also the current in the -tank is decomposed into a component equal to its first harmonic and a component equal to the sum of the remaining harmonics, that is,

Taking into account that the output harmonics of the nonlinearity depend slightly on the harmonics of the voltage , that is, , by virtue of (1) we obtain

Note that and represent the input and the output quantities, respectively, of the band-pass filter in the model in Figure 2, which are decomposed in the fundamental component at frequency and in the harmonic components. Equation (4) shows that the harmonic component of the input quantity of the filter has frequency , as shown in Figure 2.

By virtue of (3), (2) can be rewritten in the form

and can be decomposed into the following two equations for the fundamental and higher harmonics

We will first solve (7) for and, then, exploiting the solution of (7), we will solve (6) for . Thus, taking into account that the first term in (7) is greater than the second and third one, that is, , (7) can be reduced to

and its solution provides the harmonics of the output voltage, that is,

Note that, taking into account that with , (9) implies that the output voltage contains a component at frequency and a component at frequency , as represented in the block diagram in Figure 2.

By using (9) in (1), the expression of the current applied to the -tank is obtained:

Expression (10) allows us to calculate the fundamental harmonic of , that is , and in particular, the coefficients of cosine and sine Fourier components of the fundamental harmonic, that is,

with . It results in that

Taking into account that the third harmonic of the output voltage is quite smaller than the fundamental, that is , it is possible to simplify (12), obtaining

Once obtained the expression of in explicit form, or equivalently of and , (6) can be solved by using the averaging method [11, 18] and the following equations for the locked states are obtained:

Equation (13) reduces (14) to

where

It is interesting to observe that if , that is, if the circuit operates as a free-running oscillator, (16) predicts that the output oscillation frequency is different from the tank resonant frequency and it is equal to . This is a consequence of the known nonlinear effect of harmonics on the oscillation frequency [19]. Moreover, (16) highlights an unknown aspect of the frequency entrainment process, namely, that the action of the external signal on the oscillator manifests itself by a frequency deviation from the actual frequency of the free-running oscillation. Note also that (17) can be used to estimate the equivalent capacitance , which includes the device parasitics, starting from the free-running frequency.

Assuming that the frequency shift due to the harmonics does not significantly change in presence of the input signal, that is, assuming as a constant in (16), we can solve (15) and (16) for and in explicit form, obtaining

with

The values of for which a solution does exist are the values of for which the locking occurs. The minimum and the maximum values of define the output-referred locking range and are equal to

where

The input-referred locking range is equal to the output-referred locking range multiplied by the division ratio . Taking into account that , (21) provides a very simple expression of the locking range as a function of the active and passive circuit parameters, which can be usefully employed for the design of ILFD with direct forcing signal. Note that all the formulas based on the mixing principle predicts that the locking range is zero in this case [11–13].

4. Circuit Simulation

SPICE simulations of the circuit in Figure 5 were performed by using BSIM3 models of active devices in 0.13 m technology. Time waveforms of the input and output voltages, reported in Figure 9(a), demonstrated that the circuit under study can actually operate as a divide-by-three ILFD.

(a)

(b)

Figure 9: SPICE simulation of the circuit in Figure 5 obtained by using BSIM3 transistor models in MOSIS-IBM 8RF 0.13  technology and , ,   V,  nH,  Ω. (a) Voltages at the input and output terminals. (b) Frequency spectrum of the output voltage.

Moreover, SPICE simulations were performed to investigate the dependence of the locking range on the circuit parameters and to determine the accuracy of analytical expressions deduced in previous section. The locking region in the plane is reported in Figure 10(a) and the modification of the locking region as a function of the transistor sizes of the tank quality factor and of the inductor values is reported in Figures 10(b), 10(c), and 10(d), respectively. The comparison of the SPICE results with the results obtained by analytical expression (21), also reported in Figure 10, shows a good accuracy of (21), which can be effectively used to design the ILFD in Figure 5.

(a)

(b)

(c)

(d)

Figure 10: Locking regions for the divide-by-three ILFD in Figure 5, obtained by SPICE simulations (lines with circles) and by using analytical equations (lines without circles). For SPICE simulations, BSIM3 transistor models in MOSIS-IBM 8RF 0.13  technology with  V have been used. (a) Locking range as a function of the input amplitude ( nH,  Ω). (b) Locking range as a function of the transistor sizes (,  nH,  Ω). (c) Locking range as a function of the tank resistance (, ). (c) Locking range as a function of the ratio keeping the product constant ( nH 446.6 fF).

It is interesting to observe that, according to SPICE simulations and to the prediction of (21), the width of the frequency range of locking increases with the transistor size, which is proportional to and , but the center of the locking range moves toward lower frequencies due to the parasitic capacitances (Figure 10(b)). Moreover, the width of the locking range does not depend on the quality factor of the tank (Figure 10(c)) and, thus, it is not necessary to keep low the quality factor in order to widen the locking range as it happens in other ILFD topologies. Finally, we note that the increasing of the ratio for a constant product (Figure 10(d)) widens the locking range but shifts it toward lower frequencies due to nonlinear effects, as predicted by (17).

Finally, the phase relationship between the input and output signals was investigated. SPICE simulations reported in Figure 11 show that a wide variation is present when the input frequency varies within the locking range. Analytical results obtained by applying (19) and reported in Figure 11 show that presented formula provides an acceptable approximation to the numerical results. However, formulas are not able to predict a constant phase offset , that is, due to the reactive behavior of nonlinearities, which were here assumed to be memoryless. Thus, we conclude that, even if small discrepancies are present between numerical and analytical results, formulas are able to capture the main characteristics of the direct forcing injection, providing fairly accurate approximation to numerical results.

Figure 11: Phase difference between the input and output signals for the divide-by-three ILFD in Figure 5 with  nH and  Ω. SPICE simulations are obtained by using BSIM3 transistor models in MOSIS-IBM 8RF 0.13  technology with  V, , . Analytical results are obtained by using (19).

5. Conclusions

We have shown that in the injection-locked dividers wherein the external synchronization signal is applied directly to the -tank, the synchronization mechanism takes place according to a process that cannot be explained by the simple mixing between the input and output signals. This is the case of some divide-by-three circuits, of which we analyzed in detail a particular implementation. Then, a method for the approximate calculation of oscillation in the synchronous states was exposed that allows us to determine the amplitude and the phase of the oscillation and the interval of locking in explicit form as a function of the circuit parameters. These expressions, which are relatively simple and useful for design, provide sufficiently accurate results as shown by numerical simulations.

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