We are examining different configurations and circuit topologies for arithmetic components such as adder and compressor circuits using both symmetric and asymmetric workfunction FinFETs. Based on extensive characterization data, for the carry generation of a mirror full adder using symmetric devices, both leakage current and delay are decreased by 25% and 50%, respectively, compared to results in the literature. For the 14transistor (14T) full adder topology, both leakage and delay are decreased by 23% and 29%, respectively, compared to the mirror topology. The 14T adder topology, using asymmetric devices without any additional power supply, achives reduction in leakage current by 85% with a small degradation of 7% in delay. The compressor circuits, using asymmetric devices for one of the proposed configurations, achieve reduction in both leakage current and delay by 86% and 4%, respectively. All simulations are based on a 25 nm FinFET technology using the University of Florida UFDG model.
The demand for smaller and faster portable electronic equipment has forced the semiconductor technology to a sharp reduction in the minimum feature size from the micro to the nanometer regime [
The goal of this paper is to develop circuit topologies and configurations that lead to highperformance low leakage arithmetic components using symmetric fourterminal FinFETs. Also, we have developed a novel approach by applying back gate biasing techniques for asymmetric FinFETs without using any extra power supply to achieve ultralow leakage current, yet maintaining the high performance. Device and circuit characterization were performed in a SPICE simulation environment using the University of Florida doublegate device models (UFDG) [
Fourterminal FinFETs were extensively studied and analyzed in [
Device parameters for FinFET.
Parameter  Value 
 
Length of the channel ( 
25 nm 
Thickness of front/back gate oxide ( 
1 nm 
Thickness of the fin ( 
14 nm 
Height of the fin ( 
25 nm 
Work function ( 
4.6 eV 
Power supply ( 
1.2 V 
Channel doping (N_{BODY})  1 
4T FinFET device [
To demonstrate the effect of back gate biasing on the ON state current (
Data for 4T NFinFET.




−0.4  11.10  0.1 
−0.2  13.40  1.79 
0  15.70  33.10 
0.2  18.20  786 
0.4  20.80  21500 
Data for 4T PFinFET.




0.8  5.08  255 
1.0  3.74  29.20 
1.2  2.60  4.99 
1.4  1.62  1.87 
1.6  0.88  1.44 
Table
For PFinFET, Table
Back gate biasing technique is more beneficial for NFinFETs due to their dominance in the total leakage current in FinFET based digital circuits. On the other hand, the back gate of PFinFETs is more beneficial to use in SG configuration to achieve high driving capability and performance since the PFinFETs have lower subthreshold leakage current than their N counterparts.
The work function difference between the gate and the channel of a FinFET dictates the threshold voltage of the device. It is a function of the gate material and the doping concentration [
In order to demonstrate the effect of asymmetric work functions on leakage current, the N device has been characterized by changing the work functions value of the back gate in the model file in steps of 0.1 eV as shown in Table
Impact of asymmetric work functions on leakage current for N FinFET.
Back gate work function (eV)  VBG = 0 V  VBG = −0.2 V 

Front gate work function = 4.6 eV 


Symmetric ( 
33.10  1.79 
Asymmetric ( 
7.22  0.42 
Asymmetric ( 
2.03  0.12 
In addition, we have characterized both N(P) FinFETs by increasing (decreasing) the work function of the back gate by 0.2 eV with respect to their symmetric values (
The findings from simulation results at the device level dictate some design strategies to develop optimized circuit topologies. These strategies are as follows.
Back gate biasing is more beneficial for NFinFETs due to their leakage current dominance.
The back gates of PFinFETs are short gated to their front gates to improve drivability with negligible impact on the circuit leakage current.
Applying asymmetric devices is an alternative design strategy to achieve significantly lower leakage current and to avoid the use of extra power supply for gate biasing.
In this section, we will present four possible configurations of full adders: mirror, 14T, transmission gate based, and PTL based. The mirror architecture is segmented into two subsections, the carry generation circuit and the complete full adder. The reason for addressing the carry generation circuit separately is for the purpose of comparison with similar work proposed in the literature. This will be followed by comparison between the circuit metrics extracted from simulation for all topologies with emphasis on leakage current. Finally, we discuss the impact of process variations on the extracted metrics.
In [
(a) The IG/LP mode of the symmetric mirror full adder, (b) the IG/LP mode of the asymmetric mirror full adder.
The circuit with transistor widths of 25 nm was simulated for a fanout of 4 (FO4) using UFDG device model. One fanout is represented by an inverter with transistors short gated; that is, both the front and back gates are tied together. Delay was estimated for the worst case scenario, while the static power dissipation is an average value for all possible input combinations applied to the carry logic section of the mirror full adder based on the research work found in [
Results for the carry circuit.
IG/LP mode  Symmetric 
[ 
Asymmetric 


16.42  22.10  2.81 

11.94  23.88  13.63 
Static power * delay (yJ)  235.26  633.30  45.96 
Our work also covers asymmetric IG/LP carry logic circuit with
In this section, we present characterization data for the complete full adder circuit, shown in Figure
Results for the complete mirror full adder.
IG/LP mode  Symmetric 
Asymmetric 


49.85  6.24 

37.05  39.52 
Static power * delay (zJ)  2.21  0.30 
A small transistor count adder has been proposed based on the traditional CMOS technology in [
(a) Optimal configuration of the symmetric 14T full adder circuit, (b) optimal configuration of the asymmetric 14T full adder circuit.
Simulations were conducted for both symmetric and asymmetric FinFETs based on the optimal configuration of the 14T full adder circuit. Results shown in Table
Results for the 14T full adder.
Optimalmode  Symmetric 
Asymmetric 


38.47  5.85 

24.03  28.52 
Static Power * delay (zJ)  1.10  0.20 
An optimal configuration of the full adder based on transmission gates is proposed, as shown in Figure
(a) Optimal configuration for symmetric TG full adder, (b) optimal configuration for asymmetric TG full adder.
Simulations were conducted for both symmetric and asymmetric FinFETs based transmission gates full adders. Results shown in Table
Results for the TG full adder.
Optimal mode  Symmetric 
Asymmetric 


74.79  11.56 

26.56  24.79 
Static power * delay (zJ)  2.38  0.34 
The optimal configuration of a pass transistor logic (PTL) full adder cell based on fourterminal FinFET is shown in Figure
(a) Symmetric pass transistor logic full adder, (b) asymmetric pass transistor logic full adder.
Simulations were conducted for symmetric and asymmetric FinFETs based on the pass transistor logic full adder cell. Results shown in Table
Results for the PTL full adder.
Optimal mode  Symmetric 
Asymmetric 


196.35  11.42 

22.50  27.19 
Static power * delay (zJ)  5.30  0.37 
In Table
Comparison of full adder circuits.
Topology 


Static power * delay (zJ)  Number of transistors  Dynamic energy (aJ) 

Mirror  49.85  37.05  2.21  24  1206 
14T  38.47  24.03  1.10  14  242 
TG  74.79  26.56  2.38  26  1191 
PTL  196.35  22.5  5.3  20  500 
In this section, we demonstrate the impact of the variations of fin geometrical parameters, namely, the fin height (
Impact of the fin height and fin thickness on delay and leakage current in 14T full adder.
14T topology 




40.40  23.99 

36.55  24.06 

42.32  23.93 

34.62  24.10 

79.94  23.85 

18.48  24.19 
We also swept the value of the supply voltage
Impact of voltage variation on leakage current for the 14T full adder.
Impact of voltage variation on delay for the 14T full adder.
The multioperand addition involved in the summation of partial products is one of the most expensive operations in a multiplier [
A 3 : 2 compressor takes 3 inputs
3 : 2 compressor block.
The compressor is governed by the following equation [
The logic decomposition of the 3 : 2 compressor shown in Figure
Logic decomposition of 3 : 2 compressor.
The equations supporting this architecture are shown below [
Three different topologies of XOR and MUX blocks are chosen from the literature based on CMOS technology. They will be implemented based on symmetric and asymmetric 4T FinFETs in this paper as described in the following scenarios.
The Shorted Gate/Low Power (SG/LP) transmission gatebased MUX shown in Figure
(a) Symmetric SG/LP transmission gatebased FinFET MUX, (b) asymmetric SG/LP transmission gatebased FinFET MUX.
(a) Symmetric skew free topology of FinFET XOR, (b) asymmetric skew free topology of FinFET XOR.
The SG/LP transmission gatebased MUX block is still used. However, since the critical path which dictates the overall delay consists of only XOR blocks, and due to the fact that the overall area for whole compressor is dictated by the XOR block, it is more beneficial to use these blocks in configurations which are faster and have better overall area than the skew free topology. Hence, in this scenario, the SG/LP configuration of transmission gate topology of FinFET XOR shown in Figure
(a) Symmetric SG/LP configuration TG topology of FinFET XOR, (b) asymmetric SG/LP configuration TG topology of FinFET XOR.
In order to achieve further improvement in speed and area compared to the XOR topology utilized in Scenario
(a) Symmetric PTL XOR cell, (b) asymmetric PTL XOR cell.
Comparison between different scenarios for 3 : 2 symmetric FinFET compressor.
Scenario 


Static power * delay (zJ)  Number of transistors 

1  76.63  31.53  2.89  30 
2  182.51  26.99  5.91  22 
3  137.68  23.47  3.87  18 
As discussed earlier, asymmetric devices achieved a significant reduction in leakage current with a small delay penalty for most configurations except for a few where a slight improvement of the delay performance was obtained. In addition, the use of these devices did not require the need for additional power supplies for back gate biasing.
Comparison between different scenarios for 3 : 2 asymmetric FinFET compressor.
Scenario 


Static power * delay (yJ)  Number of transistors 

1  10.62  31.47  401  30 
2  19.92  31  741  22 
3  17.25  24.56  508  18 
A 4 : 2 compressor has five inputs and three outputs, as shown in Figure
4 : 2 compressor block.
The 4 : 2 compressor is governed by the following equation [
Traditional implementation of 4 : 2 compressor.
Logic decomposition of 4 : 2 compressor.
The following equations govern the outputs of this structure. Consider
Comparison between different scenarios of 4 : 2 symmetric FinFET compressor.
Scenario 


Static power * delay (zJ)  Number of transistors 

1  149.93  48.68  8.75  60 
2  186.45  37.18  8.31  44 
3  119.77  32.99  4.74  36 
Simulations were also conducted for asymmetric devices with a bias voltage of
Comparison between different scenarios of 4 : 2 asymmetric FinFET compressor.
Scenario 


Static power * delay (zJ)  Number of transistors 

1  20.36  46.94  1.14  60 
2  27.23  40.86  1.33  44 
3  19.35  34.52  0.80  36 
In this paper, fourterminal FinFETs have been extensively analyzed with the goal of reducing subthreshold leakage current. We applied both back gate biasing and asymmetric work functions, which are two effective methods to achieve ultralow subthreshold leakage current level in FinFETs. We have used these powerful techniques to design optimized circuits for arithmetic components, namely, a full adder and compressor circuits in different configurations. Our simulation results show that by applying asymmetric work functions, the subthreshold leakage current can be reduced significantly with low delay penalty and we can also avoid the use of additional power supply. However, one must also consider that asymmetric circuits are more costly to fabricate since careful adjustment of the doping profiles is required for both sides of the same FinFET.