Temperature-Dependent Physical and Memory Characteristics of Atomic-Layer-Deposited RuOx Metal Nanocrystal Capacitors

1 Thin Film Nano Tech Lab., Department of Electronic Engineering, Chang Gung University, 259 Wen-Hwa 1st Road, Kwei-Shan, Tao-Yuan 333, Taiwan 2 Material and Chemical Research Laboratories, Industrial Technology Research Institute, Hsinchu 310, Taiwan 3 Australian Key Centre for Microscopy and Microanalysis, University of Sydney, NSW 2006, Australia 4 Department of Materials Science Engineering, National Taiwan University, Taipei 106, Taiwan


Introduction
Memory devices with a low program/erase voltage operation and a better scalability with excellent endurance/retention are required for future nanoscale high-performance flash memory applications. According to the International Technology Roadmap for Semiconductors (ITRS) on a 20 nm technology node [1], the scaling of tunneling oxide thickness is one of the key issues for conventional floating gate memory devices. Recently, many nanocrystals with the advantages of many energy levels as well as high charge-trapping probability, high-speed with a low program/erase voltage operation, high scalability potential, excellent endurance, and data retention, and so forth, have been reported [2][3][4][5][6][7][8][9][10]. Due to higher density of states around the Fermi level, discrete charge storage in the nanocrystals and stronger coupling with conduction channel, the thickness of tunneling oxide can be reduced for metal or metal oxide nanocrystal memory devices. To solve the scaling problems, high-κ tunneling barriers such as HfO 2 , and Al 2 O 3 are also reported by many researchers. The metal nanocrystals embedded in high-κ tunneling barriers with high thermal stability (∼1000 • C) are needed in future nanoscale nonvolatile memory applications, that can follow the conventional complementarymetal-oxide-semiconductor (CMOS) process line. Recently, the TiN nanocrystal memory devices were reported with process temperatures of 1000 • C [7] and ∼1050 • C [10]. Due to the high melting point (∼1200 • C [11]) and high work function (Φ m > 4.7 eV) of ruthenium oxide (RuO x ) materials, this nanocrystal can be also used as a chargestorage node in nanoscale flash memory device applications. Furthermore, the RuO x material can be deposited 2 Journal of Nanomaterials by atomic-layer-deposition (ALD), which will be useful in future applications. In this study, annealing dependence of the atomic-layer-deposited RuO x nanocrystals embedded in the high-κ HfO 2 /Al 2 O 3 layers in an n-Si/SiO 2 /HfO 2 /RuO x /Al 2 O 3 /Pt memory structure has been investigated. After post-deposition annealing (PDA) temperature ranges from 850-1000 • C, the Hf-silicate layer at the SiO 2 /HfO 2 interface is formed. The memory devices with a low voltage operation (<5 V) and good memory characteristics are obtained after a high PDA of 1000 • C.

Experimental and Methods
n-Type Si (100) substrate with a doping of 1 × 10 17 /cm 3 was cleaned by an RCA process. To remove native oxide from the Si surface, the wafer was dipped in HF solution. After cleaning Si wafers, the tunneling oxide (SiO 2 ) with a nominal thickness of 3 nm was grown by a rapid thermal oxidation (RTO) process at a substrate temperature of 1000 • C for 15 s. The oxygen gas (O 2 ) was used for oxidation. The high-κ HfO 2 film with an as-deposited thickness of 2 nm was grown for a wetting layer by ALD. The high-κ HfO 2 film can be used as a part of tunneling oxide. The stack tunneling oxide layers are SiO 2 and HfO 2 films, which can also improve memory performance. Then, the RuO x metal layer with an as-deposited thickness of ∼2 nm was grown by ALD using a diethyl-cyclopentadienyl ruthenium [Ru(EtCp) 2 ] precursor at a substrate temperature of 350 • C. The precursor temperature was 100 • C. The high-κ Al 2 O 3 film with a thickness of 20 nm was deposited in situ for a blocking oxide by ALD. The H 2 O precursor was used for oxygen content. The description of the deposition of high-κ and metal oxide films by ALD can be found in our previous study [12]. To form the RuO x nanocrystals from a RuO x nanolayer, a PDA process with the temperature ranges from 850 to 1000 • C for 1 min in N 2 (90%) + O 2 (10%) gas mixtures by a rapid thermal annealing (RTA) process was performed. To maintain the quality of the high-κ Al 2 O 3 film during the RTA process, a small amount (10%) of oxygen gas was used during the annealing process. For comparison, the pure Al 2 O 3 film as a charge-trapping layer was also deposited on a SiO 2 /Si substrate. The thickness of the Al 2 O 3 film was 20 nm. The Al 2 O 3 charge-trapping layer was annealed at 900 • C for 1 min. in N 2 ambient by the RTA process. A platinum (Pt) metal gate electrode with a gate area of 1.12 × 10 −4 cm 2 was fabricated by using a shadow mask. A schematic view of the RuO x metal nanocrystal capacitors is shown in Figure 1. The RuO x metal nanocrystals are embedded in the high-κ HfO 2 /Al 2 O 3 films. Table 1 shows the thicknesses and electrical characteristics of the RuO x nanocrystal memory capacitors. To confirm the size and microstructure of the RuO x nanocrystals, highresolution transmission electron microscopy (HRTEM) with an operating voltage of 300 kV and a resolution of 0.17 nm was carried out. To investigate the chemical bonds of Si-O, Hf-O, Ru-O, and Al-O signals, X-ray photo-electron spectroscopy (XPS) was performed. Memory characteristics such as capacitance-voltage (C-V) hysteresis, current densityvoltage (J-V), retention, and endurance, and so forth, were  investigated using an HP 4284A LCR meter and HP 4156C semiconductor measurement analyzer.

Results and Discussion
The thicknesses of the as-deposited dielectric layers are verified by cross-sectional HRTEM images, as shown in Figure 2(a). The as-deposited film is investigated for comparison. The thicknesses of SiO 2 , HfO 2 , RuO x , and Al 2 O 3 layers are 3, 2, 2, and 20 nm, respectively, for the as-deposited film. The RuO x metal layer shows crystalline, while both high-κ HfO 2 and Al 2 O 3 films appear amorphous in nature. The elemental compositions of all layers are observed by energy dispersive X-ray spectroscopy (EDS) with a spot size of 0.5 nm in a diameter and a spacial resolution of ∼1 nm (Figure 2(b)). The numbers indicated on the EDS spectra correspond to the numbers on the TEM image. The peak elemental compositions of hafnium (Hf), ruthenium (Ru), oxygen (O) and aluminum (Al) atoms are 23.6, 3.5, 60.3, and 37.5 at %, respectively. It is estimated that the SiO 2 , HfO 2 and Al 2 O 3 films are closely stoichiometric for the asdeposited one. After annealing at 850 • C (sample: S1), the RuO x nanolayer displayed the nanocrystals (Figure 2(c)). The peak elemental compositions of the Hf, Ru, O, and Al atoms are 24.5, 17.7, 59.5 and 39.9 at %, respectively ( Figure 2(d)). The atomic concentration of Ru is increased from 3.5 at % to 17.7 at % after the annealing process. It is speculated that this higher atomic concentration of Ru after the annealing process may be due to both Rurich nanocrystal formation, and higher thickness from 2-3 nm. Furthermore, the atomic concentrations of Si and Hf atoms at a beam position of 4 are 33.2 and 13.5 at %, respectively, for the annealed memory capacitors, and those values are 29.9 and 6 at % for the as-deposited capacitor. Enhanced Si and Hf atoms at the SiO 2 /HfO 2 interface can be explained by diffusion of Hf and Si atoms after the annealing process. This is due to the Hf-silicate (HfSi x O y or simply HfSiO) formation at the SiO 2 /HfO 2 interface, which has been also confirmed by subsequent XPS measurement later. The atomic concentrations of Al and Hf at a beam position of 6 are 8.1 and 24.7, respectively, for the annealed memory capacitors, while those values are 6.1 and 24 for the as-deposited capacitors. The atomic concentrations are enhanced (slightly) after the annealing process. It indicates    that the Hf and Al atoms are also diffused after the annealing process which can also form HfAl x O y at the HfO 2 /Al 2 O 3 interface or in the vicinity of the RuO x nanocrystals. The thicknesses of SiO 2 , HfO 2 , and Al 2 O 3 layers are found to be 3.5, 1, and 17 nm, respectively (Figure 3(a)). The thickness of RuO x nanocrystal is approximately 3 nm. Total physical thickness of the stack tunneling oxides including SiO 2 , HfSiO, and HfO 2 layers is 4.5 nm, which is one of the important key areas to improve the memory characteristics. The thickness of SiO 2 layer is slightly (0.5 nm) increased    compared to that of the as-deposited one. The thicknesses of HfO 2 and Al 2 O 3 films are reduced (2-1 nm and 20-17 nm) compared to that of the as-deposited one, due to both the nanocrystal formation and densification of the films. All of the films including HfO 2 , RuO x , and Al 2 O 3 show crystalline after the annealing process. The thickness of SiO 2 is increased (3.5-4 nm) by increasing the annealing temperatures from 850 • C to 1000 • C ( Figure 3 and Table 1), due to both the oxygen diffusion and HfSiO formation at the SiO 2 /HfO 2 interface. The thickness of SiO 2 layer including HfSiO film Journal of Nanomaterials 5 10 nm is approximately 4 nm at a PDA of 1000 • C. The thickness of stack tunneling oxide including SiO 2 , HfSiO, and HfO 2 layers nm is approximately 5 nm. It is expected that the thickness of the HfSiO layer is about 0.5-1.0 nm. The thickness (∼3 nm at 850 • C to ∼4 nm at 1000 • C) and average diameter (∼7 nm at 850 • C to ∼11.5 nm at 1000 • C) of the RuO x metal nanocrystals are also increased with an increasing in the annealing temperature up to 1000 • C (sample: S4), due to the agglomeration or nanotwin formation after high temperature process. The Si and metal nanotwin formations after the annealing process were also reported by Wang et al. [13]. Figure 4 shows a plane-view TEM image of the RuO x nanocrystals in an n-Si/SiO 2 /HfO 2 /RuO x /Al 2 O 3 /Pt memory structure at a PDA of 850 • C (sample: S1). The RuO x nanocrystals are observed clearly. The average diameter is approximately 7 nm, which is larger than that of the crosssectional TEM image in Figure 2(c) (diameter: ∼4 nm) due to the different crystal orientations or image captured at different positions. The nanocrystals are like a circular disk and the diameters are varied from 4-10 nm. Figure 5 shows the diameter and density of the RuO x metal nanocrystals with different annealing temperature ranges from 850 • C-1000 • C. The density of the RuO x nanocrystals is calculated from the plane-view TEM images. The density of the RuO x metal nanocrystals is high: 1.5 × 10 12 /cm 2 at a PDA of 850 • C; 0.7 × 10 12 /cm 2 at a PDA of 1000 • C. A single RuO x nanocrystal with different annealing temperatures is also shown in the inset of Figure 5. At a PDA of 1000 • C, the nanocrystals are difficult to observe clearly on a plane-view TEM image because of crystalline Al 2 O 3 film. It suggests that the density of the RuO x metal nanocrystals decreases (slightly) with increasing the annealing temperatures due to the agglomeration of multiple nanocrystals. The nanocrystal sizes are varied from 4-10 nm, 4-12 nm, 4-17 nm, and 5-18 nm for the PDAs of 850 • C, 900 • C, 950 • C, and 1000 • C, respectively (data not shown). The average diameters are from 7-11.5 nm for the annealing temperatures at 850 • C to 1000 • C. The nanocrystal size distribution is broad with increasing the annealing temperature. However, the memory characteristics are very promising for future nanoscale nonvolatile memory applications. Furthermore, the compositions of the RuO x metal nanocrystals are explained by XPS below. Figure 6(a) shows the Ru3d spectra with different annealing temperatures. The RuO x metal nanocrystals show the Ru3d 5/2 and Ru3d 3/2 doublets. At a PDA of 850 • C (sample: S1), the peak binding energies of the Ru3d 5/2 and Ru3d 3/2 electrons are 281.7 eV and 285.9 eV, respectively. The peak binding energies are quite similar 281.7-281.5 eV for the Ru3d 5/2 electrons, and 285.9-285.7 eV for the Ru3d 3/2 electrons, with increasing annealing temperatures from 850-1000 • C. The peak fittings of the Ru3d 5/2 core level electrons are performed by Shirley background subtraction and Gaussian/Lorentzian functions at a PDA of 1000 • C ( Figure 6(b)). The RuO 3 peak is located at 281.5 eV. A negligible intensity of the RuO 2 and RuO 4 peak is observed. The binding energy peak positions and the separation between the doublets (4.0-4.2 eV) indicate the presence of the RuO x nanocrystals. Zhang et al. [14] reported that the peak binding energies of the Ru3d 5/2 electrons for Ru and RuO 2 elements were 280.6 eV and 281.6 eV, respectively. Kaga et al. [15] reported that the peak binding energies of the Ru3d 5/2 electrons are 280 eV for the Ru, and 280.8 eV for the RuO 2 films. Basically, the RuO 3 element is almost unchanged up to an annealing temperature of 1000 • C due to the high thermal stability of the RuO x nanocrystals in the memory capacitors. Figure 7(a) shows the Hf4f peaks with different annealing temperatures. The peaks are located at the Hf4f 7/2 and Hf4f 5/2 . These Hf4f doublet peaks originate from the pure HfO 2 or Hf-silicate film. The peak binding energies are 17-16.7 eV for the Hf4f 7/2 electrons, and 18.6-18.4 for the Hf4f 5/2 electrons with different annealing temperatures from 850-1000 • C (samples: S1-S4). The shift of the Hf peak toward higher binding energy is attributed to both the formation of the Hf-silicate and Hf-aluminate films, which    is ∼0.3 eV higher than that of pure HfO 2 film (16.7 eV [16]). Figure 7(  Clockwise capacitance-voltage (C-V) hysteresis characteristics of the RuO x metal nanocrystal memory capacitors with different sweeping gate voltages (V g ) at a PDA of 950 • C (sample: S3) are shown in Figure 8(a). The C-V measurement frequency was 1 MHz. Both hold and delay times were 0.1 s during C-V measurement. A hysteresis memory window of ΔV ≈ 4.2 V at a small sweeping gate voltage of V g = ±3 V is observed. The hysteresis memory window increases by increasing the sweeping gate voltages. Due to the high density of the RuO x metal nanocrystals, a large memory window of ΔV ≈ 10.8 V at a sweeping gate voltage of V g = ±7 V is obtained. The electron-(or hole-) trapping density under positive and negative gate voltages can be calculated using this equation below: nanocrystals are like a core-shell structure, that is, Ru-rich is inside the nanocrystal and oxygen-rich is outside the nanocrystal. So annular region of the nanocrystals will be oxygen-rich, where Hf or Al atoms will be mixed with Ru atoms. So the oxygen vacancy (positive-type defects) could be realized inside the nanocrystal and oxygen-rich (negativetype defects) could be realized on the boundary of the nanocrystal. As a consequence, the positive-type defects can trap the electrons and the negative-type defects can trap the holes. It is expected that the area covered by the annular 8 Journal of Nanomaterials region of the nanocrystals should be larger than the core area of the nanocrystals. It is believed that the holes will be trapped in the annular region while the electrons will be trapped in the core region of the nanocrystals. Considering the nanocrystal density of 0.8 × 10 12 cm −2 at a PDA of 950 • C, one RuO x nanocrystal can trap 23 electrons and 33 holes under the gate voltages of +7 V and −7 V, respectively. The hysteresis memory windows as well as electron-(or hole-) trapping density can be varied with sweeping gate voltages and different annealing temperatures, as shown in Figure 8( (Figure 8(b) and Table 1). Even though the high-density RuO 3 nanocrystals are observed at a PDA of 850 • C but the smallest memory window is observed as compared to that observed for other high temperature annealing processes. It may be due to both the higher equivalent oxide thickness (EOT = 8.9 ± 0.5 nm), as shown in Figure 9, and the unwanted defects remained in the RuO 3 nanocrystals at low annealing temperature (850 • C). The EOT decreases (slightly) with increasing PDA up to 950 • C, due to densification of the layers. But the EOT is increased at a PDA of 1000 • C due to a thicker stack tunneling oxide (∼5 nm). A minimum EOT of 7.9 ± 0.5 nm is observed at a PDA of 950 • C. The memory window at 1000 • C is also lower as compared to that of both annealing temperatures of 900 • C and 950 • C due to the higher EOT, the lower density of the RuO x nanocrystals and higher leakage current, which will be discussed below. At a PDA of 900 • C and 950 • C, a large hysteresis memory window of >14.0 V is observed under a sweeping gate voltage of ±10 V due to both the lower EOT (7.9 ± 0.5 nm) and the RuO x nanocrystals composed with RuO 2 and RuO 3 elements (data not shown). A memory window of 0.9 V is also observed under a small sweeping gate voltage of ±1 V. The large memory window and high electron-(or hole-) trapping density of the memory devices under a low voltage operation can be used in future multi-level-charge (MLC)-trapping flash memory device applications, which has been explained below.
The C-V hysteresis indicates that the charge can be trapped in the RuO x nanocrystals under a small positive gate voltage and the trapped charges can be erased under a small negative gate voltage. The electric fields across layer-bylayer under the external gate voltages (V g ) can be explained below. Considering the memory device under programming mode, the stack voltage, V stack (=V g − V FBN − ψ s ) across the memory structure can be written by where ψ s is the surface potential at the SiO 2 /Si interface, V SiO2 is the voltage across the SiO 2 tunneling layer (i.e., SiO 2 and HfSiO), V HfO2 is the voltage across the HfO 2 layer, V RuOx is the voltage across the RuO x nanocrystal layer, and V Al2O3 is the voltage across the blocking oxide (Al 2 O 3 ). The V FBN is about +0.05 V for our device. The surface potential can be written as Electric field, E (MV/cm) the doping density in n-type Si, n i (=1.45 × 10 10 cm −3 ) is the intrinsic carrier concentration of Si. Using those above values, the ψ s is 0.41 V. From Gauss's law of electrostatics on layer-by-layer structure, the boundary condition can be written as follows: The ε SiO2 , ε HfO2 , ε RuOx , and ε Al2O3 are the relative permittivities of the SiO 2 , HfO 2 , RuO x nanocrystal, and Al 2 O 3 layers, respectively. The E SiO2 , E HfO2 , E RuOx , and E Al2O3 are the electric fields across the SiO 2 , HfO 2 , RuO x nanocrystal, and Al 2 O 3 layers, respectively. The electric fields across the SiO 2 , HfO 2 , and Al 2 O 3 layers can be obtained from (2) and (4), where the t SiO2 , t HfO2 , t RuOx , and t Al2O3 are the thicknesses of the SiO 2 , HfO 2 , RuO x nanocrystal, and Al 2 O 3 layers, respectively. Total series capacitance (C total ) at accumulation region can be written as where ε 0 (=8.85 × 10 −14 F/cm) is the free space permittivity. The effective permittivity of the tunneling oxide (SiO 2 ) is higher than that of a pure SiO 2 layer (ε SiO2 = 3.9). It suggests that the Hf-silicate layer at the HfO 2 /SiO 2 interface is formed after the annealing process, due to the Hf and Si atom diffusion which is also explained by EDX and XPS analyses. Using those relative permittivity values in (5), (6), and (7), the electric fields have been calculated under positive gate voltages of V g = +10 V or +5 V on the Pt gate electrode. The electric fields versus PDA temperatures are plotted as shown in Figure 10. The electric field across the SiO 2 layer (E SiO2 ) is higher than 8 MV/cm under an operation voltage of +10 V for all annealing temperatures. Under a gate voltage of +5 V, the E SiO2 is ∼4 MV/cm. It indicates that the modified Fowler-Nordheim (F-N) tunneling mechanism plays a role to trap electron in the RuO x nanocrystals. The electric field across the HfO 2 layer is smaller ∼2 MV/cm but the conduction band offset [ΔE = (E c ) Si − (E c ) HfO2 = 4.05 eV − 2.35 eV = 1.7 eV] between the Si and HfO 2 conduction layers is also smaller. The electrons can be tunneled easily through the HfO 2 layer. The electric field is decreased (slightly) with increasing the PDA temperature, due to the higher thickness and permittivity of the SiO 2 layer. It is noted that the electric field across the high-κ Al 2 O 3 layers is much smaller than the electric field across the SiO 2 layer. In this case, the electrons are tunneled through the tunneling oxide layer and the charges are trapped in the RuO x metal nanocrystals under a low voltage operation. When we apply the negative gate voltage on Pt gate electrode then the electric field across the tunneling oxide layer (E SiO2 ) is also higher than that of the blocking oxide layer (E Al2O3 ). First, the trapped electrons will be tunneled back from the RuO x nanocrystals to the Si conduction layer. Second, the holes will be tunneled from the Si valence band to the RuO x nanocrystals. So, the large memory window is observed due to the electron and hole traps under positive and negative gate voltages, respectively, on the gate electrode. Figure 11 shows the variation of leakage current density with different annealing temperatures. The leakage current density of the RuO x nanocrystal memory capacitors is higher than that of the pure Al 2 O 3 charge-trapping layers due to the RuO x nanocrystal formation. The leakage current increases with increasing the PDA temperatures, due to the nanocrystal formation and outdiffusion of RuO x metal into the high-κ Al 2 O 3 blocking oxide. Furthermore, the crystallization of the Al 2 O 3 film can also play a role to increase leakage current. The formation of crystallites may result in increased leakage currents along grain boundaries of the Al 2 O 3 films after high temperature annealing process. The breakdown voltage of the RuO x nanocrystal memory capacitors decreases with increasing the PDA temperatures, due to higher leakage current. It is also believed that the hysteresis memory window at a PDA of 1000 • C is lower as compared to that of 950 • C, due to a higher leakage current. It implies that the hysteresis memory window can be limited by gate leakage or backtunneling current, and also by design of memory structure. Figure 12(a) shows the excellent program/erase endurance characteristics under a small program/erase voltage of ±5 V and a pulse width of 200 ms for a PDA of 1000 • C.
An initial memory window is 5.6 V and it is 5.5 V after extrapolation of 10 4 cycles. A small memory window loss of ∼2% is observed after 10 6 cycles. Figure 12(b) shows the variation of the flat-band voltage with retention time at a PDA of 1000 • C. The program/erase voltage is ±5 V and pulse width is 200 ms. To read the data (i.e., V FB ) with elapsed time under programming/erasing conditions, the capacitance is measured at a read voltage of 0.1 V and the capacitance transferred to the V FB . An initial memory window is 5.6 V, and it is 4.8 V at a room temperature (RT: 25 • C) and 4.3 V at 85 • C after extrapolation of 10 years data retention. A small charge loss of ∼14% at RT (∼23% at 85 • C) is observed after 10 years of retention time. A small charge loss and large memory window of the RuO x nanocrystal memory capacitors under a small program/erase voltage of ±5 V are due to both the deep-level charge trap in the RuO x nanocrystals and the thicker (∼5 nm) tunneling oxide layer at a PDA of 1000 • C, which is very useful for future nanoscale nonvolatile memory applications.

Conclusions
The RuO x metal nanocrystals in n-Si/SiO 2 /Hf-silicate/ HfO 2 /RuO x /Al 2 O 3 /Pt capacitors with different annealing temperatures from 850-1000 • C have been investigated by using HRTEM, EDX, and XPS measurements. An average diameter of the RuO x metal nanocrystals increases from 7-11.5 nm and the density decreases from 1.5 − 0.7 × 10 12 cm −2 with increasing PDA temperatures from 850 • C to 1000 • C, due to agglomeration of multiple nanocrystals. The isolated nanocrystals are observed by plane-view TEM images. Due to the diffusion of the Si and Hf atoms at the HfO 2 /SiO 2 interface during the annealing process, the Hf-silicate layer is confirmed by both XPS and electrical measurements. The RuO x metal nanocrystals with a high-density (>1 × 10 12 /cm 2 ), large memory window (>5 V) at a small gate voltage operation (<5 V), and a small EOT (∼9.0 nm) are obtained. A good endurance of ∼10 6 cycles and a large memory window of ∼4.3 V with a small charge loss of ∼23% at 85 • C after extrapolation of 10-year data retention are obtained, which can be useful in future low voltage operated nanoscale nonvolatile memories.