Multifunctional logic gate devices consisting of a nanodot array are studied from the viewpoint of single electronics. In a nanodot array, the dots come in a random variety of sizes, which sometimes has a negative effect on the performance of electrical device applications. Here, this feature is used in a positive sense to achieve higher functionality in the form of flexible logic gates with low power consumption in which the variability of logic functions is guaranteed. Nanodot arrays with two input gates and one control gate in a variety of arrangements are considered, in which the two-input logic functions (such as NAND, NOR, or exclusive-OR (XOR) gates) are selected by changing the voltage applied to the control gate. To ensure the flexibility of the device, it is important to guarantee the performance with any one of the six important logic functions: NAND, AND, NOR, OR, XOR, and XNOR. We ran a selection simulation using a nanodot array consisting of six nanodots with different dot arrangements to clarify the relation between the variability of the logic functions and the dot arrangements.

Single-electron devices (SEDs) are an attractive alternative for future large-scale integrated (LSI) circuits because of their small size and very low power consumption [

Miniaturization is a problem that also affects metal-oxide-semiconductor (MOS) field-effect transistors (FETs) because it is difficult to suppress the fluctuation of their sizes, when the size is less than 10 nm [

The simplest SED is a single-electron transistor (SET) that has only one dot. Its most unique characteristic is conductance oscillation as a function of the gate voltage, in which the oscillation period is determined by the capacitance between the dot and the gate. When many dots with different sizes are connected in one array, complicated characteristics seem to occur because many dots having a different oscillatory conductance with different periods and phases are connected in parallel and in series. Here, the fluctuation of the dot size can be used positively. Another important feature of SEDs is their multiple-gate capability, since the operation principle of SEDs enables them to inherently have many input gates [

(a) Schematic top view of a nanodot-array flexible-logic-gate device with many input gates and (b) cross section of the nanodot-array device.

The biggest problem of this concept is that several sets of suitable control-gate voltage have to be found out corresponding to the expected logic functions because we cannot predict the actual characteristics of nanodot arrays. However, if the nanodots are fabricated with a size close to the designed size, current oscillations in which the periods and phases are slightly distributed are achieved as a function of the input- and control-gate voltages. Since the oscillation period and phase change in accordance with the input- and control-gate voltages, a control-gate voltage can be identified so as to produce a required logic function. After the specific control-gate voltage is identified, it should be stored into nonvolatile memory. Then, another control gate voltage for another logic function should be identified and stored. Once several series of control-gate voltages corresponding to various logic functions are identified and stored, the device can be used as a multifunctional device with functions selected by using the stored control-gate voltages.

The simplest logic gate is a two-input logic gate such as NAND, NOR, or exclusive-OR (XOR) gates. When a flexible two-input logic gate is considered, the logic function should be flexibly changed by the voltage applied to the control gates. Three gates are needed at least to realize such devices: two for input and one for control. The most important point is for the device to achieve as many logic functions as possible by changing the control-gate voltage. The variability of the function is thought to be strongly affected by the arrangement of nanodots because current transport paths play an important role in deciding the electrical characteristics of the device. In this paper, we assume the most simple nanodot arrays considering the fabrication of the array by the use of the established method and the use of conventional silicon technologies named pattern-dependent oxidation (PADOX) [

Nanodot arrays typically have a variety of different dot arrangements. The most important point of any flexible device is accuracy in achieving the target function. Fluctuations of dot size and position, which are inevitable in nanodot array devices, cause fluctuations in tunnel resistances and in tunnel capacitances between dots and in gate capacitances between dots and gates. It is impossible to predict what the electrical characteristics will be, which makes it difficult to guarantee the functionality of the device. However, we propose using these fluctuations in a positive way to achieve a highly flexible device.

Here, a two-input, two-terminal logic device, in which output current or resistance between source and drain terminals, is changed by changing the combination of voltages applied to the two-input gates is considered. The device acts as a conventional two-input logic gate (such as a NAND, NOR, or XOR gate). One control gate to select the logic function of the device is attached. When the voltage applied to the control gate is changed, the logic function can be changed, for example, from NAND to XOR, and then to NOR [

The electrical characteristics of the nanodot-array devices are calculated with different dot arrangements. When six-dot arrays are assumed, four kinds of dot arrangement can be typically made, as shown in Figures

Four types of dot arrangement of an array consisting of six nanodots sandwiched by the source and drain electrode. (a) Series, (b) 2 × 3, (c) 3 × 2, and (d) parallel.

Series

2 × 3

3 × 2

Parallel

(a) The equivalent circuit of a 2 × 3 nanodot array and (b) an equivalent circuit with gate capacitors. The device has two input gates corresponding to the

Here, fluctuations in these values were introduced as shown in Table

Distribution of tunnel resistances, tunnel capacitances, and gate capacitances.

Average | Distribution function |
| |
---|---|---|---|

Tunnel resistance | 2 M |
Log normal | 0.2 |

Tunnel capacitance | 2 aF | Gaussian | 0.2 |

Input-gate capacitance | 1 aF | Gaussian | 0.2 |

Control-gate capacitance | 2 aF | Gaussian | 0.2 |

The drain voltage

The two input-gate voltages,

Figure

Simulated drain current

It should be noted here that conventional CMOS circuits usually use voltage outputs. In addition, when the current threshold is used in the current output waveform characteristics shown in Figure

It is easily understood that the current threshold plays an important role in the occurrence frequency of each logic function: when the threshold is changed, the occurrence frequency is changed because OR and NAND frequently appear at the lower current threshold conditions while AND and NOR appear at the higher current threshold condition. Figure

Occurrence frequencies of the six important logic functions (AND, OR, NAND, NOR, XOR, and XNOR) as a function of threshold current for a “parallel” nanodot-array device. We changed

Since the nanodot array has fluctuation in capacitance and tunnel resistance, the window also fluctuates. Figures

Occurrence frequency of the six important logic functions as a function of current threshold for three different “series” nanodot-array devices: (a), (b), and (c). We changed

We introduced a “normalized window width” that is normalized on the basis of the averaged value of the center of the window. Here, the center of the window of the current threshold is also normalized by the averaged value in order to compare the probability of the occurrence of six important logic functions in the four array arrangements. The electrical characteristics of more than 200 examples were calculated for each nanodot arrangement and the statistics of the normalized window width and the center of the window were evaluated. Figures

(a) Normalized window width and (b) standard deviation of the normalized center of the current threshold of the window for the four nanodot arrangements of arrays. The parameter is the minimum frequency of the six important logic functions.

In order to determine the best arrangement of the dot array, the probability of the occurrence of all the six important logic functions was evaluated. Figure

Occurrence probability of all the six important logic functions for the four nanodot arrangements of arrays when the current threshold is fixed at the most appropriate value for obtaining the highest probability. The parameter is the minimum frequency of the six important logic functions.

We also calculated the probability when the tunnel resistances have no fluctuation—namely, when they are constant at 2 M

Occurrence probability of all the six important logic functions for the four nanodot arrangements of arrays without tunnel resistance fluctuation. The parameter is the minimum frequency of the six important logic functions.

The Monte Carlo simulation was used to investigate flexible logic-gate devices consisting of a nanodot array assuming the fabrication by the use of the PADOX method in which lattice-like arrangement of nanodot arrays are attained easily. We changed the arrangement of the nanodots to clarify the importance of the parallel and series tunnel paths and then studied the variability of the logic functions of a device operating as a two-input logic gate. We introduced fluctuations in tunnel resistances, tunnel capacitances, and gate capacitances and then calculated the electrical characteristics of more than 200 sets for each nanodot arrangement as a function of the control voltage

The authors are grateful to A. Fujiwara, Y. Ono, H. Inokawa, K. Nishiguchi, T. Kaizawa, and T. Oya for their invaluable discussions. This work was partly supported by JSPS KAKENHI (2156081, 22240022, and 24360128).