Journal of Nanomaterials

Volume 2014 (2014), Article ID 347858, 5 pages

http://dx.doi.org/10.1155/2014/347858

Research Article

Temperature Effects on a-IGZO Thin Film Transistors Using HfO₂ Gate Dielectric Material

Yu-Hsien Lin and Jay-Chi Chou

Department of Electronic Engineering, National United University, Miaoli 36003, Taiwan

Received 18 January 2014; Revised 16 June 2014; Accepted 20 June 2014; Published 6 July 2014

Academic Editor: Kaushal Kumar

Copyright © 2014 Yu-Hsien Lin and Jay-Chi Chou. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Abstract.

This study investigated the temperature effect on amorphous indium gallium zinc oxide (a-IGZO) thin film transistors (TFTs) using hafnium oxide (HfO₂) gate dielectric material. HfO₂ is an attractive candidate as a high-κ dielectric material for gate oxide because it has great potential to exhibit superior electrical properties with a high drive current. In the process of integrating the gate dielectric and IGZO thin film, postannealing treatment is an essential process for completing the chemical reaction of the IGZO thin film and enhancing the gate oxide quality to adjust the electrical characteristics of the TFTs. However, the hafnium atom diffused the IGZO thin film, causing interface roughness because of the stability of the HfO₂ dielectric thin film during high-temperature annealing. In this study, the annealing temperature was optimized at 200°C for a HfO₂ gate dielectric TFT exhibiting high mobility, a high ratio, low current, and excellent subthreshold swing (SS).

1. Introduction

In recent years, transparent oxide thin film transistors (TFTs) have attracted substantial attention because of their potential application in the display industry as next-generation thin film transistors. In addition, amorphous indium gallium zinc oxide (a-IGZO) provides numerous advantages compared with polysilicon, including a high carrier mobility rate, a high switching current ratio, a low-temperature process, excellent uniformity, excellent transparency to visible light, and large-area processes, facilitating its integration in high-resolution displays [1–5]. Compared with amorphous silicon TFTs, a-IGZO TFTs exhibit higher mobility (3–30 cm²/V-s) even in the amorphous phase [2, 6–8]. In general, a-Si:H and polysilicon, which are commonly used as channel layers for transistors, have several limitations, including high temperatures, photosensitivity, and high cost when used in conventional complementary metal-oxide-semiconductor processes. IGZO thin film can be deposited at room temperature by using the cosputtering process or sol-gel methods, which involve low thermal budgets and are compatible with glass substrates and flexible plastic substrates [9].

High-κ gate dielectric materials have been widely used to reduce electron tunneling and maintain a large capacitance at a high drive current [10–12]. Hafnium oxide () is an attractive candidate for use as a high-κ dielectric material because it exhibits thermodynamic stability, a high dielectric constant, proper conduction and valence-band offset with Si, low lattice mismatch with Si, and excellent electrical properties at high drive currents. Therefore, by incorporating for the gate dielectric, the operation voltage can be reduced and device scaling can be facilitated. In addition, considering the integration of the TFTs process, the thermal budget is crucial in high-speed and high-resolution display applications. Regarding the high-κ dielectric thin film/IGZO interface, maintaining a high subthreshold swing (SS) and low carrier mobility is the critical concern when a high thermal budget is involved.

To investigate these concerns, the effect of temperature on a-IGZO TFTs with gate dielectric was studied by analyzing electrical characteristics and conducting material analysis. In addition, the optimal electrical characteristics of a-IGZO TFTs were determined.

2. Experiment

The process of fabricating the a-IGZO TFTs with gate dielectric involved using -type wafers and a bottom-gate structure, as shown in Figure 1(a). First, 100 nm thin film was deposited using the E-gun method with targets. Second, a 30 nm a-IGZO layer was deposited using cosputtering with IGZO₄ targets (In, Ga, Zn, O ratio: 1 : 1 : 1 : 4) in ambient oxygen gas (O₂). The cosputtering process was performed at Torr in room temperature with precursors of O₂ (6 sccm) and Ar (24 sccm), and the DC sputter power was set at 150 W. After active region patterning was performed, 30 nm titanium (Ti) thin film was deposited and used for source and drain electrodes, using the E-gun method at room temperature. After source/drain patterning was conducted, postannealing treatment was performed for 30 minutes at temperatures ranging from 150°C to 450°C at increments of 50°C to fabricate the gate dielectric a-IGZO TFTs. The top-view layout of the a-IGZO TFT is shown in Figure 1(b). All devices used in this study exhibited length/width dimensions of 200/1000 μm.

(a)

(b)

Figure 1: (a) Schematic cross-section of the fabricated bottom-gate a-IGZO TFTs with gate dielectric. (b) Top view of the a-IGZO TFTs with gate dielectric. The device had dimensions of  μm.

3. Results and Discussion

Figure 2 shows the basic - electrical characteristics of the a-IGZO TFTs with gate dielectric at a temperature of 200°C during postannealing; the gate voltage varied from −2 to 5 V and the drain voltage was 1 V. The inset of Figure 2 shows the - output characteristics of the a-IGZO TFTs with gate dielectric, in which the drain voltage varied from 0 to 10 V and the gate voltages were 0, 2.5, and 5 V. Based on the transfer and output characteristics, the device operated in enhancement mode and exhibited a large on-to-off current ratio (/) greater than 10⁷. The apparent filed-effect mobility induced by transconductance at a low drain voltage  V was determined as follows:

where and were the gate capacitance per unit area and transconductance, respectively [13]. For our device, the is  F/cm² measured by test pattern. The maximum is  mA/V calculated on the - curve. A high field-effect mobility of 38.29 cm²/V-s was obtained. The threshold voltage () and SS were 1.15 V and 0.137 V/dec, respectively, and were extracted from the liner portion of the log (IDS1/2) versus plot. The a-IGZO TFTs with gate dielectric exhibited superior field-effect mobility compared with that of a-IGZO [14–16]. Table 1 lists a summary of our TFTs. Figure 3 shows the transfer characteristics of the a-IGZO TFTs with gate dielectric at various oxygen gas flow rates of the precursors: 6, 25, and 50 sccm. According to previous studies, the electrical characteristics of a-IGZO film can be controlled using a combination of O₂ and O vacancies [17, 18]. The oxygen vacancies are compensated by O₂ and the conductivity of the IGZO channel is reduced for supplying free electron carriers. According to the results shown in Figure 3, when the oxygen gas flow rate was increased, the increased because of less oxygen vacancies; so the resistance of the IGZO channel was enhanced, and a high was required for activating the device. A high conductive channel that exhibited a small SS was also achieved with a low oxygen gas flow rate. To optimize the conditions of the IGZO thin film, a 6 sccm oxygen gas flow rate was used in subsequent experiments.

Table 1: A summary table (/ ratio, , , and SS) of the a-IGZO TFTs with HfO₂ gate dielectric.

(m)

(volts)
SS

(V/dec.)

(cm²/V-s)
/

1000/200
1.15
0.137
38.29
2.9 × 10⁶

Figure 2: - transfer characteristics of the a-IGZO TFTs with gate dielectric. The insert figure shows the - characteristics of a-IGZO TFTs with gate dielectric.

Figure 3: - transfer characteristics of the a-IGZO TFTs with gate dielectric with precursors of (6, 25, and 50 sccm) through RTA treatment at room temperature.

Figure 4(a) shows the transfer characteristics of the a-IGZO TFTs with gate dielectric that depended on the annealing temperature when the gate voltage varied from −2 to 5 V. The postannealing temperature ranged from 150°C to 450°C at increments of 50°C and was applied for 30 minutes. The on-to-off current ratio (), , , and SS values are shown in Figure 4(b). Based on the values listed in Figure 4(b), applying a temperature of 200°C enabled the device to demonstrate excellent performance compared with the results of applying other temperatures. The a-IGZO TFTs with gate dielectric exhibited unfavorable electrical characteristics if the postannealing temperature exceeded 300°C. The least favorable /IGZO interface and oxide quality observed during annealing was speculated to be the result of and SS increasing. Figure 5 shows an atomic force microscope (AFM) image of the /IGZO testing sample annealed at temperatures of 200°C–400°C at increments of 100°C. The testing sample /IGZO structure was IGZO-film deposited onto the thin film. Based on the AFM results, the root mean square (RMS) of the IGZO film was compatible with the splits when the annealing temperature was below 300°C. When the annealing temperature was increased to 400°C, the RMS of the IGZO film increased from 0.510 to 1.179 nm. The smooth IGZO surface played a critical role in the high-performance device developed in this study. Figure 6 shows the secondary ion mass spectrometry (SIMS) data for the /IGZO testing sample when it was annealed at various temperatures ranging from 200°C to 400°C at increments of 100°C. According to the SIMS results, the hafnium (Hf) intensity in the IGZO film was compatible with the splits when the annealing temperature was below 300°C. The Hf atoms were initially assumed to not diffuse at low temperatures. However, when the annealing temperature was increased to 400°C, the Hf atoms diffused to the IGZO film. Based on the results presented in Figures 5 and 6, surface roughness was expected to develop because of Hf diffusion, maintaining device reliability at high temperatures. Table 2 shows the standard enthalpy of formation of , , , and ZnO. Based on this information, was determined to have a low standard enthalpy of formation, indicating that is the most stable among the evaluated materials. However, if the dielectric quality was not favorable, such as the poor oxide formation of caused by low-temperature fabrication, the Hf atom and oxygen atom reacted with each other to stabilize because of the low standard enthalpy of formation. Therefore, when high-temperature annealing was performed, the Hf atom readily diffused to the IGZO film. According to Figure 6, when the annealing temperature was 400°C, the Hf atom intensity substantially increased, diffusing into all the IGZO films. This resulted in surface roughness at the /IGZO interface and caused severe device reliability problems. Therefore, the optimal annealing temperature is 200°C for fabricating a-IGZO TFTs with gate dielectric.

Table 2: The standard enthalpy of formation for HfO₂, In₂O₃, Ga₂O₃, and ZnO.

Standard enthalpy of formation
HfO₂
In₂O₃
Ga₂O₃
ZnO

(kJ/mol)
−1144.7
−925
−1089.1
−350.5

(a)

(b)

Figure 4: (a) - transfer characteristics of the a-IGZO TFTs with gate dielectric with different annealing temperature. (b) A comparison of various parameters includes / ratio, , , and SS for a-IGZO TFTs with gate dielectric.

(a)

(b)

(c)

(d)

Figure 5: AFM graph for a-IGZO TFTs with gate dielectric with different annealing temperature.

Figure 6: SIMS profiles for a-IGZO TFTs with gate dielectric with different annealing temperature.

4. Conclusion

This study explored the temperature effect of the a-IGZO TFTs with gate dielectric. During high-temperature annealing, the hafnium atom diffused the IGZO thin film easily, and caused interface roughness because of the stability between the dielectric thin film and IGZO thin film. For optimizing the conditions of combining gate dielectrics with a-IGZO thin films, the postannealing at 200°C could yield high mobility, a high ratio, low , and excellent SS. a-IGZO TFTs with gate dielectric that exhibit excellent characteristics were successfully demonstrated through sufficiently low thermal-budget processing.

Conflict of Interests

The authors declare that there is no conflict of interests regarding the publication of this paper.

Acknowledgment

This project was sponsored by the National Science Council of Taiwan (no. NSC 102-2221-E-239-034).

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