Journal of Nanomaterials
Volume 2015 (2015), Article ID 537696, 6 pages
http://dx.doi.org/10.1155/2015/537696

Research Article

Investigation of In Situ Boron-Doping in SiGe Source/Drain Layer Growth for PMOS Devices

Min Zhong,1,2 Shou Mian Chen,² and David Wei Zhang¹

¹State Key Laboratory of ASIC and System, School of Microelectronics, Fudan University, Shanghai 200433, China
²Shanghai IC R&D Center Co. Ltd., Shanghai 201210, China

Received 9 September 2015; Accepted 15 October 2015

Academic Editor: You Yin

Copyright © 2015 Min Zhong et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Abstract.

Embedded SiGe (eSiGe) source/drain (S/D) was studied to enhance PMOS performance. Detailed investigations concerning the effect of GeH₄ and B₂H₆ gas flow rate on the resultant Boron-doping of the SiGe layer (on a 40 nm patterned wafer) were carried out. Various SiGeB epitaxial growth experiments were realized under systematically varying experimental conditions. Key structural and chemical characteristics of the SiGeB layers were investigated using Secondary Ion Mass Spectroscopy (SIMS), nanobeam diffraction mode (NBD), and Transmission Electron Microscopy (TEM) itself. Furthermore, performances of 40 nm PMOS transistors are also measured by the Parametric Test Systems for the semiconductor industry. The results indicate that the ratio between GeH₄ and B₂H₆ gas flow rates influences not only the Ge and Boron content of the SiGeB layer, but also the PMOS channel strain and the morphology of the eSiGe S/D regions which directly affect PMOS performance. In addition, the mechanism of Boron-doping during SiGe layer growth on the pattern wafer is briefly discussed. The results and discussion presented within this paper are expected to contribute to the optimization of eSiGe stressor, aimed for advanced CMOS devices.

1. Introduction

Implementation of embedded SiGe (eSiGe) as source/drain (S/D) has emerged as an attractive strategy for boosting device performance in PMOS transistors to technology nodes like 40 nm logic node and beyond. This is primarily connected with the ability of eSiGe to strain engineering of the PMOS channel [1]. eSiGe essentially works by enhancing hole mobility in the PMOS channel, by inducing a uniaxial compressive stress that arises out of the lattice mismatch between the substrate (Si) and the eSiGe layer. In the last decade, optimization of the misfit strain, by increasing Ge concentration in eSiGe, has met enormous success [2–5]. Simultaneously, in situ Boron-doping during SiGe epitaxial growth has also been widely researched, mainly due to its inducement of low sheet resistance in the S/D regions [6–9]. On the other hand, reports have also suggested that Boron-doping can actually bring out strain relaxation in the channel, termed as the strain compensation effect [10]. Boron-doping essentially reduces lattice mismatch between the Si and the SiGe layer, since Boron has a smaller atomic radius as compared to that of Si. Though there is a lot of literature on SiGeB growth, few works relate to SiGeB growth on the pattern wafer. Hence there is a need to conduct a rigorous investigation into the growth factors surrounding Boron-doped SiGe on the pattern wafer, with a focus on key structural and chemical characteristics. This paper studies the effect of GeH₄ and B₂H₆ gas flow rate on Boron-doping of SiGe film, deposited on a 40 nm patterned wafer. It includes investigating Ge and Boron content in a SiGeB film, along with observation of channel strain and morphology of the S/D regions. Moreover, the performances of 40 nm PMOS transistors were analyzed. In addition, the mechanism of Boron-doping during SiGe growth is briefly discussed.

2. Experiments

Figure 1 shows a schematic diagram, depicting the S/D regions of the fabricated 40 nm PMOS transistors. Different planar PMOS devices were fabricated on a bulk silicon substrate (diameter: 300 mm), according to the following procedure: at first, the channel implantation was performed before the formation of the gate dielectric and the gate electrode. Secondarily, the dopants for the lightly doped drain (LDD) were implanted. After that, a 50 nm U-shape trench was etched and a triple-layer epitaxial S/D structure, consisting of a SiGe seed layer (20 nm), a Boron-doped SiGe bulk layer (30 nm), and a Si cap layer (20 nm), was deposited via consecutive selective-epitaxy steps. The epitaxial layers were grown in an AMAT Centura reduced-pressure chemical vapor deposition (RP-CVD) reactor, at growth temperature and pressure of 600°C and 10 torr, respectively. Dichlorosilane (SiH₂Cl₂) was used as a gas source for Si, whereas 10% germane (GeH₄) and 1% diborane (B₂H₆) were used as gas sources for Ge and Boron, respectively (with H₂ acting as a carrier gas). HCl was used as the etchant to provide the necessary selectivity during the SiGe deposition process. We have performed different experiments by exploiting a wide range of GeH₄ and B₂H₆ gas flow rates during the growth of the Boron-doped bulk layers, while keeping all the other process parameters constant. On the other hand, PMOS transistors with eSiGe S/D were formed on the device wafers using the same SiGe epitaxial conditions as mentioned above.

Figure 1: Schematic diagram of SiGe S/D area in PFET.

Immediately following the growth of the triple layered epitaxial process, Ge and Boron contents of the SiGeB layer were directly analyzed using a Secondary Ion Mass Spectrometry setup (SIMS; Camera 4F). The PMOS channel strain was measured using the nanobeam diffraction mode (NBD, FEI Tecnai G2 F20) within a Transmission Electron Microscopy (TEM) setup. eSiGe S/D morphologies were further analyzed by TEM (JEOL JEM-2100F). Besides, after the device wafers were fabricated, the universal curves ( versus ) were measured by the Parametric Test Systems for the semiconductor industry (Agilent, 4082F).

3. Results and Discussions

Table 1 lists the key growth parameters for different Boron-doped SiGe bulk layer samples, fabricated using different GeH₄ and B₂H₆ gas flow rates. Also, the estimated Ge and Boron concentrations are listed, along with the SiGeB growth rates, as calculated from the SIMS data. It was found that as GeH₄ flow rate increased while B₂H₆ flow rate was kept constant, the Ge content of the SiGeB film increased while Boron concentration decreased. In addition, the growth rate of SiGeB layer was promoted (sample #1~#3). On the other hand, as B₂H₆ flow rate increased while GeH₄ flow rate was fixed, the Boron concentration of the SiGeB layer apparently increased, while Ge content decreased (sample #2, #4, and #5). Besides, the growth rate of SiGeB improved. These observations are in agreement with a similar work reported in literature [11].

Table 1: Key characteristics of the fabricated Boron-doped SiGe bulk samples.

Sample number

#1
#2
#3
#4
#5

GeH₄ flow rate (sccm)
520
400
360
400
400

B₂H₆ flow rate (sccm)
60
60
60
70
40

GeH₄/B₂H₆ flow rate ratio ()
8.67
6.67
6.00
5.71
10.00

Channel strain 〈2, −2, 0〉
−0.88%
−1.42%
−0.80%
−0.60%
−1.50%

SiGe bulk Dep rate (nm/min)
20.6
13.2
8.04
17.9
7.9

Ge content in bulk
35%
33%
29%
29%
35%

Boron content in bulk (cm⁻³)

The NBD mode in TEM has emerged as a powerful technique for measuring strain with a nanoscale resolution [12]. The mechanism of NBD along with the related estimation method has been clearly established in literature [13]. Strain along the channel direction was measured by NBD. The nanoscale NBD probe measured the strain values along a cross section beginning from the gate oxide to the unstrained Si substrate (red arrow; Figure 2(a)), utilizing a line scan mode. The negative strain values refer to a compressive strain, which is what actually enhances the PMOS mobility. Figures 2(b) and 2(c) show the strain curves of the SiGeB film with different GeH₄ and B₂H₆ gas flow rate, respectively. Apparently, the channel shows maximal compressive strain, which is generally 0–10 nm below the gate oxide (red circles; Figures 2(b) and 2(c)) in contrast to the unstrained Si substrate (strain = 0) in all the samples. In order to further understand the influence of gas flow rates on the SiGeB film growth, ratio is defined as the ratio of the flow rate of GeH₄ to that of B₂H₆. From NBD result of the 5 studied samples (Table 1 and Figure 2), it was shown that as the value of increased, the channel strain in all the samples was monotonously enhanced, with sample #1 being an exception. Based on the fact that Boron induces strain compensation effect, it can be argued that higher Boron concentration in SiGe layer will decrease the compressive strain in the channel. Therefore, increasing , which corresponds to the increment in the content of Ge over Boron in the SiGeB layer, leads to improvement in the channel strain. A possible reason for the anomalous reduction in channel strain for sample #1 is the extremely high SiGeB growth rate associated with it. High growth rates can result into defects such as stacking fault or threading dislocations in the SiGeB film. As a consequence of this, the compressive strain in the channel could be partly relaxed, lowering the effective channel strain. Furthermore, TEM image of sample #1 was shown in Figure 3. Obvious threading dislocations appeared in the SiGeB film, which confirmed our previous speculation.

(a)

(b)

(c)

Figure 2: (a) TEM morphology along the cross section of sample #2 (). (b) Strain curves along the channel direction for samples with varying GeH₄ flow rates. (c) Strain curves along the channel direction for samples with varying B₂H₆ flow rate.

Figure 3: TEM morphology of sample #1 (threading dislocation appeared in the SiGeB film).

Increasing seems to be increasing the PMOS channel strain, which could be associated with the absence of any strain relaxation. However, besides this, the morphology of the eSiGe S/D regions also has to be considered for the SiGeB growth on the pattern wafer. Figures 2(a) and 4 show the morphology of the eSiGe S/D regions for sample #1, #2, and #5, respectively. Obviously, the Si capping layer can fully cover the SiGeB bulk layer for (Figure 2(a)). It was found that when the value of increases ( and for sample #1 and #5, resp.), the Si cap coverage of the SiGeB bulk layer becomes accumulatively sparse. When (sample #1), the edges of the SiGeB layer were not covered by the Si capping. In case of (sample #5), Si capping on the SiGeB bulk layer entirely disappears. It has been reported that a Si capping layer above the SiGeB bulk layer, which acts as a precursor for postsilicide formation, can actually improve S/D sheet resistance [14]. In the absence of this Si capping layer, the nickel germanosilicate, formed by consuming the SiGeB bulk layer during the silicide formation process, could induce higher S/D sheet resistance and strain relaxation in the SiGeB layer. The root cause of the poor covering of Si capping layer can be explained in terms of the difference existing between the lattice constant of SiGe and Si. When the value of is high, the higher Ge content leads to a higher dispersion in the lattice constants of SiGeB and Si. Thus, Si epitaxial growth on the SiGe surface, especially on the (110) facet, is rendered relatively difficult as compared to that on the identical Si surface. In order to improve the Si epitaxial growth on the SiGeB layer, the nucleation activation energy of Si capping deposition has to be enhanced by employing strategies like higher growth temperature, and so forth.

(a)

(b)

Figure 4: TEM image of the cross section of sample (a) #1 () and (b) #5 ().

Additionally, the transistors performances were compared with and without Si capping on the SiGeB S/D regions (sample #2 and #5 epitaxial condition, resp.). The currents were extracted under = 100 nA from the universal curves ( versus plot) of 40 nm PMOS transistors (as shown in Figure 5). current was increased from 418 μA/μm to 486 μA/μm. A 16.2% performance improvement was achieved, attributed to lower S/D sheet resistance of the PMOS transistor with Si capping. Lower S/D resistance indicates the on-resistance of a PMOS transistor (), which leads to the enhancement of when is fixed. The above explanation illuminated the significance of good morphology of eSiGe S/D regions.

Figure 5: Universal curves ( versus plot) for 40 nm PMOS transistors with and without Si capping on SiGe bulk.

In a word, it should be noticed that the growth mechanism of SiGeB on the pattern wafer is more complicated compared to that on the blanket wafer, since the structural and chemical characteristics of the SiGeB are sensitive to the growth parameters. According to Section 3, ratio should be considered as a key parameter instead of the individual GeH₄ and B₂H₆ flow rates. A moderate value of can result into large channel strain and a good morphology of the eSiGe S/D regions, which ultimately eliminates any strain relaxation and also suppresses sheet resistance in the S/D areas. As a result, improved effective PMOS performance can be acquired. As the presented study, sample #2, which has moderate (6.67), shows remarkable channel strain (−1.42%) along with a good Si capping coverage.

4. Conclusions

In summary, the parameter (the ratio of the gas flow rates of GeH₄ and B₂H₆) was demonstrated to have a crucial influence on the channel strain and S/D region morphologies of a PMOS. This ultimately affects the effective device performance of a 40 nm PMOS transistor. It was established that a moderate value has to be chosen in order to obtain large enough compressive channel strain, along with a good morphology in the S/D areas. In addition, the S/D sheet resistance and strain relaxation issues which were addressed in this work could be considered for integration into the PMOS fabrication process. An exhaustive understanding of the growth mechanism of the Boron-doped SiGe layer on the pattern wafer was also presented. The conclusions might serve as a useful reference for improving the eSiGe stressor performance, which could eventually lead to optimizations for advanced CMOS devices.

Conflict of Interests

The authors declare that there is no conflict of interests regarding the publication of this paper.

Acknowledgments

This work is sponsored by the Shanghai Postdoctoral Scientific Program (14R21421600), the National High-Tech R&D Program of China (863 Program, Grant no. 2015AA016501), the Program of Shanghai Subject Chief Scientist (14XD1400900), and the Program for Changjiang Scholars and Innovative Research Team in University (IRT13013).

References

T. Ghani, M. Armstrong, C. Auth et al., “A 90nm high volume manufacturing logic technology featuring novel 45nm gate length strained silicon CMOS transistors,” in Proceedings of the IEEE International Electron Devices Meeting, pp. 11.6.1–11.6.3, Washington, DC, USA, December 2003.

M. Kolahdouz, P. T. Z. Adibi, A. A. Farniya et al., “Selective growth of B- and C-doped SiGe layers in unprocessed and recessed Si openings for p-type metal-oxide-semiconductor field-effect transistors application,” Journal of the Electrochemical Society, vol. 157, no. 6, pp. H633–H637, 2010.

J.-P. Han, H. Utomo, L. W. Teo et al., “Novel enhanced stressor with graded embedded SiGe source/drain for high performance CMOS devices,” in Proceedings of the International Electron Devices Meeting (IEDM '06), pp. 1–4, IEEE, San Francisco, Calif, USA, December 2006.

A. V.-Y. Thean, D. Zhang, V. Vartanian et al., “Strain-enhanced CMOS through novel process-substrate stress hybridization of super-critically thick strained silicon directly on insulator (SC-SSOI),” in Proceedings of the Symposium on VLSI Technology. Digest of Technical Papers, pp. 101–103, IEEE, Honolulu, Hawaii, USA, June 2006.

D. Lee, M. Sakuraba, T. Matsuura, J. Murota, and T. Tsuchiya, “SiGe-channel 0.1 μm pMOSFETs with super self-aligned ultra-shallow junction formed by selective in-situ B-doped SiGe CVD,” in Proceedings of the 60th Digest Device Research Conference (DRC '02), pp. 83–84, IEEE, Santa Barbara, Calif, USA, June 2002.

N. Yasutake, A. Azuma, T. Ishida et al., “A high performance pMOSFET with two-step recessed SiGe-S/D structure for 32 nm node and beyond,” Solid-State Electronics, vol. 51, no. 11-12, pp. 1437–1443, 2007.

S. N. R. Kazmi, A. Y. Kovalgin, A. A. I. Aarnink, C. Salm, and J. Schmitz, “Low-stress highly-conductive in-situ boron doped Ge0.7Si0.3 films by LPCVD,” ECS Journal of Solid State Science and Technology, vol. 1, no. 5, pp. P222–P226, 2012.

Z. Zhu, Z. Cong, and R. Balasubramanian, “Selective epitaxial growth of heavily boron-doped silicon with uniform doping depth profile,” ECS Transactions, vol. 50, pp. 999–1006, 2013.

C. I. Liao, C. Y. Chen, S. Yu et al., “High quality SiGe:B of high Ge layer for 14nm and beyond FINFET processes,” ECS Transactions, vol. 58, no. 7, pp. 159–162, 2013.

N. Tamura, Y. Shimamune, and H. Maekawa, “Embedded silicon germanium (eSiGe) technologies for 45 nm nodes and beyond,” in Proceedings of the International 8th Workshop on Junction Technology (IWJT '08), pp. 73–77, Shanghai, China, May 2008.

X. J. Ning, D. Gao, P. Bonfanti et al., “Selective epitaxial growth of SiGe for strained Si transistors,” Materials Science and Engineering B: Solid-State Materials for Advanced Technology, vol. 134, no. 2-3, pp. 165–171, 2006.

L. Jin, H. Tu, Y. He, Y. He, and J. Wu, “A comprehensive study of SiGe source/Drain local stress by nano beam diffraction,” ECS Transactions, vol. 52, pp. 33–37, 2013.

J. Li, A. Lamberti, A. Domenicucci et al., “Channel strain characterization in embedded SiGe by nano-beam diffraction,” ECS Transactions, vol. 16, no. 10, pp. 545–549, 2008.

T.-H. Yang, G. Luo, E. Y. Chang, T.-Y. Yang, H.-C. Tseng, and C.-Y. Chang, “Study of nickel silicide contact on ,” IEEE Electron Device Letters, vol. 24, no. 9, pp. 544–546, 2003.