Charge Trapping in Monolayer and Multilayer Epitaxial Graphene

1Graduate Institute of Applied Physics, National Taiwan University, Taipei 106, Taiwan 2International Center for Quantum Materials, Peking University, Beijing 100871, China 3Department of Physics, National Taiwan University, Taipei 106, Taiwan 4Graduate School of Advanced Integration Science, Chiba University, Chiba 263-8522, Japan 5National Institute of Standards and Technology (NIST), Gaithersburg, MD 20899, USA

Graphene, a layer of carbon atoms bonded in a hexagonal lattice, has attracted a great deal of worldwide interest [1,2] because of its fundamental importance as well as its great potential applications.Although graphene prepared by the mechanical exfoliation method [3,4] has the highest sample quality which allows one to study fascinating physical phenomena, its small size may limit graphene's realworld applications.In contrast, the sizes of chemical vapor deposition-grown graphene [5,6] and epitaxial graphene (EG) grown on SiC [7][8][9][10][11][12] can be large and thus they are highly desirable for wafer-scale device applications.In particular, EG can find prospects in high-frequency transistors [13] and thus is a great candidate for integration of graphenebased GHz devices with existing Si technology.In order to fully realize EG's potential, it is highly desirable to obtain a thorough understanding of the electronic properties of epitaxial graphene, for example, how the carrier density of an EG device varies with measurement temperature.Such important information can shed light on charge trapping in EG grown on SiC [11].In this paper, we report carrier density (n) measurements of two multilayer and two monolayer graphene devices over a wide range of temperatures (T).We find that, in the high temperature regime, ln() shows a linear dependence on 1/T.Such results yield activation energies for charge trapping ranging from 196 meV to 34 meV depending on the quality of the EG devices.By low-temperature vacuum annealing to remove adsorbates on a monolayer EG device, we are able to vary the carrier density of the sample in a controlled manner without significantly modifying the nature of the SiC/graphene interface.We suggest that both the SiC/graphene interface and the adsorbates on EG devices must be considered in order to obtain a thorough understanding of charge trapping in EG devices.Our results further suggest that, by low-temperature vacuum annealing ( ∼ 400 K), the carrier density of monolayer EG can be roughly constant, a great advantage for electronic devices operating over a wide range of temperatures.
Here we briefly describe fabrication of multilayer EG samples.SiC substrates were cleaned using a standard substrate cleaning procedure.The optically polished Si-face surfaces were then placed face to face with a polished graphite disk and arranged such that uniform Newton rings could be observed in fluorescent light [14].These optically finished substrate surfaces, as compared to the ones that were treated by the chemical-mechanical processed (CMP) method, resulted in a higher rate of SiC decomposition and created multiple graphene layers.The epitaxial growth process was controlled by annealing in a sequence of temperature ramps and dwell stages in Ar gas at a pressure slightly higher than 1 atm using a commercial furnace.After dehydration and cleaning at 725 ∘ C for 16 hours in the furnace, the temperature was ramped to 1200 ∘ C for 30 min and then ramped at 100 ∘ C/min for graphene growth at a temperature of 1850 ∘ C and 1950 ∘ C with a dwell time of 45 min and 30 min for Device 1 and Device 2, respectively.The temperatures were measured and controlled using molybdenum-sheathed type "C" thermocouples.After being carefully examined by the tapping-mode atomic force microscopy (AFM) and the transmission electron microscopy (TEM), Device 1 was estimated to have five layers, and Device 2 was estimated to have six layers.Optically polished substrates produce much thicker graphene for the same processing conditions compared to that grown on CMP surfaces.Monolayer epitaxial graphene samples (Device 3 and Device 4) were grown on an optically polished 6H-SiC(0001) wafer at 1850 ∘ C for 30 minutes under an Ar gas pressure at 98 kPa using a controlled Si sublimation process [15].The number of layers was confirmed by the AFM images.Specifically, we deposited a metal bilayer (5 nm thick Pd and 10 nm thick Au) directly on the as-grown EG after a dehydration baking at T = 115 ∘ C for 10 minutes so as to prevent the contamination from photoresist residues so as to produce low-carrier-density epitaxial graphene devices at low temperatures.We performed the standard optical lithography for a Hall-bar configuration and the protective metal was removed from the Hall bars using diluted aqua regia before measuring the device [15].Four-terminal magnetoresistivities for longitudinal   and Hall   were measured using standard AC lock-in techniques.
Figures 1 and 2 show the measured Hall slope   (, )/ of multilayer EG samples (Device 1 and Device 2) as a function of T, respectively.The change of the low-temperature Hall slope can be ascribed to electron-electron (e-e) interactions [16].However, at high temperatures, the observed change of the Hall slope is large (>10-fold) and cannot be simply to e-e interactions.Therefore this large change in the Hall slope at high  must be related to the change of  with increasing .In order to further study this interesting effect, we plot the logarithmic scale of the measured carrier density ln() as a function of 1/T (see the inset of Figures 1 and 2).Interestingly, in the high temperature regime (T ≥ 200 K), the data can be fitted to the following equation: where Δ,  B , and  are the activation energy, the Boltzmann constant, and the fitting constant, respectively.The measured Δ for Device 1 is (132 ± 12) meV which is the energy for electrons trapping.Similar results are obtained on Device 2 with a slightly higher Δ = (196 ± 17) meV.Our results are in qualitative agreement with those obtained on front-gated monolayer graphene (∼70 meV) [10].
It is natural to study the charge trapping effect in monolayer EG.To this end, we plot ln() as a function of 1/T for Device 3 and Device 4 in Figure 3 and the inset in Figure 3, respectively.The measured Δ is (50 ± 1) meV and (34 ± 4) meV for Device 3 and Device 4. Such values are smaller than those obtained in our more disordered multilayer EG devices.Since the mobilities, which can be calculated from Hall slope and the longitudinal resistivity at zero magnetic field, of our monolayer graphene (>30000 cm 2 /V/s at T = 3 K) are much higher than those of multilayer graphene (∼1000 cm 2 /V/s at T = 3 K) due to homogenous film with less  disordered conditions in monolayer graphene, our results suggest that, with increasing mobility, there is less charge trapping.The carrier mobility in the monolayer was greater than that in the multilayer due to the linear dispersion relation [17].By vacuum annealing to remove adsorbates on monolayer EG, we are able to controllably vary the low-temperature carrier density of our devices.Figure 4 shows () under different low-T annealing conditions.For  ≥ 2.2×10 11 cm −2 , we can see that  only increases slightly when increasing the measurement temperature.In these cases, the change in  is too small and fitting the data to (1) yields Δ smaller than the thermal energy at 300 K which is unphysical.We note that in top-gated monolayer EG charge trapping occurs at the SiC substrate since the surfaces of the devices are protected by a dielectric layer [11].In our case, since the annealing temperature is low (T ≤ 423 K) and is not expected to vary the nature of the SiC/graphene interface [18], our results show that the adsorbates on EG can significantly vary the binding energy for charge trapping.We thus suggest that one must consider charge trapping [19][20][21] by both SiC/graphene interface and adsorbates on graphene in open-faced EG.
Finally Figure 5 shows the measured Δ as a function of low-temperature mobility ().We can immediately see that Δ decreases with increasing .Our results demonstrate that the binding energy for charge trapping decreases with sample quality.Charge trapping, which could be detrimental to device operation over a wide range of T, should be minimized by improving the sample quality including the SiC/graphene interface, the graphene surfaces, and the sample mobility.
In conclusion, we have reported carrier density measurements of multilayer and monolayer epitaxial graphene devices over a wide range of temperatures.It is found that the activation energies corresponding to charge trapping decrease with increasing sample mobility.Vacuum annealing experiments show that both adsorbates on EG's surface and the SiC/graphene interface play an important role in determining the carrier density dependence on T.

1 Figure 1 :
Figure 1: Hall slope as a function of temperature on a semilogarithmic scale (Device 1).The inset shows ln() as a function of 1/T.The linear fit yields the activation energy.

Figure 2 :
Figure 2: Hall slope as a function of temperature on a semilogarithmic scale (Device 2).The inset shows ln() as a function of 1/T.The linear fit yields the activation energy.

Figure 3 :Figure 4 :
Figure 3: ln() as a function of 1/T.The linear fit yields the activation energy (Device 3).The inset shows ln() as a function of 1/T.The linear fit yields the activation energy (Device 4).

Figure 5 :
Figure 5: Δ as function of low-T mobility on a semilogarithmic scale.From left to right: Device 2, Device 1, Device 3, and Device 4.