Modeling, Simulation, and Analysis of Novel Threshold Voltage Definition for Nano-MOSFET

+reshold voltage (VTH) is the indispensable vital parameter in MOSFETdesigning, modeling, and operation. Diverse expounds and extraction methods exist to model the on-o8 transition characteristics of the device. +e governing gauge for e:cient threshold voltage de;nition and extraction method can be itemized as clarity, simplicity, precision, and stability throughout the operating conditions and technology node. +e outcomes of extraction methods diverge from the exact values due to various short-channel e8ects (SCEs) and nonidealities present in the device. A new approach to de;ne and extract the real value of VTH of MOSFET is proposed in the manuscript. +e subsequent novel enhanced SCE-independent VTH extraction method named “hybrid extrapolation VTH extraction method” (HEEM) is elaborated, modeled, and compared with few prevalent MOSFET threshold voltage extraction methods for validation of the results. All the results are veri;ed by extensive 2D TCAD simulation and con;rmed analytically at various technology nodes.


Introduction
Ceaseless curtailing of integrated circuit technology along with the accuracy of threshold voltage management methods and depletion in short-channel e ects (SCEs) are emphasizing the threshold voltage to exceptionally low values. It is necessary to extract the precise threshold voltage (V TH ) for appropriate performance of the device. Flawlessly evaluated threshold voltage is mandatory to deliver correct and genuine gate control in channel conductivity and output characteristics of the device [1,2]. Minor millivolt inaccuracy cannot be shirked because it may trigger grievous faults in the circuit practicality. Precisely for high-speed sturdy analog circuit nanoscale design, accurate threshold voltage evaluation is vital and crucial for accurate device behavior [3][4][5]. e extracted threshold voltage assists the process of device matching too. reshold voltage is often exerted in evaluation and anticipation of device operation. e value of V TH is often utilized in examining the discrepancy because of manufacturing process technological parameter uctuations. Additional utilizations of threshold voltage value are compiled as to appraise reliability elements like radiation damage, hot carrier, stress, temperature instability, and ageing degradation.
Generally, the V TH value is extracted speci cally from the device transfer characteristics [6,7]. e functional drain voltage (V DS ) exaggerates several SCEs like DIBL, V TH roll-o , punchthrough, surface scattering, velocity saturation, impact ionization, and hot electron e ect. No particular evaluative analytic locus can be acknowledged as V TH in the device transfer characteristic curve due to subthreshold leakage phenomenon, hence causing ambiguity in the V TH extraction process. In the curve, weak inversion section demonstrates exponential divergence, whereas strong inversion section indicates linear/quadratic divergence. Conversely, the V TH is distinguished in the midst of weak and strong inversion transition sections. reshold voltage likewise hinge on numerous device parameters (gate width, gate overlap, gate length, biased bulk, temperature, etc.) and process technology limitations (C ox , T ox , doping concentration, etc.), making the de nition and extraction extrastrenuous [8].
In consideration of the above, the manuscript presents a new simple approach to de ne and extract the V TH of MOSFET. e corresponding novel enhanced SCEindependent V TH extraction method named "hybrid extrapolation extraction method" (HEEM) is further illustrated and compared with few prevalent customary MOSFET V TH extraction methods for validation of the results and claim the predominance of the HEEM over other extraction methods with minimum in uence of short-channel e ects (SCEs) and other second-order e ects like DIBL, V TH roll-o , punchthrough, surface scattering, velocity saturation, impact ionization, and hot electron e ect. Rest of the paper is organized as follows. Section 2 presents the conventional threshold voltage de nitions of MOSFET. Section 3 expounds the HEEM. Section 4 implements the HEEM concept on the test device and conventional MOSFET models. Furthermore, Section 5 presents the simulation results and validation of the proposed method and evaluation and analysis of discrete sub 45 nm technology nodes. Finally, concluding remarks and enhancement in the eld are presented in Section 6.

Conventional Threshold Voltage Definitions
of MOSFET e conventional de nition of the threshold voltage of doped semiconductor devices states that the gate voltage produces a surface potential equal to twice the fermi potential (∅ B ) in the bulk of the semiconductor [9]. Mathematically, the threshold surface potential (Ψ TH ) can be articulated as where β represents the inverse of thermal voltage and p 0 and n 0 are the equilibrium hole and electron densities, respectively [10,11]. N A and n i are the substrate doping density and intrinsic free-carrier concentration, respectively. Experimentally, it is observed that the modeled conventional de nition does not agree well with the V TH value extracted from the transfer characteristic curve. Consequently, the enhanced de nition was proposed for hot channel devices by including the MOSFET second-order e ects. e proposed empirical term (6/β) was added to (1) for a typical range of MOSFET substrate doping concentrations and oxide thickness. e improved empirical definition is modeled as e conventional de nition was also modi ed for longchannel devices by adding the corresponding empirical parameters to (1). e improved expression was developed by comparing the inversion and depletion charge terms of the device. Hence, the modi ed long-channel empirical de nition is modeled as where the empirical parameter τ 10 is valued for the typical range of substrate doping concentrations and oxide thickness analogous to long-channel devices. We can easily extract the subsequent threshold voltage (V TH ) from the threshold surface potential (Ψ TH ) of n-channel MOSFET using the standard basic threshold voltage MOSFET model expression. e modi ed conventional de nitions proposed in [10,11] are based on the concept of intersection of the two asymptotes of the surface potential for the depletion and strong inversion region surface potential, whereas the enhanced HEEM concept is a current-based approach for evaluating V TH (elaborated in the Section 3). Hence, it is easier to model and simulate at nanolevel and more accurate to de ne even for upcoming slim ballistic transistors.
e concept proposed in [10,11] works well for longchannel devices but deviates to give accurate results in extracting V TH for nano-MOSFETs with thin oxide layers and high doping densities. It also fails to generate sharp surface potential curves for nanodevices, hence asymptotic V TH point for nanodevices. e model equations of [10,11] are approximate asymptotic V TH de nition. It does not have an explicit expression for threshold voltage and gives considerable errors in predicting the V TH value at nanolevel technologies. Furthermore [10,11], study includes only the classical e ects with lot of approximations. e enhanced HEEM logic is applicable for both short-channel and longchannel devices and gives more accurate results. e HEEM logic generates sharp curves even working at nanotechnology node; hence, more accurate well-de ned values are obtained. Simulation results validate the results shown in upcoming sections.

A Novel Approach: Hybrid Extrapolation V TH
Extraction Method e new simple straightforward approach of extracting the threshold voltage of nano-MOSFETs is based on globally accepted drift-di usion model (DDM) and latterly developed ballistic, quasi-ballistic model. e transfer characteristics of MOSFET exemplify that the di usion current governs the subthreshold region, while the drift current dominates in the linear-saturation region. e net entire current is equal to the summation of drift current and di usion current. However, if potential across the drain to source terminals (V DS ) is zero, the net current ow is also nil as no current streams across the equipotential terminals even after biasing the gate terminal [12][13][14]. e constant current threshold voltage extraction method has an unclear description of critical drain current (I DCRITICAL ) liable on the technology employed. Linear extrapolation method, quadratic extrapolation method, and transition method results are highly in uenced by many second-order e ects like mobility degradation, shortchannel e ects, and extrinsic resistance e ects [6,7,15]. Second derivative method, third derivative method, Ghibaudo method, reciprocal H-function method, and transconductance to current ratio method are extensively exaggerated by noise. e V TH de nitions are also not based on ideal V TH de nition condition [16]. e match point 2 Journal of Nanotechnology method is seldom used as it is more laborious and more time-consuming. 5% deviation value is also an ambiguous de nition of threshold voltage calculation in match point method [17]. In normalized mutual integral di erence method and normalized reciprocal H-function method, the accurate evaluation of maxima in wide ranges makes the V TH extraction process tough and problematic [18,19]. e HEEM has the competence to accurately determine the threshold voltage (V TH ) of MOSFET and totally remove or nullify the abovementioned aws of the prede ned existing extraction methods.
For simplicity, we have only considered the n-channel MOSFET to illustrate this unique HEEM approach. Similar analysis can be extended for p-channel MOSFET. Following assumptions are made purposely: the device is considered to be laterally symmetrical and the source, drain, and bulk terminals are considered to be grounded; hence, no potential exists amongst the corresponding terminals, the gate is made of n+ polysilicon with work function q∅ M 4.24eV, the immobile charge in the oxide near the oxide-semiconductor interface has the same dispersal over both p and n regions, and the interface traps or interface states have the same distribution for both the p and n parts of the device close to metallurgical junction.
With the drain and source terminals grounded, the gate terminal governs the charge in the channel. When a small positive-biased voltage is applied to the gate of n-channel MOSFET, the state within the channel will alter. e free holes present in p-type silicon are deterred, thus forming a depletion region in the channel. is depletion region is formed over both lateral and vertical directions, that is, across the length and width of the channel. Increasing the positive gate voltage further will eventually lead to the saturation of the depletion depth. Once the saturation of the depletion region is reached, additional gate voltage will entice negative mobile electrons to the channel surface [20]. When adequate electrons have accrued in the channel area, the surface of the channel alters from the hole-dominated to the electron-dominated silicon material and is said to have inverted. Under this condition, a steering n-channel or inversion layer is formed under the gate between the two n+ silicon materials, namely, source and drain regions. Additional upsurge in gate voltage will only increase the surface potential of the channel gradually beyond 2ϕ B , whereby the increased gate voltage drops across the gate oxide. e minimum gate voltage required to form the conducting channel or an inversion layer underneath the surface is called as threshold voltage (V TH ). Figure 1 represents the 10 nm test device simulation results of drift current and di usion current components versus gate voltage (V GS ) for V DS 0.1 V. We can further classify the four MOSFET operation states as depletion region, weak inversion, moderate inversion, and strong inversion in reference.
e drift-di usion model (DDM) states that the total current across the channel is the sum of drift current and di usion current as [21] I TOTAL I DRIFT + I DIFFUSION . e DDM and even the Landauer approach (Boltzmann transport equation) in ballistic, quasi-ballistic nano-MOSFET models advocate that with the source and drain terminals grounded (V DS 0V), the total current ow is zero because of the zero potential drop across the terminals. However, if we plot the discrete components of the total current versus gate voltage, we see nonzero values and are exactly equal but opposite in direction of ow as both drift and di usion currents balance each other [22]. e drift and di usion current components literally equivalent but contrary in polarity can be termed as junction current 1 (I JNSC ) owing between source and channel junction and junction current 2 (I JNDC ) owing between drain and channel junction. Both the junction currents would be equal due to the symmetrical applied conditions and parameters. Hence, we can collectively denote both the junction currents I JNSC and I JNDC by I JNC . Gradually increasing the gate voltage from zero to high bias (V DD ), the drift-di usion current density and driftdi usion current components (I DRIFT and I DIFFUSION ) also increase as shown in Figure 2. Consequently, we can conclude that I JNC also increases with the increase in gate bias  terminal. However, I TOTAL remains zero because of the contrary ow direction of the distinct current components. Figure 2 justi es the logic as it can be seen that the drift current density is the same as the di usion current density but opposite in polarity [23].
As per the assumptions and the applied conditions in our HEEM, the subsequent I JNC value is nearly zero (negligible) in the subthreshold region. A linear/quadratic increase is witnessed in the I JNC numerical value as the inversion layer is formed. Hence, we are able to e ciently extract vital V TH by plotting I JNC versus V GS . Extrapolation of the I JNC versus V GS curve at the in exion point gives an accurate threshold voltage. e threshold voltage is found at the intercept of the tangent in the in exion point with the V GS axis. e linearity of the curve allows an easy extrapolation for better results as seen in Figure 3(a). e I JNC numerical value required for plotting the extraction curve is modeled in the subsequent section for reference. However, the I JNC value can be extracted easily from the TCAD simulation tools also. e I JNC ow density contour plots along the channel length for distinct gate potentials (V GS ) are simulated and shown in Figure 3(b) of 10 nm n-channel MOSFET test device. We can clearly see no current ow in the channel at V GS 0 V. However, contour of current ow is observed at the sourcechannel junction and drain-channel junction at V GS 0.5 V and increases with the gate bias (V GS 1 V). e current ow contour remains zero even at high gate bias (higher than the threshold voltage) exactly at the channel length position x L/2 representing no current ow between source and drain terminals. e extraction procedure is autonomous of drain-biased short-channel e ects, extrinsic series resistances, mobility degradation, slope factor variations, and channel length modulation, allowing a direct accurate determination of the threshold voltage. Hence, it is more e ective and fast in extracting V TH for both short-channel and long-channel devices. Exhaustive numerical simulations at various technology nodes and analytical results to demonstrate the extraction procedure are used to certify the proposed logic with conviction.

Implementation of Hybrid Extrapolation
Extraction Method e new hybrid extrapolation extraction method is implemented on test device and statistically evaluated using wellestablished MOSFET models. Comparison amid various conventional extraction methods and the new proposed method is performed on both technology CAD simulation and measurement in order to endorse the new enhanced extraction technique and related theory [10][11][12]. As described, the enhanced extraction method is independent of drain-biased short-channel e ects, extrinsic resistances, channel length modulation, and mobility degradation. Hence, it is more e ective in extracting V TH for both shortchannel and long-channel devices.

Execution of HEEM on Test Device. A basic square-sized bulk NMOS structure is contemplated for TCAD execution.
e nanodevice is modeled with channel length (L G ) 10 nm, gate oxide thickness (T ox ) 1 nm, bulk doping concentration (N BULK ) 10 17 cm −3 , and junction depth (X j ) 8 nm. For generalization of the outcomes, uniform doping is deemed all through the bulk [24,25]. Gaussian doping with the maximum limit of 10 20 cm −3 is modeled in source and drain regions for realistic results, whereas the extensions are planted and doped with the concentration of 10 19 cm −3 to reduce the GIDL consequences. Source-drain extensions expand 2 nm underlap, making the channel as an enhanced controlled and conductive path. Various parameters are considered to be steady in relation with the channel length scaling (EOT 1 nm, N BULK 10 17 cm −3 ). e physical models deployed for unblemished outcomes include ballistic, quasi-ballistic, doping-dependent mobility with high-eld saturation and degradation, Shockley-Read-Hall and tunneling models, and analytical model for e cacious temperature-dependent extractions. e model MOSFET incorporates the supply voltage of 0.9 V.
As per the set condition, V DS 0 V; hence, the proposed method will return a unique threshold value which can be considered as V TH of the device. e extracted threshold voltage value is independent of short-channel e ects like DIBL and threshold voltage roll-o and many other secondorder e ects instigated due to drain bias. e outcome of the hybrid extrapolation V TH extraction method for 10 nm test device and comparison with other predominant V TH extraction methods are shown in Table 1 (refer Figures 4(a)-4(d)).
V TLIN represents the threshold voltage with MOSFET operating in the linear region. e extracted value is found to accord with other recognized threshold extraction methods. e minor variation of the outcomes of the other predominant methods may be probably due to neglecting the SCE and second-order e ects. e validity of this new proposed HEEM was veri ed for long-channel devices also. e test device considered for the long channel is a squaresized uniformly doped bulk-driven n-channel MOSFET with 180 nm channel length. Most common extraction methods were also applied to extract the threshold voltage in similar conditions. e extracted values using HEEM were found to accord with other recognized V TH extraction methods [24,25]. e outcomes of various extraction methods for 180 nm test device are shown in Table 2.
e V TH extracted value using HEEM is very close to the few of the most popular V TH extraction methods. e overestimation of the other predominant methods may be probably due to neglecting the second-order e ects. Hence, we can conclude that the HEEM is equally e ective for both short-channel devices and long-channel devices [26,27].

Execution of HEEM on MOSFET Models.
Di usion current is a type of current in a semiconductor instigated by the variance of charge carrier concentration (holes and/or electrons), whereas the drift current is due to the transport of charge carriers prompted by an electric eld force exerted on them. Di usion current can be in the same or con icting direction of a drift current. e sum of di usion current and drift current collectively are designated by the drift-di usion equation [28].
Four autonomous current mechanisms in our n-type MOSFET test device are possible. ese components are the majority carriers' electron drift current and di usion current as well as the minority carriers' hole drift current and diffusion current. e complete current density is the summation of these four components. For one-dimensional instance, we can inscribe the concept as [4,5] J nqμ n E x + nqμ P E x + qD n dn dx − qD p dp dx .

(4)
Equation can be generalized to three-dimensional format as J nqμ n E + nqμ P E + qD n ∇n − qD p ∇p , (5) where D n and D p are electron and hole di usion coe cients, respectively, n is the number of electrons per unit volume, global symbol q represents the electron charge, and μ n and μ p denote the electron and hole mobility in the medium, respectively. e electric eld E − dϕ dx , where ϕ indicates the potential di erence. e logic is expressed as We also know D μϕ t as Einstein relationship on electrical mobility. ermal voltage (ϕ t ) KT/q, with K as the Boltzmann coe cient and T representing temperature in Kelvin. us, substituting E for potential gradient in (6) and multiplying both sides with e −∅/∅ t , we get Integrating (7) over depletion region of channel-source P-N junction assuming xd as the depletion thickness, we get where N a and N d characterize the doping concentration of n region (source) and p region (channel), respectively. ∅ B is built-in barrier potential and V IN denotes input voltage. With erefore, the expression can be expressed as where ϵ s denotes the permittivity of the material.
Using the above approximation in (9), we get we obtain the current due to di usion.
From (11), we can observe that current depends exponentially on the input voltage (V IN ) and the barrier height (Ø B ). V IN can be written as a function of electric eld intensity as Manipulation and substitution in (11) gives From (13), one can observe that when zero input voltage (V IN ) is observed, the drift current entirely balances the di usion current. Hence the net current ow density at zero potential V IN is always zero as the source and drain terminals are presumed to be grounded as per the assumptions and applied conditions in our HEEM. e above outcome of HEEM can also be performed through the well-established MOSFET charge sheet model (CSM). We represent the CSM complete expression of drain current (I DS ) valid for all the operating regions and con rm  In the CSM, the channel depletion area is obtained under the assumption that the substrate is uniformly doped (N B ). We presume the source and drain junctions are geometrically symmetrical in shape with a radial junction depth (X j ), and the channel depletion area is linearized in terms of only source-and drain-end surface potentials. X dms and X dmd represent the depletion depth across the channel aside the source and drain regions, respectively. us, the bulk charge density can be obtained. Statistically, the CSM model equation of the net drain-to-source current can be represented as follows [4,5].
Let x be the horizontal position in the channel, measured from the source end. If inversion layer current in lateral direction at any position x is denoted by I(x), then we have I DRIFT (x) as drift current contribution and I DIFFUSION (x) as the di usion current contribution at point x.
e intricate CSM drain current can be modeled as with Ψ s0 and Ψ sL expressing the surface potential at channel length x 0 and x L, respectively. c denotes the body e ect coe cient. W indicates the width of the channel. C ′ ox is oxide capacitance per unit area. V GB and V FB describe the gate-to-bulk voltage and at band voltage, respectively. As per the assumptions and the applied conditions in HEEM, Ψ sL Ψ s0 (the source terminal and drain terminal are equipotential). e channel depletion region area is symmetrical across the channel length around the source and drain region area due to the assumed balanced doping and regular geometry. Hence, we can perceive from the model (15) that the net current is always zero in the described situation. Consequently, in this state, we can further conclude that the drift current totally balances the di usion current; that is, the drift current value is exactly equivalent to the di usion current value but with the contrary direction.

Simulation Results and Validation of the
Proposed Method e HEEM logic is explored and executed at 10 nm MOSFET IC technology along with discrete additional existing sub 45 nm IC technologies. e outcomes are corroborated through immense 2D TCAD simulation and analytically rea rmed using industry standard tools. Discrete PT models developed by the Nanoscale Integrations and Modeling (NIMO) Group at Arizona State University (ASU) are employed to exemplify the outcomes [25]. e models are capable of capturing numerous second-order e ects to forecast the accurate device characteristics [29][30][31][32]. e validation of the new proposed hybrid extrapolation extraction method was accomplished by two-dimensional (2D) numerical simulations, and brief analysis was carried out on both short-channel NMOS and long-channel NMOS devices. First, using numerical simulations, I JNC was monitored as a function of the gate voltage (Figures 2 and 3(a)). I JNC has an exponential behavior for positive low gate voltages less than V TH , which corresponds to the weak inversion conferring to the MOS theory. Further increasing the gate voltage, we observe a linear/quadratic increase in I JNC corresponding to the transition of the surface from weak to moderate/strong inversion. is transition is considered as the de nition of the threshold voltage of the device.
In the second phase of validation, the results of V TH extraction using HEEM was compared with other recognized threshold extraction methods, namely, CCM, LEM, SDM, GM, and MPM [15][16][17][18]. e HEEM's extracted V TH value was found to accord with the other referred extraction methods. e extracted V TH values are presented in Table 3. Compact meshing and larger added checkpoints can improve the extraction accuracy.
A number of existing V TH extraction methods were put forward, analyzed, and analytically compared their respective outcomes with the presented HEEM concept. e comparative extracted V TH values of presented extraction methods were simulated and analyzed in the same analogous conditions. Table 3 presents comparative V TH extraction values of HEEM along with largely applied threshold extraction methods, namely, CCM, LEM, SDM, GM, and MPM for bulk-driven  32]. e comparative outcome con rms that the HEEM extracts the accurate threshold voltage results for both short-channel and long-channel devices. V TLIN and V TSAT in Table 3 represent the threshold voltage with MOSFET operating in the linear region and saturation region, respectively.

Conclusion
e robust analysis and comparison of various existing V TH extraction methods were employed to determine the V TH value test device. HEEM V TH logic was also employed in similar conditions, manifesting the new extraction approach HEEM as the improved extraction method for direct determination of threshold voltage, superior with minimum in uence of second-order e ects like DIBL, short-channel e ect, V TH roll-o , punchthrough, surface scattering, velocity saturation, impact ionization, and hot electron e ect. It is very bene cial and convenient for accurate extraction of V TH for both short-channel and long-channel devices as it is based on the physics of the device. e other augmentation of this method can be listed as the threshold voltage outcome value is exclusive (V TH ) for all operating regions unalike outcomes of other extraction methods that normally generate V TH in the linear region (V TLIN ) and V TH in the saturation region (V TSAT ). e linearity of the I JNC versus V GS curve allows an easy extrapolation for better results. e HEEM is independent of drain-biased short-channel e ects, extrinsic resistances, mobility degradation, channel length modulation, etc. Hence, it gives more precise results for both short-channel devices and long-channel devices.

Conflicts of Interest
e authors declare that they have no con icts of interest.