Fabrication of a Piezoresistive Barometric Pressure Sensor by a Silicon-on-Nothing Technology

This paper presents a piezoresistive barometric pressure sensor fabricated by using a Silicon-on-Nothing (SON) technology. Array of silicon trenches were annealed in hydrogen environment to form continuing crystalline silicon membrane over a vacuum cavity. Epitaxial growth on the silicon membrane is then completed for the desired thickness. All processes are CMOS compatible and performed on the front side of the silicon wafer.The piezoresistive barometric pressure sensor has been demonstrated with pressure hysteresis as low as 0.007%.


Introduction
MEMS pressure sensors find applications such as indoor and outdoor navigation, altimeter, and barometer.Recently, the shipping in the field of consumer electronics has rapidly increased.The consumer applications demand highperformance, low cost, and small size.A piezoresistive pressure sensor is a good candidate.The piezoresistive pressure sensors were first demonstrated by Tufte et al. in the 1960s [1] by using KOH etching.They may be made by bulk micromachining [2,3] or surface micromachining [4,5].Also, wide-band gap semiconductors based piezoresistive pressure sensors have been proposed for hostile environments [6,7].However, double-side processing from bulk micromachining is not CMOS process friendly [2,3].For example, doubleside alignment has the low photography accuracy and low throughput, and KOH etching has low efficiency and accuracy, resulting in high costs and high risk of batch process failure.Robert Bosch reported Advanced Porous Silicon Membrane (APSM) process for pressure sensors fabrication [8,9].However, such commercial piezoresistive pressure sensor through the APSM process demand dedicated tools to fabricate porous silicon which is not available in most of IC foundry.The Empty-Space-in-Silicon (ESS) process, a new SON technology, was developed in 2000 [10,11].Array of silicon trenches were annealed in hydrogen environment to form continuing crystalline silicon membrane over a vacuum cavity.It has been used for capacitive pressure sensors [12] and other sensors [13].This paper presents a process for a piezoresistive barometric pressure sensor by using the Silicon-on-Nothing (SON) technology.

SON Technology
The Empty-Space-in-Silicon (ESS) process includes the trench etching and annealing [10,11].In the first step, regular arrays of trenches are etched in (100) silicon wafers by reactive ion etching.The dimensions of the trenches depend on the annealing temperature and time.In the second step, the wafers are annealed in hydrogen environment.A heat treatment induces silicon to minimize the surface energy, leading silicon migration to widening of the void at the base and shrinking of the opening at the top.
The surface migration of silicon is governed by [10]  where  is the drift velocity of surface silicon atoms,  is the surface diffusion coefficient,  is the Boltzmann constant, and  is the process temperature.The chemical potential  = Ω, where  is the local mean curvature,  is surface tension, and Ω is the molecular volume.The relationship between the processing temperature and silicon diffusion coefficient was described [10].The diffusion coefficient at 1200 ∘ C is fourfold that at 1100 ∘ C. Thus, the annealing temperature and time, which will be optimized for ESS formation, depend on the size of the initial trenches.In our experiments, the trench with a diameter of 0.8m was etched in (100) silicon wafers by reactive ion etching (RIE).As showed in Figure 1, the sizes of the trench on the top, middle, and bottom are 0.89m, 0.87m, and 0.81m, respectively.The trenches can be transformed to ESS by the annealing at 1100 ∘ C for 10 min.Figures 1(b)-1(d) show the SEM cross-section pictures for our experiments at different annealing time.
When annealing for 10 min, as shown in Figure 1(c), the trenches were not completely merged as a whole.Thus, annealing for 10 min was not long enough to produce the membrane.When the annealing time was increased to 15 min, the desired cavity, as shown in Figure 1(d), was formed.However, when the annealing time was further increased to 20 min, the membrane was formed but cracked on the joint between the membrane and substrate.As a result, the formation process of the silicon membrane over a vacuum cavity depends on the annealing conditions.Usually, the trench diameter was controlled in the range of 0.5-1.2m.The spacing between the trenches was 0.5-1m, and the aspect ratio of the trench was defined in the range from 3 to 9.5.

Design and Fabrication
A piezoresistive pressure sensor was designed to measure 100 kPa absolute pressure.When the pressure was applied on the diaphragm, the strain () or stress () would bend the piezoresistors.Such a strain/stress can be measured by monitoring the resistance change of the sensor.
The resistivity () variation due to stress was written as [14] where   is the piezoresistive coefficients and   is the stress, in different orientations (), respectively.According to Hooke's Law, it yields where  is Young's Modulus.
3.1.Deflection Simulation. Figure 2 gives the simulation results of the stress and deflection of the diaphragm under 100 kPa.The diaphragm size is 600 m × 600m and its thickness is 13 m.The maximum deflection in the center reaches 0.64m and the stress concentrations occur in a 10 m wide rectangular area from the edge of diaphragm.
where piezoresistive coefficients  are defined as in Figure 3 and Table 1.
When the direction of stress is the same as that of current, the corresponding longitudinal piezoresistive coefficient is  11 , and the resistor is along with [100] direction.When the direction of stress is perpendicular to the current, the transverse piezoresistive coefficient is  12 . [110] [110] Figure 5: The schematic layout of piezoresistors.

Wheatstone Bridge.
A Wheatstone bridge is widely used in the design of piezoresistive pressure sensors, as shown in Figure 4.   stands for applied voltage across the node BD and V out is the output voltage measured across the node AC.When pressure is applied, the resistances of  1 and  3 vary due to the longitudinal piezoresistive effect, while the resistances of  2 and  4 change due to transverse piezoresistive effect.
A particular design, the full-bridge with four identical piezoresistors, that is, All piezoresistors are fabricated on N-type <100> silicon wafer and aligned with [110] direction because of a large piezoresistive coefficient.
According to the simulation in Figure 2, the four piezoresistors were aligned in the middle of the edge of diaphragm, showed in Figure 5.The cross-section and overview of the devices are showed in Figure 6.Four piezoresistors were implanted and connected via aluminum as a Wheatstone bridge.P + stands for a boron heavily doped region, P − stands for a boron lightly doped region, and TEOS is abbreviated by Tetraethyl Orthosilicate.ANSYS was used here to simulate stress distribution and deflection so that the size of the membrane over the cavity can be optimized.
Moreover, piezoresistors were related to temperature variation; the piezoresistance factor P(N, T) for p-Si was a function of doping concentration and temperature [3].As shown in Figure 7, the temperature coefficient of resistance (TCR) was around 2200 ppm/ ∘ C.
With the TCR values illustrated in Figure 7, Figure 8 shows the calculated bridge voltage output as a function of pressure at different temperatures, 0 ∘ C, 40 ∘ C, and 80 ∘ C.   ion etching.In the second step (b), the wafers were annealed in hydrogen environment at 1100 ∘ C for 15 min.Then, 12 m epitaxial growth of the silicon membranes was carried out.
Together with 1 m silicon membrane after annealing, the total thickness reached 13 m, which meet the design demand for 100Kpa silicon pressure sensor.In the third step (c), light boron was implanted to form piezoresistors with the resistance of 200∼500Ω/sq.Though 12 m thick epitaxy film, the alignment can still be processed by the ASML stepper, and the piezoresistors were aligned and exposed.Silicon oxide and silicon nitride were deposited on the membrane and the contact holes were etched.Aluminum was finally deposited and patterned to form connects (d). Figure 10 shows the SEM cross-section pictures of the silicon membrane over the sealed vacuum cavity.

Measurement and Results
Sensors were measured in a Model-GY-600 test chamber connected to pressure control equipment, shown in Figure 11.
The sensor was put into the chamber and connected to the electrodes outside the chamber through an electrical   interface.With the pressure controller, the pressure in the chamber was monitored while measurement.
Figure 12 shows voltage-current property of a fabricated piezoresistor at room temperature.It is clear that the resistance of the piezoresistor is measured to be 5.03kΩ.
Figure 13 shows the measured bridge output of the pressure sensor as a function of pressure with respect to different temperatures.Compared with the simulated data in Figure 8, the measured value, in Figure 13, was closed to calculated one.The offset is around 10 mV and the max span of 0 ∘ C is close to 80 mV.
The temperature hysteresis was measured to be 0.056mV for 25 ∘ C.
The temperature coefficient of offset (TCO) was measured to be 29.80V/∘ C.
The temperature coefficient of span (TCS) was measured to be -0.202%FS.
In order to study processing variations, different samples were measured.Table 2 shows a list of features of four different pressure sensors.
It shows that the pressure hysteresis is lower than 0.007%.
To compare with SON technology, the same design was fabricated by the Cavity-SOI technology [15], in which silicon membrane on the vacuum cavity was formed by anodic bonding or fusion bonding technology.Four regular parameters including zero-point output, span, TCO, and TCS were measured and showed in Figure 14.The membrane thickness of the SON devices has less variation than that of the Cavity-SOI, because the Cavity-SOI requires grinding the top wafer to desired values with a variation of ±1m, while the SON by using epitaxy is less than ±0.2m.Moreover, the Cavity-SOI has a lower throughput due to process steps including etching cavities/double-side lithography, bonding, and grinding, while the SON process takes less process steps.Thus, the SON devices are better in characteristic and throughput.

Conclusions
A process for a piezoresistive barometric pressure sensor is proposed and demonstrated by using a Silicon-on-Nothing technology.All fabrication processes have been performed on the front side of the silicon wafer, and they avoid the use of double-side processing and wet bulk silicon micromachining, resulting in high production efficiency.The continuing monocrystalline silicon membranes and selfclosed vacuum cavity assure the low hysteresis.And the SON devices demonstrated here are better than those fabricated by the Cavity-SOI.

Figure 1 :
Figure 1: The SON process.(a) Top view of initial trenches, (b) cross-section view of initial trenches, (c) cross-section view after 10 min annealing, (d) cross-section view after 15 min annealing, and (e) cross-section view after 20 min annealing.

Figure 2 :Figure 3 :
Figure 2: The simulation results of the stress and deflection of the diaphragm under 100 kPa.

Figure 9 :
Figure 9: Fabrication process of a piezoresistive barometric pressure sensor.
(a) The membrane over sealed cavity after annealing (b) The membrane over sealed cavity after epitaxial growth (c) SEM view of the fabricated piezoresistive sensor

Figure 10 :Figure 11 :Figure 12 :Figure 13 :Figure 14 :
Figure 10: SEM picture of the process.(a) The cross-section of the silicon membrane, (b) the sealed vacuum cavity, and (c) the piezoresistive sensor.

Table 2 :
Parameters of piezoresistive pressure sensors.