Mathematical Problems in Engineering

Volume 2014 (2014), Article ID 879402, 13 pages

http://dx.doi.org/10.1155/2014/879402

Research Article

Handling Fault Diagnosis Problem of Linear-Analogue Circuits with Voltage Phasor Measurement

Xin Gao, HouJun Wang, and Zhen Liu

School of Automation Engineering, University of Electronical Science and Technology of China, Chengdu 611731, China

Received 11 April 2014; Accepted 4 August 2014; Published 28 August 2014

Academic Editor: Yuqiang Wu

Copyright © 2014 Xin Gao et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Abstract.

This paper proposes a novel method to estimate the influence of hard-fault in linear-analogue circuit system based on the measurement of voltage phasor with assistant branch introduced. Furthermore, a new fault diagnosis strategy based on the voltage phasor modeling is established, and the tolerance influence on the corresponding voltage measurement is also discussed. The actual analogue circuit test shows us that the proposed method is effective and reliable to locate the accurate fault signature in voltage measurement for the fault diagnosis. As a matter of fact, it includes both the amplitude and phase information in a complex value form when the linear-analogue circuit is under the AC test. Besides, it can be also applied to ambiguous groups and the sensitive test-frequencies determination in the process of fault diagnosis,while the effectiveness of multifrequencies test has also been testified through test-frequencies sweeping investigation and the maximum error evaluation of fault component value in the second circuit example.

1. Introduction

The fault diagnosis problem has been one of the most critical issues in the test of large-scale industrial or military digital-analogue hybrid circuit. Furthermore, according to statistics, in the mixed-signal (circuit) system, more than faults occur in the analogue section [1], and the corresponding test cost accounts for of the total test cost and 30%–50% of manufacturing cost, as well as the test time which is more than of the total test time [2]. Therefore, there still exists a pressing need to locate an effective and simple method handling fault diagnosis in the analogue circuits.

Up to now, there have been extensive researches on analogue circuit fault diagnosis, in which scientists developed various fault diagnosis methods through different excitation for the circuit test: (a) DC test: it is the simplest and fastest one; however, it might fail because of energy-storage components; (b) AC test [3–5]: it uses a periodic signal as external stimulus for the circuit under test (CUT) and overcomes the shortcomings of DC test, as well as requiring relatively simple test; (c) aperiodic signals stimulus test [6–9]: it owns the most abundant features about circuit state but needs most complex test requirement.

To compromise the test simplicity (e.g., less time or money consumption) and the test effectiveness (e.g., higher fault detection and/or isolation rate), one can recommend the AC test in this paper. Moreover, depending on the number of frequency components in a stimulus, AC tests are further classified into two categories: single-tone and multitone test. In practice, multitone test stimuli can be composed of signals of different frequencies; therefore, in this paper, all concerns should be on the single-tone test: sinusoid signal test.

Eventually, this paper proposes a robust voltage phasor-based method for the circuit diagnosis, when the sinusoid signal stimulus is used in analogue circuit such that this method is robust, because of the fault modeling being established according to the rigorous theories. What is more, there are at least 3 more advantages: (a) the corresponding fault signature (voltage measurement) is simple to calculate in the process of circuit diagnosis, compared to the feature used in [10, 11]; (b) the fault diagnosis can be found in toleration circumstance to benefit us in the actual fault diagnosis with given requirement (e.g., the fault detection and/or isolation rate); (c) although the voltage measurement is discussed in a form of complex value for a AC test, it actually can be generalized to the case of real voltage measurement in the DC test.

In the end of this section, all of critical aspects of fault diagnosis discussed in this paper are listed as follows: (a) the calculation of voltage phasor value for a faulty linear-analogue circuit with a given AC test, (b) the influence of component tolerance on circuit voltage phasor response, (c) the AC test selection for fault diagnosis based on voltage phasor measurement, and (d) the further discussion about ambiguous groups determination and evaluation of multifrequencies test.

The rest of paper is organized as follows. At first, Section 2 establishes the theoretical basis for all the discussed contents as mentioned above. Then Section 3 tests the effectiveness of theories of Section 2 in some representative linear circuits. In Section 4, considering an important aspect—ambiguity groups determination was often discussed in linear-analogue circuit diagnosis in the past; one also discusses this topic on the basis of proposed fault modeling in this paper. Besides, the effectiveness of multifrequencies test in the second circuit example is further evaluated. In the end, the corresponding conclusions and prospects are made in Section 5.

2. Basic Principle

2.1. Voltage Phasor Modeling in Fault Diagnosis

Without loss of generality, one assumes that a linear-analogue circuit in Figure 1 is excited by an independent voltage stimuli as shown in (1). Besides, this signal is expressed in a phasor form of (2), according to the linear circuit theory in [12]:

where is the amplitude of sinusoidal signal of , is a known fixed frequency, and represents the phase of this signal. Therefore, voltage phasor is a complex value including the information of amplitude and phase from the stimuli of

Figure 1: The linear circuit network.

With the input signal , the circuit output response is also a sinusoidal signal , whose voltage phasor form is . Then, on the basis of the superposition theorem [13, 14], one can establish (3) for the voltage phasor at test-node as follows:

where is the complex transmission factor between and , while is the complex transmission factor from to .

As a matter of fact, the value of equals the value of voltage phasor response at , if the input stimulus is the sole incentive and component is in short-circuit state. In order to be convenient speaking in this paper, one can set it as .

Ulteriorly, on the basis of Thevenin’s theorem in the linear-analogue circuit, one can get the following:

where the () represents a voltage phasor through the circuit branch , when component is in normal (open) state. Besides, is a complex impedance for component . Meanwhile, is Thevenin’s equivalent impedance seeing through the circuit ports and , when component is open.

Due to the formula and (3)-(4), this paper finds the following:

In particular, one assumes that component is in open-circuit state; then the voltage phasor at is as follows:

At last, in accordance with (5) and (6), there exists a formula as follows:

In other words, (8) is formulated as follows:

where represents an invariable continuous function for a given linear-analogue circuit.

In the case of parametric fault of , the value of or is considered as constant. At last, “Theorem 1” can be found.

Theorem 1. In analogue circuit of Figure 1, the potential faulty component owns the nominal impedance value , and the nominal response is ; then the faulty response caused by parametric fault of at test-node can be calculated according to the following equation:

where the value of is a constant determined by .

Proof. With the statement in (8), it is obvious to find following equations:

Later, if (10) is divided by (11), will be eliminated. Then Theorem 1 is obtained.

Theorem 1 builds up the accurate analytic expression of fault response, because of parametric fault of component . It also tells us that based on the voltage phasor measurement or estimation in a few fault states (e.g., open-circuit state, short-circuit state, and nominal state), one can induce all the fault responses for any continuous parametric faults.

In particular, if component is resistance or capacitance , which means or , “Theorem 2” is given as follows.

Theorem 2. The faulty response curve of voltage phasor in Figure 1 can be determined by (14)-(15), respectively, if the fault component is capacitance or resistance in linear-analogue circuit.

Proof. Without loss of generality, let , , , and , then (12) is given as follows:

where .

Furthermore, the results of (12) lead to (13), when component is capacitance (, ) or resistance (, ) as follows:

where , , , and .

It is obvious to find that . Then if one sets and , (14)-(15) can be found as follows:

where , ,, , , and .

2.2. Voltage Phasor Measurement and Estimation

In the Theorems 1 and 2, we know that by separately measuring voltage phasor in the nominal circuit state and () in open (short)-circuit state, one can calculate the value of the output voltage phasor in all parametric fault states, which benefit us to accomplish the circuit fault modeling.

However, the open-circuit and short-circuit faults are the most catastrophic fault states, which means the corresponding analogue circuit in these states has to be destroyed in both physical structure and circuit function; that is, one can not drive the actual circuit into these two dangerous states for constructing the fault modeling. Therefore, there are 2 possible means to solve this tricky thing: faulty responses are simulated in PSpice-modeled circuit, which has been utilized in the SBT method; faulty responses can also be estimated through the voltage phasor measurement and calculation as shown in this section.

In Figure 2(a), when the circuit is in nominal state, one can set stimulus and measure the voltage phasor through component ’s branch as well as locate the value of . Furthermore, in Figure 2(b), by adding an auxiliary stimulus with voltage phasor stimuli representation of in Figure 2(b), in this case, the voltage phasor at will be , while the value of turns to . After this, Lemma 3 is acquired.

(a)

(b)

(c)

(d)

Figure 2: Short-circuit response evaluation in linear circuit.

Lemma 3. The faulty response , which is caused by short-circuit fault of component , is as follows:

Proof. According to the superposition theorem in linear circuit theories and (3), . Furthermore, the value of is the CUT output at when the original input stimulus is shortened but the auxiliary stimulus is preserved; that is, . As a result, Lemma 3 is founded.

Lemma 3 means that, with the measurement of voltage phasor in Figures 2(b) and 2(d), one can estimate the short-circuit response at before the potential faulty component is involved in short-circuit fault state. The cost is the input stimulus should be shortened in the process of voltage measurement. In order not to shorten any stimulus or port for the estimation of , Theorem 4 is established.

Theorem 4. The faulty response , which is caused by short-circuit fault of component , is as follows:

Proof. According to the process of deduction of Lemma 3, it is apparent to know that . By substituting it to (6), one obtains the following equations:

Furthermore, when circuit is in normal state, the complex impedance of is , and then there is the following equation:

Based on (6) and (18)-(19), one further knows the following equation:

In general case, ; that is, . Hence, with , one can get the solution of Theorem 2.

According to Theorems 1 and 2, if one can further obtain the value of , the fault modeling with voltage phasor will be established. In fact, the faulty response of can be calculated with Theorem 5.

Theorem 5. If one replaces the auxiliary stimulus in Figure 2(b) with an auxiliary branch owning impedance , then the output response . Thus, the value of faulty response at , which is caused by open-circuit fault of component , is estimated through (21). Here, as follows:

Proof. Assume that the faulty complex impedance of is , while the nominal complex impedance of is ; then according to (10)-(11), (22) is as follows:

According to (22), there should be (23), in which , and :

At last, Theorem 5 is established by the result of (23).

In short, the paralleled impedance of achieves the impedance transformation in Theorem 5; then the hard-fault state (open-circuit) influence can be estimated with the help of auxiliary branch and other circuit responses (e.g., , ).

2.3. Tolerance Influence on the Voltage Phasor

According to (9) in Theorem 1, Lemma 6 is found.

Lemma 6. Set the faulty value of component to , and the corresponding circuit output voltage phasor at is ; then within the tolerance circumstance, there are 2 continuous functions shown as follows:

where () is obtained, when component is in the open-circuit state (short-circuit state) with all other fault-free components according to component tolerance. And the value of is measured in the case that all components are set around the nominal component values within the tolerance range.

Proof. According to (9), one can assure that there are 2 equations without consideration of tolerance:

where . Therefore, Lemma 6 is correct while taking the account of tolerance influence in the analogue circuit.

On the basis of Lemma 6 and the basic principle of continuous function, one can conclude that if the faulty value of component varies continuously in a given parametric range as shown in (26), the corresponding value of voltage phasor at the circuit output should be bounded in (27) as follows:

Without loss of generality, if the potential faulty component is resistance , whose nominal value is and the component tolerance is , then the component value variation within tolerance range is . Furthermore, the maximum range of component parameters is , . Then Lemma 7 and Theorem 8 can be listed.

Lemma 7. Assume that component owns the following parametric values: (a) and (b) , and these values satisfy:   ;   ; then the conclusions are made in (28) as follows:

where the potential faulty component owns the parametric range of , , when the corresponding voltage phasor value is . And is the voltage phasor corresponding to the maximum range of component parameters being , .

Proof. If component can take these values: and , which means and , then = .

Therefore, if the value of component varies within parametric range of , according to the continuous function in (24), Lemma 7 is established.

Theorem 8. The accurate parametric range of is , which can be determined according to (29), when the faulty component value is or . Consider

where and are shown in Lemma 7, and , which has been given in Lemma 6.

Lemma 7 and Theorem 8 tell us that in tolerance-influencing circuit, if the potential faulty component is in a continuous faulty parametric range, the corresponding variation range of faulty response at can be estimated through the simulation or measurement of voltage phasor in some particular discrete faulty parameter cases. Or in other words, the limited simulations or measurements in practice could bring us accurate faulty response range estimation.

Furthermore, in the simulation or measurement of voltage phasor in discrete faulty parameter cases, Lemma 9 is shown.

Lemma 9. As for a general linear-analogue circuit, it can be considered as a network with branches and nodes (one of the nodes is reference node, e.g., ground). Let be the branch complex admittance matrix, represent the voltage phasor measurement vector, and be a complex current vector, then it is obvious to find (30) as follows:

The tolerance and discrete fault values influencing the corresponding branches (components) introduce these increment matrices: , , and as follows:

Without loss of generality, assume that the excitation current is fixed; then . As a result, Theorem 10 is established.

Theorem 10. Given a discrete faulty parameter for component through its branch, the corresponding voltage phasor (real part and image part) follows normal distribution in the tolerance-influencing circuit, if (a) the elements in the matrix for all fault-free components follow the normal distribution; (b) .

Proof. Due to the solution of (30)-(31) and , one can get

Therefore, each element of can be linearly expressed by the elements in matrix . And the corresponding voltage phasor (real part and image part) follows normal distribution if the elements in the matrix follow the normal distribution.

Theorem 10 states that the complex parametric faults (discrete fault values) lead to the faulty responses at , whose real part and image part number should conform to the normal distribution.

2.4. Fault Diagnosis in Linear-Analogue Circuit

In a linear-analogue circuit under test (CUT), the estimated range of voltage phasor is represented in Table 1. Here, the fault states set is , . And is the number of fault states in linear-analogue circuit. Each fault state can represent one of following continuous fault parameter ranges: (a) or for th component branch in the circuit, where and the tolerance is and (b) for th component in the circuit, where the component tolerance () exerts on all other fault-free elements in the circuit and is the representative discrete fault value as the central value of parametric range.

Table 1: Voltage phasor-based fault diagnosis with tolerance.

Considering the voltage phasor is dependent on the input stimulus at test-node , which could variate with different test-frequency of signal; thus, the test-frequency set can be shown in the columns of Table 1: , for the best fault diagnosis.

The corresponding voltage phasor value range in the rows of Table 1 can be separated into two parts: one is from the real part of voltage phasor value (e.g., [], ), while the other is from the image part of voltage phasor value (e.g., [], ). Therefore, based on the corresponding values in Table 1, the fault diagnosis for a set of parametric faults is categorized into fault detection and isolation: (a) a fault can be detected if the corresponding value of voltage phasor range owns no parametric overlaps with the fault-free state. (b) Meanwhile, a fault can be isolated meaning that this fault state can be distinguished from all other fault states because of no intersection of complex voltages range.

To be convenient speaking in the following sections, one sets the representation of and ; then following functions are shown in (33)-(34) as follows:

where .

where .

Then the result of fault diagnosis is measured through fault detection rate (FDR) and fault isolation rate (FIR) as follows:

Fault detection rate (FDR): the ratio of fault states that can be detected in a given fault states set as follows:

where .Fault isolation rate (FIR): the ratio of fault states pair can be isolated based on a given fault states pair set as follows:

where .

3. Computational Example

In this section, there are 2 representative examples to validate the proposed fault diagnosis based on the voltage phasor analysis in both tolerance-free and tolerance-influencing circuit. To be simplifying the question, in the first example of this section, the proposed method to estimate the parametric fault response and hard-faults influence is concerned with the theories from Theorem 1 and Theorems 4–8 and their corresponding lemmas. After this, in the second example, one can organize the complex voltages as what has been shown in Table 1 and select appropriate test-signal frequencies; that is, we can use these selected columns for fault diagnosis of a given fault states set, in order to satisfy the requirement of and .

3.1. Thomas Filter Example

The first example circuit is shown in Figure 3, while the circuit output is at . This example is used to demonstrate the critical results of proposed method for fault diagnosis based on complex voltages estimation, and the parametric faults are as follows: (a) discrete fault values in tolerance-free case as shown in Tables 2 and 4; (b) the parameter of faulty components varies from to of its discrete fault values in Table 5. Here, the former one is to testify the accuracy of Theorems 1, 4, and 5, while the latter one is used to demonstrate the process of faulty response estimation with consideration of tolerance and continuous parametric fault pattern diagnosis in the linear-analogue circuit.

Table 2: Component values in circuit of Figure 3.

Nominal values
Discrete fault values
Parametric faults limit

42.5 nF, 57.5 nF

127.5 nF, 172.5 nF

Figure 3: The Thomas filter.

In addition, in this circuit example, the stimulus signal (green sketch in Figure 4) is as follows: (a) the amplitude is  (V); (b) the test-frequency is set as 1.5 kHz; (c) the phase of this signal is zero. Furthermore, the circuit response in nominal circuit state is also given in Figure 4 (red sketch), which satisfies: (a) the amplitude is  (V); (b) the test-frequency is set as 1.5 kHz; (c) the phase of this signal is . Therefore, according to the relationship between (1) and (2), the corresponding phasor is  (V) ( (V)).

Figure 4: The circuit stimulus (green) and response (red) in AC test.

In order to estimate the faulty responses because of parametric faults in second column of Table 2, one should primarily estimate all hard-faults influence in this circuit. For instance, as for test-node , if is assumed to be the potential parametric fault component, the corresponding circuit output voltage phasor at test-node could be estimated as the following procedure in the circuit with nominal parametric values: (a) the circuit is in nominal state (fault-free), and the stimulus is  (V); (b) the voltage phasor through branch is  (V), and one can locate this complex value through the amplitude and phase of sinusoidal signal at test-node ; (c) as shown in Figure 3, one adds an auxiliary voltage stimulus  (V), and at the same time, the voltage phasor at test-node is  (V); (d) let all these measurements be in (17), the solution of (17) is  (V).

The similar measurements and calculations are processed for the other hard-faults influence estimations at test-node ; after that, the corresponding voltage phasor values are shown in Table 3.

Table 3: Voltage phasors for hard-faults at in Figure 3.

Fault response (short-circuit)
Fault response (open-circuit)

Table 4: Voltage phasors for parametric faults at test-node in Figure 3.

Diagnosis

Y

Y

Y

Y

Y

Y

Y

Y

Table 5: Voltage phasor-based fault diagnosis.

Diagnosis

No faults

The voltage phasor response at is .

These particular hard-fault responses can be used to evaluate the parametric fault responses through the solution of Theorem 1. Here, some parametric fault examples are shown in Table 4, and one gives a specific process of calculating fault response at test-node , when is the fault component (e.g., ): (a) according to data in Table 3,  (V) and  (V); (b) when all the components are in nominal circuit state , the value of on test-node is  (V); (c) according to (9), is ; (d) let all these measurements, estimations, and calculations be in (9); one can find the estimated complex value  (V).

All the estimated results for the discrete parametric faults in Table 2 (column 2) have been calculated based on (9) and been listed in Table 4 (column 2). And the results from actual circuit measurements have also been shown in the third column of Table 4. As a consequence, the corresponding fault diagnosis can be well done because of the consistence of data (e.g., the amplitude and phase reflected in the voltage phasor value) in column 2 and 3 of Table 4.

The results in Tables 3 and 4 point out that the process of calculating faulty response when the circuit suffered from parametric fault without consideration of tolerance. Furthermore, in order to form the corresponding faulty response data while considering the tolerance influence, the basic solutions of Lemmas 6 and 7 and Theorem 8 are used. Here, one gives a example process to calculate the the voltage phasor value range for at test-node . Here, the fault component varies in , and . Then, there exist these values: 1.500 kΩ, 1.643 kΩ, and  kΩ (1.358 kΩ), which lead to the following component value ranges with respective tolerance influence:

[1.425 kΩ, 1.575 kΩ], (b) [1.561 kΩ, 1.725 kΩ],[1.275 kΩ, 1.409 kΩ], (d) [1.290 kΩ, 1.426 kΩ].

These parametric sets unify to cover the whole range of for component . Therefore, by running 100 simulations around the component value or or , with the consideration of tolerance , the complex response ranges (including real part range and image part range for each complex response) at test-node are as follows:

(a), ;(b), ;(c), ;(d), .

Therefore, according to Lemma 7 and Theorem 8, the faulty response range for component at the test-node is as follows:

(a);(b).

Take some representative parametric faults in Table 5 into account; the corresponding fault states are continuous fault component values in a given bounded parametric varying range. And the other fault-free components’ values are randomly selected around their corresponding nominal values, while the tolerance is . Here, according to the contents in Table 5, it is obvious to find both of the values of and are for these 3 parametric faults.

3.2. Sallen-Key Filter Example

The proposed fault diagnosis method will be testified in another representative linear circuit: Sallen-Key filter example. In this section, the nominal component value is as follows: 1 kΩ; 3 kΩ; 2 kΩ; 4 kΩ; 6 kΩ; 5 nF. Different from the discussion in the previous subsection, the test-frequencies of sinusoidal signal are carefully selected according to the fault response curves determined by Theorem 2. And all the candidate test-signal frequencies eventually construct a test-frequencies set , .

The number of (test-frequencies numbers) is quite dependent on the number of systematic parameter in transfer function. For instance, in this example, the transfer function is in (37). Therefore, there are at most 3 test-frequencies required, in order to determine all the systematic parameter in (37). Consider

Note that, in this example, if the faulty component can own all possible parametric fault values (), and the corresponding stimulus signal is , then the corresponding faulty response curve is shown in Figure 6 for each component. With Theorem 2, these curves are determined according to equations as follows: (a) : . (b) : . (c) : . (d) : . (e) : . (f) : .

The intersections of these curves indicate the potential ambiguous faults in Table 6; for instance, when is open, or is short, the voltage phasor on owns the same value:  (V). Thus, the fault state : short, is one of ambiguous faults to the fault state : .

Table 6: Ambiguous faults in the circuit of Figure 4.

Fault state
Ambiguous faults

Open
: Short, : Short, : Open

Short
: Open, : Short, : Short, : Open

Short
: Open, : Short, : Short, : Open

All parametric faults
: All parametric faults

All parametric faults
: All parametric faults

Short
: Open, : Short, : Open

Open
: Open, : Short, : Short

For any given parametric fault of (),there exists a parametric fault of () generating the undistinguishable complex faulty response at test-node .

According to Figure 6 and Tables 6 and 7, test-frequency 30 kHz is a sensitive frequency for the circuit under test (CUT) of Figure 5 in parametric fault diagnosis (Table 7). Furthermore, one can sketch the other response curves with different test-frequencies. Such investigation leads to 3 representative sensitive test-frequencies: 30 kHz, 20 kHz, and 60 kHz, for a given fault states set in Table 7.

Table 7: Voltage phasor-based tolerance-free fault diagnosis with test-frequencies set .

No faults

Figure 5: The Sallen-Key filter circuit.

Figure 6: Complex faulty response curve for each component, where R-axis represents , while I-axis represents .

These test-frequencies can be testified as sensitive frequencies, according to the frequency sweeping results in Figure 7: (a) each response curve corresponds to a component fault in Table 7; (b) actually, in Figure 6, the test-frequencies 30 kHz and 20 kHz are around the center frequency of Sallen-Key filter.

Figure 7: The Sallen-Key filter circuit response in frequency domain.

As a matter of fact, the sensitive test-frequencies investigated in Figures 6 and 7 are also the recommendations in the circuit diagnosis for all potential single parametric faults with tolerance consideration (i.e., component tolerance for fault-free component is , while the parametric range for faulty component is [] and is the value in Table 7 for each potential faulty component). For instance, as for the fault states set in Table 8, if one lists the corresponding voltage phasor varying ranges, which can be estimated through the similar manner as what the Thomas filter example does, it is simple to locate the value of and . Therefore, all faults in Table 8 can be diagnosis with given test-signals set.

Table 8: Voltage phasor-based tolerance-influencing fault diagnosis with test-frequencies set .

No faults

:

:

:

:

:

:

:

4. Further Discussion

So far, this paper has presented a novel parametric fault modeling to the fault diagnosis of linear analog circuits via voltage phasor measurements. Particularly, it has discussed the tolerance and multifrequency measurements in the fault diagnosis as follows.

(a)The tolerance often introduces a variable parameter for the circuit components which leads to the variation of circuit response from one circuit board to another. In this paper, its influence is estimated according to the principles from Lemmas 6–9 and Theorems 8 and 10. At last, the corresponding applications have been shown in the illustrative examples of previous section.(b)The analytic parametric fault modeling (see, (9), (14)-(15)) and tolerance estimation in this paper give us a simple rule to select test-frequency for fault diagnosis in a given fault states set, which means the following:   the maximum number of test-frequencies is determined by the number of systematic parameter in transfer function (i.e., (37)); the final test-frequencies set should attempt to avoid ambiguous faults and increase the value of FDR and FIR (see, (35)-(36)).

However, considering the fact that an important aspect in the linear circuit fault diagnosis problem is constituted by the concepts of testability, the voltage phasor-based ambiguous groups determination will be in a discussion in this section. One can find that it is quite effective when it is compared with the “Jacobian rank approach” [15] based on transfer function coefficients. Futhermore, one uses the maximum error evaluation technology to evaluate the multifrequencies test previously listed in the second circuit example. This technology used to appear in [16].

4.1. Ambiguous Groups in Voltage Phasor Investigation

In this section, the ambiguous groups determination is based on voltage phasor investigation and the corresponding principle is shown as follows.

According to (9), test equations are constructed and circuit parameter functions (impedance value functions vector for potential faulty circuit network components) are related to test measurements (voltage phasor values vector) through the testability matrix as shown in the following equation:

where , , and .

Due to general method of ambiguous groups determination illustrated in [15–17], testability matrix can be used to locate ambiguous groups based on Definition 11 and to locate the canonical ambiguous groups because of Definition 12. Besides, the concept of “linearly dependent” here is in Definition 13; thus, the columns of the testability matrix are linearly dependent which means the corresponding components constitute an ambiguity group, for the whole complex test-frequencies domain.

Definition 11. A set of components constitutes an ambiguity group of order if the corresponding columns of the testability matrix are linearly dependent.

Definition 12. A set of components constitutes a canonical ambiguity group of order if the corresponding columns of the testability matrix are linearly dependent and every subset of this group of columns is constituted by linearly independent columns.

Definition 13. The columns of the testability matrix are linearly dependent, if , where the constant includes at least one nonzero real value.

With Definitions 11–13, let us talk about the ambiguous groups division in the circuit examples of previous section; in the first circuit example, it should be noted that the output voltage phasors caused by , , , and satisfy . Therefore, the corresponding columns are linearly dependent in matrix . Therefore, in this circuit, one can make the conclusion that , and constitute an ambiguous group, only through the direct observation of and as mentioned above, and such ambiguous group can be divided into two canonical ambiguous groups, [] and [].

Then the similar process is used to the components set , , , , here the [, , , ] constitutes an ambiguous group due to the corresponding linearly dependent columns in : , where the voltage-phasors are from Table 3. Then can be found as a canonical ambiguous group according to Matlab computation and Definition 12. Eventually, the final canonical ambiguous group division in the circuit of Figure 3 is , , and [, , , ].

The similar process of determination of ambiguous group is given in the second example; then it is obvious that components and constitute a canonical ambiguous group, when and ). Besides, the columns corresponding to in testability matrix is ,,], and nonzero real constants in Definition 13 cannot be found under the circuit test with the test-frequency being , which means these columns in are not linearly dependent. After that, [] does not constitute an ambiguous group for the whole complex frequencies domain. At last, the final canonical ambiguous group division in the Sallen-key circuit is , ], , [], [], and [] for the whole complex frequencies domain.

The results of ambiguous groups division above can be verified through “Jacobian rank approach.” Therefore, in the first circuit example, the transfer function of the Thomas filter is shown in (39), while Jacobian matrix is given by (40)–(42):

where .

In (41), the corresponding columns for components , and in are linearly dependent. Furthermore, in (42), the corresponding columns for, and are linearly dependent too. Therefore, the effectiveness of ambiguous group division through proposed method is finally verified in a point of view of “Jacobian rank approach” when it is applied in the following special circuit example: and . Morevoer, a canonical ambiguous groups division in the corresponding circuit is , , and .

The similar verification can be proceeded in the second circuit example; then the corresponding testability matrix is established in (43). Here, considering the testability value does not depend on component values [18], one assigns all “1” values to the circuit parameters in matrix . Thus, one can also find the same result about canonical ambiguous groups division in the proposed method application and the transfer function-based testability matrix (Jacobian matrix in [15]) investigation in (43). As a matter of fact, considering the relationship that the output voltage phasor is actually , where is the complex frequencies, it is not hard to understand such consistency. Consider

4.2. Multifrequencies Circuit Test Determination and Evaluation

In the last paragraph, one could conclude that the ambiguous group based on voltage phasor is the same as the result of testability analysis based on “Jacobian rank approach,” where the testability matrix is a Jacobian matrix determined by coefficients in transfer function. Such conclusion is not surprise, because the output voltage phasor can be expressed as , where is the complex frequencies.

Such conclusion implies that the sensitive test-frequency selected according to voltage phasor is also the sensitive one for fault diagnosis, which is searched out through the transfer function-based method. This solution has been verified geometrically through the frequency sweeping results shown in Figure 7, when the parametric faults in Table 7 need diagnosis.

In fact, the result of Table 6 and Figure 6 further tells us that one should select appropriate test-signal to distinguish the given ambiguous faults between and , which is also what canonical ambiguous groups result would like to tell us. Moreover, one can find out the same results in the ambiguous faults determination through Figure 6 or the ambiguous groups analysis in the last subsection.

At last, the observation of Figure 7 and Tables 7 and 8 points out that the test-frequencies 30 kHz, 20 kHz, and 60 kHz are sensitive to all the parametric faults that need diagnosis; even the tolerance is in consideration. And the values of and in the circuit example are .

In spite of the values of and , the maximum error evaluation technology involved in [16] can also be used to evaluate the effectiveness of multifrequencies test in fault diagnosis, where the maximum error for the potential fault components is represented by . And is a real fault value, while is a calculated value based on (9).

In order to simplify the illustration, let us firstly assume that the fault component in investigation owns a given discrete fault parameter while other fault-free components suffered from tolerance. For instance, is single fault in a tolerance-influencing circuit, whose faulty value is 1.5 kΩ. In addition, the tolerance of other fault-free components is and the test-frequency is 20 kHz. Then one of representative output voltage phasor measurement at test-node in such tolerance circumstance is given as , while the corresponding estimated hard-fault output responses based on the measurements in Theorems 4 and 5 are and . Therefore, the calculated fault value of is 1.4995 kΩ according to (9), which means the error for is . Such error tells us the test-frequency 20 kHz is a sensitive one to the fault 1.5 kΩ, because it is accurate enough to accomplish the parametric diagnosis of 1.5 kΩ when the corresponding input stimulus with test-frequency 20 kHz is used. Besides, it also means the estimated hard-fault responses are accurate through the methods in Theorems 4 and 5.

The similar test and diagnosis process can be extended to the multifrequency measurements ( 20 kHz, 30 kHz, and 60 kHz}) for the fault diagnosis of ; therefore, 0.067%. As a matter of fact, if the calculations based on the proposed fault modeling are done for all other potential faults, the maximum errors for all these fault values are much less than the component tolerance influence ().

5. Conclusion

This paper gives a voltage phasor-based viewpoint in order to solve the fault diagnosis problem in linear-analogue circuit: in the process of fault diagnosis, the accurate voltage phasor feature discussion let us know the accurate faulty response. Furthermore, the tolerance problem is also demonstrated, in which the proposed statistics-based point of view is used to estimate the voltage phasor varying range. After that, the test-frequencies are determined in fault diagnosis applications in order to obtain the required FDR/FIR values. In fact, all of these aspects have been analyzed and tested in the experiment of representative linear-circuit benchmarks.

In sum up, the method presented in this paper, is an acute view to handle the fault diagnosis problem of the component parametric alteration in linear-analogue circuit. Furthermore, it has been discussed in the problem of ambiguous groups determination, too. And it can be extended to the following cases (a)–(c). All of these aspects should be done in further research.

(a)Although the hard-fault is not the main focus in this paper, the proposed method could be generalized to hard-fault case through hard-fault influence estimation based on voltage phasor measurement in Theorems 4 and 5.(b)In fact, the discussion of accurate analysis can be used in the nonlinear circuit cases, as long as the linear-wise segments modeling can be established. In this case, the equivalent linear circuit network is used to replace the nonlinear circuit component. This means the parametric fault influence caused by nonlinear components can be transformed to the parametric alterations of corresponding linear circuit network.(c)The ambiguous groups determination could benefit us in the test-nodes selection problem.

Conflict of Interests

The authors declare that there is no conflict of interests regarding the publication of this paper.

Acknowledgments

Here, authors of this paper show their sincere thanks to following colleagues and tutors: Weimin Xian, JinYu Zhou, and Wei Li give us sound advices in amendments of writing and in data acquisition. Moreover, Vice Professor Long in our lab, for all his kindness, has also helped us a lot in the procedure of programming of Matlab/R code and Spice simulation. At last, this work was supported in part by the National Natural Science Foundation of China under Grants (no. 61271035 and 61201009).

References

F. Li and P. Woo, “Fault detection for linear analog IC—the method of short-circuit admittance parameters,” IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, vol. 49, no. 1, pp. 105–108, 2002.

Y. K. Sun, Study on Fault Diagnosis in Analog Circuit based on Support Vector Machine, University of Electronic Science and Technology of China, Chengdu, China, 2009.

D. Grzechca and J. Rutkowski, “Creation of analog fault AC dictionary based on fuzzy C neural network and output coding,” in Proceedings of the European Conference on Circuit Theory and Design, pp. 237–240, Cracow, Poland, 2003.

D. Grzechca, T. Golonek, and J. Rutkowski, “Analog fault AC dictionary creation—the fuzzy set approach,” in Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS '06), pp. 5744–5747, Island of Kos, Greece, May 2006.

D. Grzechca and L. Chruszczyk, “Wavelet C neural network to analog paramteric fault circuit location,” in Proceedings of the 13th International Mixed Signals Testing Workshop and 3rd GHz/ Gbps Test Workshop, pp. 2–6, Povoa de Varzim, Portugal, 2007.

A. Balivada, J. Chen, and J. A. Abraham, “Analog testing with time response parameters,” IEEE Design and Test of Computers, vol. 13, no. 2, pp. 18–25, 1996.

L. Chruszczyk, D. Grzechca, and J. Rutkowski, “Finding of optimal excitation signal for testing of analog electronic circuits,” in Proceedings of the International Conference on Signals and Electronic Systems, pp. 613–616, Lodz, Poland, 2006.

L. Chruszczyk and J. Rutkowski, “Optimal excitation in fault diagnosis of analog electronic circuits,” in Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems, Valletta, Malta, 2008.

H. Dai and T. M. Souders, “Time domain testing strategies and fault diagnosis for analog systems,” in Proceedings of the IEEE Instrumentation and Measurement Technology Conference, pp. 293–298, Washington, DC, USA, April 1989.

B. Long, S. Tian, and H. Wang, “Diagnostics of filtered analog circuits with tolerance based on LS-SVM using frequency features,” Journal of Electronic Testing: Theory and Applications, vol. 28, no. 3, pp. 291–300, 2012.

M. Aminian and F. Aminian, “Neural-network based analog-circuit fault diagnosis using wavelet transform as preprocessor,” IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 47, no. 2, pp. 151–156, 2000.

J. B. Jin and X. Z. Liu, Circuit Analysis, Xianxidian University Press, 3rd edition, 2009.

R. L. Boylestad, Introductory Circuit Analysis, Prentice Hall, Englewood Cliff, NJ, USA, 10th edition, 2002.

P. Wang and S.-Y. Yang, “A soft fault dictionary method for analog circuit diagnosis based on slope fault mode,” Control and Automation, vol. 22, no. 6, pp. 1–23, 2006.

G. Fedi, S. Manetti, M. C. Piccirilli, and J. Starzyk, “Determination of an optimum set of testable components in the fault diagnosis of analog linear circuits,” IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, vol. 46, no. 7, pp. 779–787, 1999.

F. Grasso, A. Luchetta, S. Manetti, and M. C. Piccirilli, “A method for the automatic selection of test frequencies in analog fault diagnosis,” IEEE Transactions on Instrumentation and Measurement, vol. 56, no. 6, pp. 2322–2329, 2007.

J. A. Starzyk, J. Pang, S. Manetti, and G. Fedi, “Finding ambiguity groups in low testability analog circuits,” IEEE Transactions on Circuits and Systems. I. Fundamental Theory and Applications, vol. 47, no. 8, pp. 1125–1137, 2000.

N. Sen and R. Saeks, “Fault diagnosis for linear systems via multifrequency measurements,” IEEE Transactions on Circuits and Systems, vol. 26, no. 7, pp. 457–465, 1979.