Mathematical Problems in Engineering
Volume 2018 (2018), Article ID 4584069, 9 pages
https://doi.org/10.1155/2018/4584069

Research Article

Neurospace Mapping Modeling for Packaged Transistors

Shuxia Yan,1,2 Xiaoyi Jin,1,2 Yaoqian Zhang,1,2 Weiguang Shi,1,2 and Jia Wen1,2

¹School of Electronics and Information Engineering, Tianjin Polytechnic University, Tianjin 300387, China
²Tianjin Key Laboratory of Optoelectronic Detection Technology and System, Tianjin 300387, China

Correspondence should be addressed to Weiguang Shi; shiweiguang12345@126.com

Received 10 March 2018; Accepted 4 September 2018; Published 1 October 2018

Academic Editor: Akhil Garg

Copyright © 2018 Shuxia Yan et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Abstract.

This paper presents a novel Neurospace Mapping (Neuro-SM) method for packaged transistor modeling. A new structure consisting of the input package module, the nonlinear module, the output package module, and the S-Matrix calculation module is proposed for the first time. The proposed method can develop the model only using the terminal signals, instead of the internal and physical structure information of the transistors. An advanced training method utilizing the different parameters to adjust the different characteristics of the packaged transistors is developed to make the proposed model match the device data efficiently and accurately. Measured data of radio frequency (RF) power laterally diffused metal-oxide semiconductor (LDMOS) transistor are used to verify the capability of the proposed Neuro-SM method. The results demonstrate that the novel Neuro-SM model is more accurate and efficient than existing device models.

1. Introduction

With the development of electronic technology, the accurate computer-aided design (CAD) models of transistors play a decisive role in the circuit/system design with high performance and reliability [1, 2]. The transistor in the circuit system contains not only the active cells, but also the passive devices such as the encapsulated package circuit. As the operating frequency increases, the presence of package components cannot be neglected due to the fact that the package parasitics influence the transistor performance [3, 4]. In order to predict the electrical performance of the packaged transistor, the CAD model must accurately reflect the characteristics of the active cells and the packaged circuit.

Package modeling for active/passive devices have been a field of strong interest in recent years [5, 6]. The equivalent-circuit-based model of metal-ceramic packages which was described in terms of inductances, resistances, and capacitances was used in radio frequency (RF) and microwave transistors [6, 7]. When the equivalent-circuit parameters are simultaneously optimized by the device data, the exact relationship between the voltage and current of packaged transistor can be obtained. As the device structure becomes complicated, it is inaccurate and time consuming to construct packaged transistor model in equivalent-circuit modeling manner due to slow trial-and-error processes. Electromagnetic (EM) modeling approaches become essential to realize design accuracy [8, 9]. A modeling method based on EM theory was presented in [10] to predict the EM feature of the three-dimensional construction of a high-power RF transistor with internal matching networks. Tedious calculation of EM simulation is prohibitively expensive, especially when a significant number of the geometric and material parameters have to be adjusted repeatedly [11–13].

Recently, Neurospace Mapping (Neuro-SM) techniques have been recognized as useful alternatives to conventional approaches in microwave modeling [14–16]. The Neuro-SM model can not only accurately represent the input and output relationship of the device/circuit, but also calculate quickly reducing the circuit/system simulation cycle [17]. Circuit-based Neuro-SM was proposed firstly in 2003 and then received wide attention from academia and industry [18]. An evolutionary Neuro-SM modeling technique with high computational efficiency was proposed in literature [19] which considered not only the voltage mappings but also the current mappings. Reference [20] used a dynamic neural network as the mapping network, and two mapping networks with analytical equations were added on the existing model in [21]. These existing Neuro-SM methods mainly focus on modeling for the active cells of transistor. The problem of package modeling is not addressed in these existing works.

In this paper, we proposed a new modeling method for packaged transistor based on Neuro-SM. The proposed method roughly divides the packaged transistor into three parts: the input package circuit, the nonlinear circuit, and the output package circuit, and they are built, respectively. In addition, an advanced training method making the novel model match the device data effectively is developed, which can avoid the mutual interference of the optimized parameters for the different performance of model. To verify the availability of the proposed modeling approach, a practical example on modeling RF power LDMOS transistor is presented.

2. Proposed Neuro-SM Modeling for Packaged Transistors

2.1. Proposed Neuro-SM Model Structure

Packages of transistors typically contain a metal flange and a dielectric window frame. The transistor is bonded to the die-bond area inside the cavity of the window frame. Metal leads are provided at the input and output sides of the window frame to allow for connection to external circuitry. Based on the physical structure of packaged transistor, we propose to roughly divide the total structure into three parts: the input package circuit, the nonlinear circuit, and the output package circuit. The proposed Neuro-SM modeling method creates the CAD modules for the three parts, respectively, and an additional -Matrix calculation module is required to associate the three CAD modules as a whole.

There are 4 modules in the novel Neuro-SM model of the packaged transistor: the input package module, the nonlinear module, the output package module, and the -Matrix calculation module, as shown in Figure 1. The input/output package module represents the performance of the package circuits which consist of passive components such as bond wires, MOS capacitors, integrated capacitor, and so on. Because the input/output package circuit consists of linear components, the unique input signal of the input/output package modules is the frequency, and the output signals are the real and imaginary parts of , and . The nonlinear module represents the characteristic of the multiple active cells in the packaged transistors. The nonlinear module is constructed by the existing Neuro-SM modeling method in literature [22]. Both DC characteristic and the -parameter performance of packaged transistors are affected by the nonlinear module. For the nonlinear module, bias voltages and frequency are the input signals, and the real and imaginary parts of 4 -parameters are the output signals. -Matrix calculation module plays an important role to in calculating the -parameter matrixes of the input package module, nonlinear module, and the output package module. The output signals of the S-Matrix calculation module are the -parameters of the modeled object.

Figure 1: Block diagram of the proposed packaged transistor model.

Scattering-matrix analysis is applicable to any general microwave circuit configuration when all the circuit components are modeled in terms of their scattering parameters. The -Matrix calculation module is constructed based on the literature [17]. represents the -parameters of the th component. For the packaged transistor model we proposed, i equals 1, 2, and 3 representing the input package module, the nonlinear module, and the output package module, respectively.

called the connection-scattering matrix represents the relationship between the incident wave and reflected wave. The main diagonal elements in are the negative of the reflection coefficients at the various component ports. The other (nondiagonal) elements of are negative of the transmission coefficients between different ports of the individual components. For the proposed model in Figure 1, can be written as represented in

Setting , we can obtain the total -parameters of the input package module, the nonlinear module, and the output package module, that is, the output of the -matrix calculation as represented in

2.2. Proposed Package Module Structure

There are two reasons for employing package circuit for RF/microwave transistors. The first one is the environmental ruggedness and the mechanical strength which can protect the internal circuit of transistor. The second one is to ease external matching-circuit design and improve device performance by adding an internal matching circuit into the package circuit. To achieve high gain or efficiency, lots of active cells are added to the transistor, which result in more bond wires; MOS capacitors and integrated capacitor are used to make electrical connections. The complex structure of package circuit greatly increases the difficulty of modeling. The package modeling method we proposed can be applied to arbitrary packaging structures, because the advanced package module is achieved only using the terminal signals, instead of the internal and physical structure information of the package circuit.

The block diagram of the package module is shown in Figure 2. The frequency is the unique input signal of the package module which is not excitated by the bias voltage. The real and the imaginary parts of the -parameters which are represented by prefix and , respectively, are the output signals of the package module. The subscripts and represent the input package and output package, respectively. In the package modules, the is not selected as an output because the dual network has the relationship , which can reduce the output dimension of the input/output module and simplify the model structure.

(a)

(b)

Figure 2: Block diagram of the proposed package module. (a) Block diagram of the proposed input package module. (b) Block diagram of the proposed output package module.

In the proposed package module, is a free variable and is the phase of the -parameter. The subscript indicates the port number of the input/output packaged circuit and the superscript and represent the input package and output package, respectively. The neural networks are used to represent the nonlinear relationship between the frequency and the 4 outputs of the neuronetwork as represented in (4) and (5).

and

where fANN and hANN represent multilayer feedforward neural network and and are vectors containing all internal synaptic weights of the neural network fANN and hANN, respectively.

Let A represent the amplitude of the -parameters of the package circuit. The subscripts indicate the port number of the package circuit. The proposed package module adopts a free variable to calculate the amplitude of the -parameters, which make sure that the value of is between 0 and 1 whatever the value of is. is computed as represented in

In the proposed method, the package circuit is supposed to be lossless and satisfies that quadratic sum of Return Loss and Insertion Loss is 1. The relationship of the amplitudes is described as represented in

The amplitude A and the phase of -parameters are obtained based on the output parameters of the neural network, (6), and (7). The formula conversion block completes the transformation from the amplitude/phase to the real/imaginary parts of -parameters. The real/imaginary parts of -parameters are adopted to make calculation procedure which combines the -parameters of the package modules and the nonlinear module easier. Moreover, for the same -parameter, many values of the phase which are several cycles apart are consistent. The values of the adjacent phase vary greatly due to the phase cycle, which increases the nonlinearity between frequency and the phase and enhances optimization difficulty. Therefore, the proposed method adopts the form of the real/imaginary part instead of the amplitude/phase. Appropriated weights and make the proposed package module describes accurately the characteristics of the encapsulated circuit without the information of the physical structure.

2.3. Nonlinear Module Structure

In order to perform the nonlinear characteristic of active cells in packaged transistor, Neuro-SM modeling method in literature [22] is used. Let the fictitious model that accurately matches the new measured/simulated data of transistors be called the fine model. Let the existing empirical/equivalent-circuit model be called the coarse model. When the accuracy of the coarse model cannot meet the modeling requirements, the Neuro-SM model including the coarse model and mapping networks is used to best match the fine model by automatically mapping the nonlinear relationship between signals of the coarse model and the fine model. Compared with other modeling methods based on space mapping, the Neuro-SM model does not require complex parametric extraction to obtain the next iteration point, which greatly reduces the time required for model development. In the novel Neuro-SM model we proposed, the nonlinear module is constructed as the structure shown in Figure 3.

Figure 3: Block diagram of the nonlinear module.

In the nonlinear module, when the coarse model operates with the signals instead of the signals , the output current and the -parameters of coarse model can match that of fine model accurately. The neural network is used to describe the nonlinear relationship between the signals of the coarse model and the signals of the fine model as represented in

where represents a multilayer feedforward neural network and is a vector containing all internal synaptic weights of the neural network .

2.4. Proposed Training Method

Precise models rely on reasonable parameters except for the correct model structure. The most important step during neural network modeling is to find a suitable set of weights by the training process. Let the training error measure the learning performance of the proposed model. Let the test error measure the predictive ability of the proposed model. The training process is performed until both the training error calculated with the training data and the test error calculated with the test data meet the accuracy requirements. The same error function of DC and -parameters as represented in (9) and (10), respectively:

where and represent the DC responses of the packaged transistor data and the proposed model, respectively. and represent the -parameters of the packaged transistor data and the proposed model, respectively. The superscript represents the training or test data index, and represents the total number of the training or test data.

The optimized parameters in the proposed model consist of in the input package module, in the output package module, and in the nonlinear module. The advantage of the proposed modeling approach is modular modeling, which make different parameters control different characteristics. However, the existing training methods optimize all parameters of neural networks at the same time, which cannot get appropriate parameters for the proposed model easily. In order to improve the optimizing efficiency of the proposed model, the proposed training method complete the construction and training of the packaged transistor model by using the following four steps.

Step 1. Send the bias voltage of the fine model to the mapping network in the nonlinear module. Initialize the weight making equal to , which ensure that the performance of the Neuro-SM model will not get worse than the coarse model.

Step 2. Adjust the weight of the mapping network in nonlinear model by solving (9). Obtain the bias voltage of coarse model and by solving (8), which make the Neuro-SM model match the fine model in the DC simulation.

Step 3. Adjust the weights and of the neural networks in package modules by solving (10). Obtain the appropriate parameters , and by solving (4) and (5), which make the proposed Neuro-SM model match the fine model in the -parameter simulation.

Step 4. Train the proposed Neuro-SM model with DC and - parameter data simultaneously. Fine tune the weights , , and improving the performance of the proposed model further.

The proposed training method enhances the advantage of the existing training method by adjusting the parameters in steps. The proposed method controls the DC/AC performance of the Neuro-SM model with different weight parameters, which reduce the mutual interference of the optimized parameters for the different performance of model and avoid changing the optimized parameters repeatedly.

3. Examples

RF power LDMOS transistor is the technology of choice, due to its low power consumption, high mechanical hardness, and the inherent economic advantages that silicon wafer manufacturing offers. To verify the accuracy and feasibility of the proposed Neuro-SM modeling method, the I-V and -parameter characteristics of packaged LDMOS transistor are modeled [23]. Measurement data of LDMOS transistor with packages are obtained as the training data and test data. The range of the training data and test data used in this example is showed in Table 1. The proposed Neuro-SM model learns the training data by adjusting automatically the weight of the neural networks. Test data which are different with the training data are used to validate the accuracy of the constructed model.

Table 1: Training data and test data for DC and S-parameter modeling of LDMOS transistor.

(V)
(V)
freq (GHz)

DC Simulation
Training Data
2.6:0.1:3.2
0:2:32

Test Data
2.6:0.1:3.2
1:2:31

S-Parameter Simulation
Training Data
0:1:1
8:4:24
1.7:0.028:3.1

2.5:0.1:2.8
30

0:0.2:2.2
28

2.3:0.1:2.8

Test Data
0:1:1
10:4:26
1.7:0.028:3.1

2.5:0.1:2.8

0.1:0.2:1.1
28

1.5:0.2:2.1

2.45:0.1:2.75

In this example, Angelov model is used as the existing coarse model. At present, Angelov model which can match many types of transistors is considered to be the great nonlinear model. Choosing Angelov model as the coarse model improve the general applicability of the new modeling method. The mismatch between the coarse model and the measured data of the LDMOS transistor cannot be ignored even by optimizing the parameters in the coarse model as much as possible. Then, the input/output package modules and mapping network are applied. The new model is trained as the four steps introduced in Section 2. The proposed model adjusts the weights of neural networks with the training data until the error between the fine model and the proposed Neuro-SM model operating with test data meet the design requirements. Table 2 gives the test error of the coarse model and the proposed model. This result demonstrates that the novel Neuro-SM method improves the current capabilities of the coarse model.

Table 2: Accuracy comparison of coarse model and proposed models for DC and S-parameter simulation.

Parameter
Coarse Model 
Test Error (%)
Proposed Model 
Test Error (%)

1.01
0.85

21.61
2.18

25.87
3.12

23.81
3.97

36.68
3.79

10.29
2.02

4.99
2.07

24.18
2.01

40.40
2.19

In order to further show the detail results, the I-V comparison of the coarse model and the proposed model is shown in Figure 4. Due to the low nonlinearity of DC characteristic, both the coarse model and the proposed model can match the measured data well. However, the accuracy of the proposed model is much higher than the coarse model in -parameter simulation as shown in Figure 5. These models work at bias voltage (, ) which is never used in training data. The magnitude and phase of -parameters from the proposed Neuro-SM model vary versus frequency in the exactly same way as that from the measure data. Because the 4 -parameters of the coarse model are controlled by the same set of parameters, it only provides a roughly approximation to the fine model. In the proposed model, the package module can respond to the frequency and the active module can respond to the bias voltages. The parameters in the proposed modules are independent and control different performance of the packaged transistor. Therefore, the proposed model contains more free variables and matches 4 -parameters of the fine model well simultaneously.

Figure 4: I-V comparison between measured data, coarse model, and proposed model for the LDMOS example.

(a)

(b)

(c)

(d)

(e)

(f)

(g)

(h)

Figure 5: Comparison of -parameters between measured data, coarse model, and proposed model for the LDMOS transistor at the typical work bias point (): (a) magnitude of , (b) phase of , (c) magnitude of , (d) phase of , (e) magnitude of , (f) phase of , (g) magnitude of , and (h) phase of .

After being trained with DC data and -parameter data, both the coarse model and the proposed model are operated in harmonic balance (HB) simulation to further verify the effectiveness of the advanced modeling methodology. Those models work at bias voltage (), fundamental frequency (), source impedance (), and load impedance (). The range of the input power is from 4.5 to 18.5dBm and the step of that is 2dBm, which allows the LDMOS transistor in this example to work in a linear region. The comparison results of the gain and the power added efficiency (PAE) between the coarse model and the proposed model are shown in Figure 6, demonstrating that the HB response of the proposed Neuro-SM model is much closer to the measured data than that of the coarse model. This result provides a good foundation for the large signals modeling in the future work.

Figure 6: Plot of the gain and PAE between measured data, coarse model, and proposed model for the LDMOS transistor.

4. Conclusions

A new Neuro-SM modeling approach has been proposed for packaged transistors. The novel model structure can accurately reflect the characteristics of both the active cells and the packaged circuit. This allows existing models to exceed their current capabilities. The advanced training method avoids repetitive adjustment of the optimization parameters improving the modeling efficiency. Good results are verified by the practical example. In the future, we can extend the proposed modeling method to further improve the larger-signal characteristic of the package transistors. Another potential future direction is to apply the proposed method in this work to the trapping behaviors of the gallium nitride transistors, meeting the needs of contemporary technology.

Data Availability

The data used to support the findings of this study comes from the author herself and may not be available for publication for the time being.

Conflicts of Interest

The authors declare that there are no conflicts of interest regarding the publication of this paper.

Acknowledgments

This work was supported by the National Natural Science Foundation of China (Grant no. 61601323), the Scientific Research Project of Tianjin Education Commission (Grant no. 2017KJ088), and the Tianjin Natural Science Foundation (Grant no. 17JCQNJC01400).

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