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This paper presents a novel Neurospace Mapping (Neuro-SM) method for packaged transistor modeling. A new structure consisting of the input package module, the nonlinear module, the output package module, and the S-Matrix calculation module is proposed for the first time. The proposed method can develop the model only using the terminal signals, instead of the internal and physical structure information of the transistors. An advanced training method utilizing the different parameters to adjust the different characteristics of the packaged transistors is developed to make the proposed model match the device data efficiently and accurately. Measured data of radio frequency (RF) power laterally diffused metal-oxide semiconductor (LDMOS) transistor are used to verify the capability of the proposed Neuro-SM method. The results demonstrate that the novel Neuro-SM model is more accurate and efficient than existing device models.

With the development of electronic technology, the accurate computer-aided design (CAD) models of transistors play a decisive role in the circuit/system design with high performance and reliability [

Package modeling for active/passive devices have been a field of strong interest in recent years [

Recently, Neurospace Mapping (Neuro-SM) techniques have been recognized as useful alternatives to conventional approaches in microwave modeling [

In this paper, we proposed a new modeling method for packaged transistor based on Neuro-SM. The proposed method roughly divides the packaged transistor into three parts: the input package circuit, the nonlinear circuit, and the output package circuit, and they are built, respectively. In addition, an advanced training method making the novel model match the device data effectively is developed, which can avoid the mutual interference of the optimized parameters for the different performance of model. To verify the availability of the proposed modeling approach, a practical example on modeling RF power LDMOS transistor is presented.

Packages of transistors typically contain a metal flange and a dielectric window frame. The transistor is bonded to the die-bond area inside the cavity of the window frame. Metal leads are provided at the input and output sides of the window frame to allow for connection to external circuitry. Based on the physical structure of packaged transistor, we propose to roughly divide the total structure into three parts: the input package circuit, the nonlinear circuit, and the output package circuit. The proposed Neuro-SM modeling method creates the CAD modules for the three parts, respectively, and an additional

There are 4 modules in the novel Neuro-SM model of the packaged transistor: the input package module, the nonlinear module, the output package module, and the

Block diagram of the proposed packaged transistor model.

Scattering-matrix analysis is applicable to any general microwave circuit configuration when all the circuit components are modeled in terms of their scattering parameters. The

There are two reasons for employing package circuit for RF/microwave transistors. The first one is the environmental ruggedness and the mechanical strength which can protect the internal circuit of transistor. The second one is to ease external matching-circuit design and improve device performance by adding an internal matching circuit into the package circuit. To achieve high gain or efficiency, lots of active cells are added to the transistor, which result in more bond wires; MOS capacitors and integrated capacitor are used to make electrical connections. The complex structure of package circuit greatly increases the difficulty of modeling. The package modeling method we proposed can be applied to arbitrary packaging structures, because the advanced package module is achieved only using the terminal signals, instead of the internal and physical structure information of the package circuit.

The block diagram of the package module is shown in Figure

Block diagram of the proposed package module. (a) Block diagram of the proposed input package module. (b) Block diagram of the proposed output package module.

In the proposed package module, _{ANN} and_{ANN} represent multilayer feedforward neural network and _{ANN} and_{ANN}, respectively.

Let

In order to perform the nonlinear characteristic of active cells in packaged transistor, Neuro-SM modeling method in literature [

Block diagram of the nonlinear module.

In the nonlinear module, when the coarse model operates with the signals

Precise models rely on reasonable parameters except for the correct model structure. The most important step during neural network modeling is to find a suitable set of weights by the training process. Let the training error measure the learning performance of the proposed model. Let the test error measure the predictive ability of the proposed model. The training process is performed until both the training error calculated with the training data and the test error calculated with the test data meet the accuracy requirements. The same error function of DC and

The optimized parameters in the proposed model consist of

Send the bias voltage of the fine model to the mapping network in the nonlinear module. Initialize the weight

Adjust the weight

Adjust the weights

Train the proposed Neuro-SM model with DC and

The proposed training method enhances the advantage of the existing training method by adjusting the parameters in steps. The proposed method controls the DC/AC performance of the Neuro-SM model with different weight parameters, which reduce the mutual interference of the optimized parameters for the different performance of model and avoid changing the optimized parameters repeatedly.

RF power LDMOS transistor is the technology of choice, due to its low power consumption, high mechanical hardness, and the inherent economic advantages that silicon wafer manufacturing offers. To verify the accuracy and feasibility of the proposed Neuro-SM modeling method, the I-V and

Training data and test data for DC and S-parameter modeling of LDMOS transistor.

| | | ||
---|---|---|---|---|

DC Simulation | Training Data | 2.6:0.1:3.2 | 0:2:32 | |

Test Data | 2.6:0.1:3.2 | 1:2:31 | ||

| ||||

| Training Data | 0:1:1 | 8:4:24 | 1.7:0.028:3.1 |

2.5:0.1:2.8 | 30 | |||

0:0.2:2.2 | 28 | |||

2.3:0.1:2.8 | ||||

Test Data | 0:1:1 | 10:4:26 | 1.7:0.028:3.1 | |

2.5:0.1:2.8 | ||||

0.1:0.2:1.1 | 28 | |||

1.5:0.2:2.1 | ||||

2.45:0.1:2.75 |

In this example, Angelov model is used as the existing coarse model. At present, Angelov model which can match many types of transistors is considered to be the great nonlinear model. Choosing Angelov model as the coarse model improve the general applicability of the new modeling method. The mismatch between the coarse model and the measured data of the LDMOS transistor cannot be ignored even by optimizing the parameters in the coarse model as much as possible. Then, the input/output package modules and mapping network are applied. The new model is trained as the four steps introduced in Section

Accuracy comparison of coarse model and proposed models for DC and

Parameter | Coarse Model | Proposed Model |
---|---|---|

| 1.01 | 0.85 |

| 21.61 | 2.18 |

| 25.87 | 3.12 |

| 23.81 | 3.97 |

| 36.68 | 3.79 |

| 10.29 | 2.02 |

| 4.99 | 2.07 |

| 24.18 | 2.01 |

| 40.40 | 2.19 |

In order to further show the detail results, the I-V comparison of the coarse model and the proposed model is shown in Figure

I-V comparison between measured data, coarse model, and proposed model for the LDMOS example.

Comparison of

After being trained with DC data and

Plot of the gain and PAE between measured data, coarse model, and proposed model for the LDMOS transistor.

A new Neuro-SM modeling approach has been proposed for packaged transistors. The novel model structure can accurately reflect the characteristics of both the active cells and the packaged circuit. This allows existing models to exceed their current capabilities. The advanced training method avoids repetitive adjustment of the optimization parameters improving the modeling efficiency. Good results are verified by the practical example. In the future, we can extend the proposed modeling method to further improve the larger-signal characteristic of the package transistors. Another potential future direction is to apply the proposed method in this work to the trapping behaviors of the gallium nitride transistors, meeting the needs of contemporary technology.

The data used to support the findings of this study comes from the author herself and may not be available for publication for the time being.

The authors declare that there are no conflicts of interest regarding the publication of this paper.

This work was supported by the National Natural Science Foundation of China (Grant no. 61601323), the Scientific Research Project of Tianjin Education Commission (Grant no. 2017KJ088), and the Tianjin Natural Science Foundation (Grant no. 17JCQNJC01400).