Ultra-Low-Voltage CMOS-Based Current Bleeding Mixer with High LO-RF Isolation

This journal presents an ultra-low-voltage current bleeding mixer with high LO-RF port-to-port isolation, implemented on 0.13 μm standard CMOS technology for ZigBee application. The architecture compliments a modified current bleeding topology, consisting of NMOS-based current bleeding transistor, PMOS-based switching stage, and integrated inductors achieving low-voltage operation and high LO-RF isolation. The mixer exhibits a conversion gain of 7.5 dB at the radio frequency (RF) of 2.4 GHz, an input third-order intercept point (IIP3) of 1 dBm, and a LO-RF isolation measured to 60 dB. The DC power consumption is 572 µW at supply voltage of 0.45 V, while consuming a chip area of 0.97 × 0.88 mm2.


Introduction
Various low-power front-end receivers had been widely reported for application such as wireless sensor network (WSN). WSN application which requires low-power operation often adopts ZigBee standard with the operating frequency ranging from 2.4 to 2.4835 GHz [1]. Direct conversion receiver (DCR) has been in the heat of discussion in recent years due to its inherent low power consumption and the simplicity in realization [2]. One of the major setbacks associated with DCR is the LO to RF port-to-port isolation. An incurred mismatch in the device physical dimension would potentially couple the LO leakage to the RF port through the gate-drain capacitance, gd of the RF transconductance transistors. The leakage component will mix with RF signal, resulting in a detrimental phenomenon known as self-mixing [3] which in effect produces DC offset that degrades the performance of the overall receiver. In preference, high isolation between the LO-RF ports is crucial in alleviating self-mixing. The typical LO-RF isolations of the standard Gilbert cell mixer are in the range of 40-50 dB [4]. In this paper, the conventional current bleeding architecture which has a high conversion gain and low noise figure is modified by integrating a combination of NMOS-based current bleeding transistor, PMOS-based LO switch, and integrated inductors, thus improving the isolation between the LO and RF port.

Proposed Design
Previous design: Figure 1 shows the conventional CMOS current bleeding mixer that integrates a combination of PMOS-based current bleeding stage and NMOS-based local oscillator, LO switching stage [5].
In effect to the mismatch in the switching stage, the LO leakage component at nodes 1 and 2 will directly couple to the RF port through the gate-drain capacitance, gd , of the RF transconductance stage ( 1 -2 ). This will adversely reduce the isolation between the LO and RF ports. Figure 2 shows that the proposed mixer consists of a RF transconductance stage ( 1 -2 ), a PMOS-based LO switching input ( 3 -6 ), a NMOS-based current bleeding stage ( 7 -8 ), and the output load ( 1 -1 and 2 -2 ). Inductors 1 and 2 act as a RF choke in alleviating the RF   signal leakage into the voltage supply, DD . The RF frequency is mixed with the LO frequency at node 1 and 2 . The differential output current, neglecting the higher order spurs, can be derived as follows: where 1,2 is the transconductance for 1 and 2 and V RF is the input RF signal, while RF and LO are the RF and LO frequency, respectively. At the IF output, the combination of 1 -1 and 2 -2 forms a low pass filter (LPF), which filters out the high-order spurs at the output such as the upconverted frequency component sin( RF + LO ).
An incurred mismatch in the LO switching transistor physical dimension would result in a feed-through of LO leakage at nodes 1 and 2 to the RF port as described in Figure 2. The dotted arrowhead illustrates the LO leakage path from the LO ports to nodes 1 and 2 .
Other than for providing a desirable bleeding path for the DC current, transistor 7 -8 is optimized to enhance the LO-RF isolation. Transistors 7 and 1 are cascoded in series, thus observing high impedance, referring to the drain terminal of the bleeding transistor 7 , expressed as where 7 and 7 are the transconductance and output resistance for 7 while 1 is the output resistance for transistor 1 . Accordingly, this high impedance node minimizes the LO leakage from nodes 1 and 2 to the RF port. As a bench of comparison to the design in Figure 1, the LO leakage component at nodes 1 and 2 would directly couple to the RF port through parasitic capacitance gd in the absence of additional shielding between LO-RF port. The proposed mixer on the other hand utilizes the bleeding transistor ( 7 and 8 ) as the shielding element between LO and RF port to improve the LO-RF isolation. In addition, the high frequency LO leakage at the output node of IF+ and IF− as shown in Figure 2 is insignificant as it is directed towards the ground rail via the low impedance path of capacitor 1 and 2 in contrary to the conventional architecture where the leakage component couples to the RF port. Additionally any LO leakage at the IF output port is further attenuated by load resistor (1,2) before reaching the RF port, in a goal of improving the LO-RF isolation.
Along with the presence of the cascoded configuration between transconductance and the bleeding stage, this mixer is able to work down to 0.45 V of supply headroom. The conventional current bleeding mixer as shown in Figure 1 requires an LO bias of where LO is the DC voltage to bias the switching transistors, gs3 is the gate to source voltage of transistor 3 , and ds1(sat) is the overdrive voltage of transistor 1 . By adapting PMOSbased LO switching stage ( 3 -6 ), coupled together with inductors 1 and 2 as illustrated in Figure 2, the DC voltage required to bias the gate of transistor 3 -6 is reduced to only sg (source-gate voltage) which approximate to the threshold voltage, th of the PMOS transistor, whereas the DC voltage at nodes 1 and 2 approaches to DD . The LO bias voltage LO is given as where th3 is the threshold voltage of transistor 3 . The DC voltage required to turn on the LO switching stage no longer depended on the overdrive voltage, ds1,2(sat) of the transconductance stage ( 1 -2 ) as given in (3). In this proposed mixer, the DC voltage for LO nears ground potential instead of the positive power rail resulting the design to operate favorably at ultra-low supply headroom. As for the conventional current bleeding mixer architecture as in Figure 1, the DC bias voltage for LO moves towards the positive rail providing a bottleneck in operating the mixer at low supply headroom.
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Measurement Result
The proposed mixer is implemented on a 0.13 m standard CMOS technology. The mixer consumes only 1.27 mA of DC current from 0.45 V of supply voltage. The LO-RF isolation in dB is given as [10] Isolation (dBm) = flo(LO) (dBm) − flo(RF) (dbm) , (5) where Isolation is the isolation between LO and RF port due to the leakage component from LO port, flo(LO) is the injected LO power at LO port, and flo(RF) is the observed LO power coupled to the RF port. The LO-RF isolation has been measured at a difference discrete LO power as described in Figure 3. It can be observed that from the frequency of 2 GHz to 5 GHz, the isolation achieved is more than 55 dB and at 2.4 GHz, the LO-RF isolation is measured at 60 dB. The isolation technique adapted in this circuit has improved the LO-RF shielding significantly while operating at ultra-low supply voltage down to 0.45 V. Figure 4 shows the results for LO-IF isolation which measures more than 64 dB at 2.4 GHz. Two-tone test with an input frequency of 2.443 GHz and 2.442 GHz is applied to the RF port with the corresponding LO frequency of 2.439 GHz to quantify the linearity of the mixer. The conversion gain of the proposed mixer is observed to be 7.5 dB with an IIP3 of 1 dBm as shown in Figure 5. Inductors 1 and 2 in the proposed mixer of Figure 2 not only function as the DC current source but concurrently resonate out the parasitic capacitance at nodes 1 and 2 to improve the IIP3. The noise figure (NF) is observed to be around 18 dB as illustrated in Figure 6. Table 1 summarizes the design parameters for the proposed mixer and the performance comparison of the proposed architecture respective to other reported works is given in Table 2. The designed mixer has the highest LO-RF isolation   and among the lowest in DC power consumption. The measured conversion gain and linearity, IIP3, of the mixer is 7.5 dB and 1 dBm, respectively. The dynamic performance of the architecture is evaluated adapting a figure of merit (FOM) expression, which is highlighted in the following equation, given as [11]: FOM = 10 log ( 10 /20 ⋅ 10 (IIP3−10)/20 10 NF/10 ⋅ ) , where is the conversion gain in dB, IIP3 is the third order linearity in dBm, NF is the noise figure in dB, and is the power in mW. In reasoning out the performance comparison respective to other reported recent work, the proposed architecture exhibits the highest FOM of 16.67 while relating to power dissipation well below 1 mW. In the loop of recent reported work, the proposed architecture process to be the lowest in power consumption. The photomicrograph of the chip is illustrated in Figure 7, with a corresponding chip area of 0.97 × 0.88 mm 2 .

Conclusion
The proposed mixer is successfully designed and verified in 0.13 m standard CMOS technology. The implemented CMOS-based current bleeding mixer topology, which consists of a combination of NMOS-based current bleeding transistor, PMOS-based switching stage, and integrated inductors, has significantly improved the LO-RF isolation while operating at supply voltage headroom down to 0.45 V. The design observes a considerable high LO-RF isolation of 60 dB and consuming merely 572 w of power, which is a promising performance metric for ZigBee application.