The signal integrity of the circuit, as one of the important design issues in highspeed digital system, is usually seriously affected by the signal reflection due to impedance mismatch in the DDR3 bus. In this paper, a novel optimization method is proposed to optimize impedance mismatch and reduce the signal refection. Specifically, by applying the via parasitic, an equivalent model of DDR3 highspeed signal transmission, which bases on the match between the ondietermination (ODT) value of DDR3 and the characteristic impedance of the transmission line, is established. Additionally, an improved particle swarm optimization algorithm with adaptive perturbation is presented to solve the impedance mismatch problem (IPSOIMp) based on the above model. The algorithm dynamically judges particles’ state and introduces perturbation strategy for local aggregation, from which the local optimum is avoided and the ability of optimizationsearching is activated. IPSOIMp achieves higher accuracy than the standard algorithm, and the speed increases nearly 33% as well. Finally, the simulation results verify that the solution obviously decreases the signal reflection, with the signal transmission quality increasing by 1.3 dB compared with the existing method.
As the most popular memory, DDR3 illustrates faster speed, higher data rate, and lower operating voltages than DDR2, with the data rate up to 1.6 Gbps or even higher at the operating voltage of 1.5 V. However, DDR3 memory requires more in its interconnect interface design while bringing higher data transmission rate. During the highspeed signal transmission, sudden changes of transient impedance will lead to discontinuity of signal line impedance, which results in signal reflections and thus substantial overshoot, undershoot, and ringing. Therefore, researching the signal reflection of DDR3 bus has become a key component in the design of highspeed digital system.
There has been considerable research on optimization of DDR3 bus signal quality. Jagdale et al. [
The research above shows that in DDR3 bus design, the discontinuity of characteristic impedance is the primary factor causing signal reflection, which indicates that an appropriate ODT value could effectively decrease impedance discontinuity of signal transmission line. Jagdale et al. [
Multiple factors being considered are bound to bring greater difficulties in the circuit optimization. Particle swarm optimization (PSO) [
Li et al. [
In this paper, how to improve the efficiency while maintaining initial high performance is the key point. The major contributions of this paper are as follows: (1) an improved optimization strategy, which combines the characteristics of embedded hardware, is proposed in this paper for design of DDR3 highspeed bus. The strategy considers the impact of via on highspeed signal; (2) we propose an improved particle swarm optimization algorithm with adaptive perturbation, which optimizes routing length of DDR3 signal, characteristic impedance, via parasitic impedance, and the impact of ODT on highfrequency signal quality; (3) the experiments demonstrate that the strategy proposed could improve effectively impedance continuity of transmission line and reduce reflection effects of highspeed signals.
The rest of this paper is organized as follows. In Section
In high frequency, interconnection lines exhibit characteristics of transmission lines. Thus, distributed model of lossy transmission line cascaded by
Transmission line equivalent model.
The driver and the load do not have signal reflection when
Via is the conductor connecting the lines of different signal layers in multilayer PCB. Studies [
Figure
Via equivalent model.
Since parasitic capacitance, parasitic inductance, and parasitic resistance exist in via, via leads to impedance discontinuities on highfrequency signal transmission line, which results in signal reflection. Figure
The impact of the via on signal reflection.
It is easily seen that via effects on signal reflection are even obvious when the frequency exceeds 1 GHz. The line between DSP processor and DDR3 pins inevitably has at least two vias, and the data rate can reach 1.6 Gb/s or even higher; therefore, the effect of via’s parasitic resistance, parasitic inductance, and parasitic capacitance on high frequency signal cannot be ignored. And the discontinuity occurred leads to issue of signal reflection, which should be considered in design of DDR3 highspeed bus interconnection [
In this section, transmission coefficient and reflection coefficient for DDR3 bus transmission line are obtained through parameter
the two vias connecting the three transmission lines are presented by
the length of the three transmission lines is, respectively, denoted by
the characteristic impedance of the three transmission lines is, respectively, denoted by
the internal impedance of the source and load is presented by
the power of source end and load end is, respectively, denoted by
Highspeed transmission line structure.
According to the electromagnetic theory, each transmission line is subject to interference from surrounding transmission lines, especially the adjacent lines. Therefore, we take three adjacent transmission lines as study object in this paper in order to approximate the actual circuit, provided that (1) the length of a transmission line is
Driver line and victim line model.
The first RLC unit of victim line is analyzed first. According to the basic circuit theorem, we obtain the following:
When
Given that (1) the via impact on highspeed bus is considered, (2) the impact among vias is ignored, and (3) Figure
The
Similarly, reflection coefficient
Equation (
Due to the lossy transmission, signal of sending end cannot be sent to the receiving end completely. Moreover, due to the coexistence of transmission signal and reflection signal, improving quality of signal received needs to reduce the reflection signal and enhance the transmission signal. And thus the fitness function for DDR3 bus should be defined according to both the transmission signal and the reflection signal. Provided that the transmission line is lossless when writing to DDR3, we can obtain the following according to conservation of energy:
Equation (
Similarly, when reading from DDR3, the fitness function could be obtained as follows:
We get from (
Equation (
The parameters in the fitness function.
No.  Name  Description  Range 

1 

Length of transmission lines 

2 
 
3 
 


4 

Impedance of transmission lines  20 Ω 
5 
 
6 
 


7 

Radius of the via 



8 

Length of the via 



9 

Value of driver resister in writing 



10 

Value of driver resister in reading 



11 

ODT in writing 



12 

ODT in reading 

It should be noted that values of
Equation (
The above discussion tells us that the problem is transformed into the optimization of nonlinear function with multiple parameters. Exactly speaking, 12 parameters of them need to be optimized in this problem. Due to the premature convergence of standard PSO algorithm which is easy to fall into local optimal, we present an improved particle swarm optimization algorithm for solving impedance mismatch problem (IPSOIMp).
In this section, the IPSOIMp is proposed and described. By analyzing the particle movement during PSO algorithm optimization, it can be easily seen that the main reason leading to particle local optimum is that global optimal particle is too dependent on the individual optimal solution [
By the definitions of the particle position, each particle represents a feasible solution of the impedance mismatch problem in the IPSOIMp.
The range of each parameter is different, where
In (
According to velocity updating, the position updating in this paper adopts Algorithm
Procedure
Assume
if (
end if
else if (
(
(
)
end if
else if (
end if
else if (
end if
end procedure
According to dynamic behavior of the particles, the optimal solution will tend to a specific value after several iterations, which indicates that particle swarm has been or will be trapped into local optimal state according to the existing trajectory. The global optimal value, which reflects the current state of the particle swarm, could be adopted to conduct adaptive perturbation. Since the fitness function proposed aims to find the minimum value after successive
In summary, the algorithm IPSOIMp includes the following steps.
Define individual particles of 12dimensional space by taking the 12 parameters of fitness function as elements, and particle swarm size is set to
Initialize population particles randomly according to the constraint range of 12 parameters.
Calculate adaptive value for each particle according to the fitness function established by (
Update velocity and position for each particle in accordance with (
Calculate adaptive value for each particle again according to (
According to the global optimal value, judge the particle aggregation state by (
Judge whether the iterative precision or the number of iterations are reached. If not, turn to Step
The simulation experiment is conducted on multicore DSP processor and DDR3 interconnect bus, taking IBIS model of TI TMS320C6678 and Samsung K4B4G1646B as simulation models, respectively. Considering typical routing of PCB and the signal quality, the transmission line connecting DSP and DDR3 is abstracted into 2 vias and 3 sections of transmission line. The length of these transmission lines is
To be consistent with the actual design, the specific parameters for simulation are listed in Table
Design and simulation of parameters.
Parameter  Value 

IPSOIMp  
Swarm size  50 
Iteration  100 
Inertia weight  0.4~0.9 
Constant acceleration  2 
Signal parameter  
Amplitude  1.5 V 
Data rate  1.6 Gbps 
Rise time  50 ps 
Other  
Permittivity  4.5 
Stackup thickness  0.8 mm 
Line space  5 mil 
To illustrate the performance of IPSOIMp algorithm, the standard PSO, IPSO [
The comparison is shown in Table
Comparison of different optimization algorithms.
Algorithm  Best fitness ( 
Cost time (s) 

PSO  3.5247  71 
IPSO  0.9125  63 
IPSOIMp 


Comparison of different optimization algorithms.
IPSOIMp algorithm guarantees the efficiency of early optimization. In later optimization, once the particles are found in local optimal aggregation, the movement perturbation is launched, from which particles are activated, founding the better value around and obtaining global optimum. Although the optimization results of IPSO and IPSOIMp are approximately equal, the iteration speed of IPSOIMp is faster nearly 12% than IPSO. That is because the latter introduces perturbation too early, resulting in increasing of the number of iterations. Compared to the standard PSO algorithm IPSOIMp improves the accuracy significantly and the speed increases nearly 33%.
In addition, the same circuit is optimized using the approach given in [
The results of parameter optimization.
Parameter  This paper  Reference [ 

Line length  

200 mil  346 mil 

1356 mil  951 mil 

128 mil  581 mil 
Impedance  

48 Ω  44 Ω 

45 Ω  47 Ω 

52 Ω  55 Ω 
Write DDR3  

34 Ω  34 Ω 

60 Ω  60 Ω 
Read DDR3  

40 Ω  40 Ω 

60 Ω  60 Ω 
The radius of the via ( 
6 mil  — 
The length of the via ( 
1.6 mm  — 
When the radius and the length of via are less than or equal to 6 mil and 1.6 mm, respectively, the influence of continuity in signal transmission changes slightly. For the actual design of 12 layers when considering the plate making technology, the via radius
ADS simulation software is used to verify validity of the optimized parameters from two aspects, frequency domain and time domain. Reading and writing circuits need to be designed, respectively, in our experiments, with parameters configured according to Table
During the transmission of highspeed signal, transmission constant should be close to 0 dB if impedance of transmission path is completely matched. Yet, due to the influence of many factors such as routing density and via parasitic effect, impedance discontinuity in transmission path emerges, leading to signal reflection and thus signal loss. Simulation results in frequency domain are shown in Figure
Simulation results for frequency domain.
The preoptimized design (before OPT) does not consider various factors causing impedance discontinuity, which mainly comes from improper selection of values in transmission lines, vias parameters, and ODT; thus, the signal at the receiving end suffers from serious loss. According to simulation result after optimization, we observe that our method (proposed) obviously reduces signal loss compared with the strategy presented in [
The main reason involves two aspects. Firstly, the parasitic effect of via is not obvious in low frequency. Yet, the impact of via on signal reflection starts manifesting with the increasing of frequency. Due to proper selection of via parameters in the signals optimization, the characteristic impedance of the transmission line achieves matching, which improves the impedance continuity. Secondly, IPSOIMp obtains better accuracy than standard PSO.
In order to analyze the effectiveness of our optimization strategy in the time domain, this section achieves the eye diagram simulation of DDR3 reading and writing circuits. The data rate is set to 1.6G bps and each data line transmits random number. The simulation eye diagram before optimization is shown in Figure
Simulation eye diagram for the general design.
Simulation eye diagram for the method of [
When adopting the approach we proposed, the simulation eye diagram of DDR3 reading and writing circuits is given in Figure
The details of eye diagrams.
Write to DDR3  Read from DDR3  

General design  
Magnitude (mV)  424.52  428.37 
Width (ps)  560.34  548.21 
Reference [ 

Magnitude (mV)  584.14  579.36 
Width (ps)  577.44  572.62 








Simulation eye diagram for the proposed method.
This paper presented an enhanced optimization strategy for DDR3 highspeed bus design, which aims to reduce the signal reflection. The strategy obtains parasitic effects of via specifically for equivalent circuit model through theoretical derivation. Additionally, we proposed an improved particle swarm algorithm to optimize the parameters in highspeed bus design. The experiments of frequency domain and time domain demonstrate that the strategy proposed could improve effectively impedance continuity of transmission line and reduce reflection effects of highspeed signals. The superiority is even more obvious with the increasing data transfer rate. It provides the referential meaning for the design of DDR4 and even higher speed bus.
The authors declare that there is no conflict of interests regarding the publication of this paper.
The authors would like to thank the anonymous reviewers for their helpful comments and suggestions. This work was supported by the National Science Fund for Distinguished Young Scholars (no. 61125206), NSFC (no. 61272347), and Scientific Research Common Program of Beijing Municipal Commission of Education (no. KM201410011005).