50 MHz-10 GHz low-power resistive feedback current-reuse mixer with inductive peaking for cognitive radio receiver.

A low-power wideband mixer is designed and implemented in 0.13 µm standard CMOS technology based on resistive feedback current-reuse (RFCR) configuration for the application of cognitive radio receiver. The proposed RFCR architecture incorporates an inductive peaking technique to compensate for gain roll-off at high frequency while enhancing the bandwidth. A complementary current-reuse technique is used between transconductance and IF stages to boost the conversion gain without additional power consumption by reusing the DC bias current of the LO stage. This downconversion double-balanced mixer exhibits a high and flat conversion gain (CG) of 14.9 ± 1.4 dB and a noise figure (NF) better than 12.8 dB. The maximum input 1-dB compression point (P1dB) and maximum input third-order intercept point (IIP3) are −13.6 dBm and −4.5 dBm, respectively, over the desired frequency ranging from 50 MHz to 10 GHz. The proposed circuit operates down to a supply headroom of 1 V with a low-power consumption of 3.5 mW.


Introduction
As the number of new wireless applications advents tremendously, the demand for additional frequency spectrum allocation has been growing rapidly. However, the former practice of fixed spectrum allocation policy suffers from the low spectrum utilization setback and this sets a limitation in the available spectrum of accommodating the next generation wireless applications and services [1]. The inefficiency in spectrum usage and the shortage in spectrum have motivated the evolution of CRs. CR was deemed to be an innovative approach due to its versatility in the context of sensing local spectrum reliably and utilizing unoccupied frequency spectrum in the targeted spectral range, while abstaining interference for licensed user by favourably altering its receiving and transmitting parameters [2]. The first international regulation which establishes CRs based system is IEEE 802. 22, where the access of unlicensed CR devices on (TV) frequency spectrum (54 MHz-862 MHz) is permitted [3].
Due to excessive demand and technology advancement, the CRs have a greater potential to be expanded further from the constraint of TV band [4].
In the realization of CRs function, a wideband receiver is required to encapsulate the entire aspired frequency band instead of the conventional practice where multiple receivers are envisioned to cover different frequency bands. This highlights the importance of wideband mixer in RF frontend receiver circuit to perform frequency translation. This paper focuses on the design of low-power wideband mixer with a flat and high CG frequency response, along with a flat and low NF frequency response and an adequate linearity over a wide frequency range for CR receiver application. On the platform of CMOS technology, several state-of-the-art architectures for wideband mixer have been reported [5][6][7][8][9][10][11][12][13][14][15]. The double-balanced Gilbert cell mixer has been the mainstay of development in wideband mixer due to its inherent characteristics of high CG and high port-to-port isolation [16,17]. However, a high CG is inherited at the penalty of 2 The Scientific World Journal high bias current which concurrently contributes towards the flicker noise problem and voltage headroom limitation. In the advantage of minimizing the load resistance in addressing the limitation of voltage headroom, the CG of the mixer is adversely affected. In [18], current-bleeding technique is used to mitigate the output voltage headroom problem by steering the DC current flow through the load resistance. However, this approach is not a preferred solution as the total power consumption remains the same as in conventional Gilbert cell architecture. In addition, the parasitic capacitance introduced by the bleeding transistors not only limits the operating bandwidth, but also degrades the CG by channelling a signal leakage path to the substrate ground.
The well-defined folded-cascode mixer is envisaged to surmount the drawbacks that exist in the Gilbert cell mixer. Instead of stacking the switching stage above the transconductance stage, the folded-switching stage is a promising solution to overcome the voltage headroom limitation. The folded-cascode mixer presented in [19] exhibits a narrow band response and it is not suitable for CR application. Hence, a wideband matching network is integrated at the input mixer to achieve a wideband operating frequency [15]. The mixer input matching circuit not only is crucial as an interstage matching in cascaded systems, but also is essential to ensure the wide bandwidth performance by providing a low input reflection loss across the frequency range.
The RFCR mixer [7,20] with folded-cascode structure is widely adapted in recent reported work due to the inherent wideband input matching characteristic with low NF and high gain. Although the RFCR architecture had shown good inherent performance but there is severe contradiction in improving wideband input matching and noise due to the large gate-source parasitic capacitance of the input stage transistors. Therefore, a -match LC network is introduced in [21] to enhance the input matching by creating an extra zero while reducing gate noise by series resonance ofin at high frequencies. The reported low-voltage, low-power RFCR mixer architecture in [7] achieves a high CG over wide range of frequency bandwidth in 65 nm CMOS technology. As the DC current-reuse is not feasible in a folded architecture, the cost of this implementation would be in increased power consumption relative to the technology of implementation.
The effect of even-order distortion in CRs is more critical than narrow band receivers [4]. This distortion is heavily attributed to the presence of asymmetric mismatch in the downconversion mixer and it causes disturbance to the desired channel. To alleviate this distortion effect, a balanced circuit with differential architecture and symmetrical physical layout is preferred. In this work, a low-voltage, lowpower and double-balanced wideband mixer integrates amatch LC network at the input mixer to meet wideband input matching performance. The complementary current-reuse topology [22] improves the power consumption of mixer while enhancing the RF input transconductance. In addition, an inductive peaking is also employed to improve the mixer noise and conversion gain flatness. The proposed mixer is extracted, simulated, and verified on 0.13 m standard CMOS platform. This paper is organized as follows. Section 2 reviews and highlights the design limitations and performance tradeoffs in conventional RFCR mixer. In Section 3, the circuit topology and operation principles of the proposed mixer are presented. An insight into RFCR mixer operation is given by analyzing the innovative techniques that are adapted to overcome the limitations in confirming the stringent requirements for CR application. Section 4 reports the RCextracted postlayout simulation results and Section 5 presents the conclusion.

Design Challenges
Several publications were reported on RFCR architecture [7,20,23] which can be amenable to both narrow and wideband applications. The RFCR architecture is more viable design for wideband system due to its inherent wideband input matching, low-power consumption, and high gain characteristics. In typical wide bandwidth application, a flat frequency response of gain and NF is preferred across the operating frequency. However, the conventional RFCR architecture tends to suffer from poor NF performance although the CG can be flattened across the range of wide bandwidth due to intrinsic conflict between flat gain and flat NF [21,24,25]. Therefore, the conventional RFCR architecture is reviewed in order to analyse the performance parameter trade-offs, which limit the extension of the operational bandwidth. The architecture of Figure 1(a) illustrates the common singlebalanced RFCR mixer with the simplified equivalent small signal representation of the transconductance stage given in Figure 1(b). Transistor 1,2 represents the RF input transistor; transistor 3,4 is LO switching pair; capacitor ac is the DC-decoupling capacitor; capacitor is the emulation of the parasitic capacitance at node while resistors , fb , and (1,2) represent the input source resistance, feedback resistor, and load resistor, respectively.
At low frequency, the frequency-dependent component is negligible. From Figure 1(b), the input impedance, in can be defined as follows: where V is the open-loop gain, computed as , in which is the RF input transconductance represented as 1 + 2 and is 1 2 . Equation (1) reveals that input impedance of the RFCR circuit is mainly determined by resistor fb and transconductance . In order to achieve an input reflection coefficient, |Γ| ≤ −10 dB, with respect to a source impedance of = 50 Ω, yields in in a range of 25 Ω to 100 Ω [7,21].
The voltage gain and noise factor of the transconductance stage can be derived as where is the ratio between the device transconductance and the zero-bias drain conductance, while is the channel The Scientific World Journal Switching stage thermal noise coefficient. From (1) and (3), it can be observed that there is a close relationship between input impedance matching and NF. The NF can be significantly improved by increasing the RF input transconductance and the value of resistor fb at the expense of the input impedance matching performance. However in practical circuit implementation, the parasitic capacitances introduced by the gate of input transistors further exacerbate the input matching especially at high frequencies. The frequency dependent component is taken into account to finalize the limitation of wideband operating bandwidth; thus (1) can be rewritten as follows: where gs = gs1 + gs2 . From (4), as in = = 50 Ω for the perfect matching condition, the maximum gate-source parasitic capacitance can be expressed as follows: where represents the input port impedance and is the cut-off frequency. Based on (5), at the targeted input matching of −10 dB with an upper corner frequency of 10 GHz respective to a source impedance of = 50 Ω, the maximum capacitance gs,max which is contributed from both NMOS and PMOS input transistors equals 200 fF. Evidently, a comparative small parasitic capacitance reflects to a small aspect ratio of RF input transistors which concurrently creates limitation in boosting the RF input transconductance and achieving low noise performance.
In addition to this trade-off, the investigation of noise contribution from switching stage reveals more setbacks which further degrade the mixer's performance. The total output noise of a mixer consists of thermal noise and flicker noise. The thermal noise which is mainly dominated by the transconductance stage can be easily reduced by increasing the bias current. The switches in an active mixer predominately contribute towards the growth of flicker noise at the mixer's output. The flicker noise articulated by the LO switches exists at the output of the mixer via direct and indirect mechanism [26]. The flicker noise in effect through the direct mechanism is due to random modulation of the duty cycle of the output current, whereas through the indirect mechanism it is caused by charging and discharging of the parasitic capacitances between transconductance and LO stages. The output noise current generated by the direct mechanism and indirect mechanism is given as in the following [26,27]: The Scientific World Journal where tail,sw is the DC tail current in switching stage, is the equivalent flicker noise of the switching pair, is the slope of LO signal, is the LO period, is the parasitic capacitance at switching tail, LO is the frequency of LO signal, and ,sw is the transconductance of switching transistor. In reference to (6) and (7), the direct and indirect noise currents are evidently proportional to the flicker noise voltage, of LO transistor which is expressed as in the following: where is the technology parameter, eff and eff are the effective width and length of LO transistor, respectively, ox is the oxide capacitance of LO transistor, and is the operating frequency. Apparently, in order to minimize the flicker noise effect caused by the direct mechanism, low DC current at the switching stage and large size of LO transistor are preferred. On the contrary, the larger size of LO switching transistor yields to a larger parasitic capacitance, at node as referred to in Figure 1(a). This results in an increase of noise current from indirect mechanism as can be observed from (7). In addition, the capacitance also creates detrimental effect at high frequency by introducing a low impedance path for RF signal which shunts the RF signal to the ground, thus reducing the CG and adversely limiting the operational bandwidth. This effect can be mathematically proven by deriving the pole frequency of the effective transconductance of the mixer in Figure 1(a) as in the following: where eq is total resistance at the node . Hence, the pole frequency of the mixer which plays a crucial role in determining the operating bandwidth of the mixer core can be derived as It is noted that the capacitor forms as a low-pass filter at the tail of switching quad, where the gain response rolls off beyond the cut-off frequency. Therefore, it can be concluded that obtaining a large operation bandwidth with relatively large capacitor at node is not feasible. This has driven the need for the exploration of new design technique to achieve large bandwidth performance.

Proposed Mixer
The proposed RFCR mixer illustrated in Figure 2 consists of RF input transistors 1,2 , current-reuse PMOS bias transistors 3,4 , feedback resistor fb (1,2) , DC-decoupling capacitor ac (1,2) , switching transistors 7 -10 , peaking inductor (1,2) , and passive load of (1,2) and (1,2) . The folded architecture is preferred over the conventional series stacking topology due to its merit in low voltage headroom realization. The minimum voltage headroom that can be applied to the designed circuit is approximated as DD,min = ds1,2(sat) + ds3,4(sat) + th, + th, , where ds1,2(sat) and ds3,4(sat) are the overdrive voltage of transistors 1,2 and 3,4 , respectively, while th, and th, are the respective threshold voltage of the transistors 1,2 and 3,4 . The transconductance stage is realized through the integration of inverter with feedback resistor, fb (1,2) . At the transconductance stage, PMOS transistor 3,4 is stacked at the top of NMOS transistor 1,2 to form a current-reuse topology. Therefore, the transistor 3,4 enhances the RF input transconductance ,RF to (1,2) + (3,4) without additional power consumption compared to a single Ntype common source amplifier associated with an RF input transconductance, ,RF = (1,2) . In addition, the PMOS transistor 3,4 also provides high intrinsic output impedance to prevent RF signal leakage to the power supply. The resistor fb(1,2) is used not only to meet the aspired input impedance matching criterion, but also to reduce the power consumption in line to the elimination of additional biasing circuitry for transistors 1 -4 in the context of self-biased principle. By adapting the complementary current-reuse technique, the DC current from the switching stage is fed into transistor 1,2 instead of being routed into silicon ground as in a typical folded topology apparently in a quest to boost the gain without additional power consumption. As a result, the NMOS transistor 1,2 contributes more transconductance than PMOS transistor 3,4 due to an increased current flow through the transistor 1,2 ; thus the aspect ratio of transistors 1,2 and 3,4 along with feedback resistor fb (1,2) is optimized diligently according to (1) and (3).
As mentioned before, a large aspect ratio of RF input transistors contributes to a respective large gate-source parasitic capacitance at the input stage of the conventional RFCR topology and thus adversely affects the input matching and concurrently reduces the operating bandwidth. Hence, an inductor (1,2) is placed in series with the gate of the transconductance stage transistors while the input capacitor in (1,2) is placed in parallel to the transconductance stage to extend the input bandwidth of the frequency response in achieving a good matching over the operating frequency range. The capacitor in (1,2) and inductor (1,2) integrated with the total gate-source capacitance, gst of input transistors, form a third-order LC ladder low-pass filter. In this approach, the inductor (1,2) coupled with the capacitor in (1,2) to eliminate the effect of gst and to resonate out the reactive component of in at the desired frequency. Through this technique, the constraints of gate-source parasitic capacitance as described in (5) are relaxed. In preference the transconductance can be increased to achieve higher gain and low noise performance simultaneously by increasing the size of RF input transistor while retaining the operating bandwidth as there is an additional degree of freedom in increasing gst . Figure 3 depicts the corresponding half circuit small signal representation of the proposed wideband mixer which   is illustrated in Figure 2. The capacitors (1,2) and (1,2) represent the parasitic capacitances at nodes (1,2) and (1,2) , respectively. To simplify the analysis, the DC blocking capacitor ac (1,2) between the transconductance and switching stage is neglected since the impedance in effect of ac (1,2) is relatively small at the operating frequency range. The input impedance in and the input return loss 11 of the proposed architecture can be derived and expressed as in (12) and (13), respectively, where gst = gs1 + gs3 is total gate-source capacitance of the input transistors and denotes the impedance looking into the resistor 1 . Assume that the -match LC network is symmetrical for perfect input impedance matching by equating the capacitor in (1,2) to capacitor gst and in = which is typically 50 Ω. From (12), a good input matching for this circuit is obtained at frequencies As can be seen from (14), the two frequencies, 1 and 2 , are adjusted to be located at DC and high frequency, respectively.

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The Scientific World Journal The frequency 2 is optimized to be in the vicinity of frequency 1 in order to maintain an input reflection of 11 below −10 dB across the entire operating frequency confirming a good input matching response inherited. At node (1,2) of Figure 2, the resistive load, (1,2) , is designed to be relatively large compared to the impedance looking into the switching transistors; thus the RF signal is driven to subsequent stage through the AC coupling capacitor, ac (1,2) . In the worst case scenario, a small amount of RF signal leakage through the load resistor (1,2) can still be shorted out to ground through the load capacitor (1,2) instead of being routed to the IF output. Since the impedance looking into transistor 5,6 at node (1,2) is also large, the RF signal is forced to enter the switching quad.
A PMOS based local oscillator (LO) switching stage is adopted in place of conventional NMOS transistor as PMOS transistor inherits an intrinsic characteristic of low flicker noise performance and less LO power sensitivity compared to NMOS transistor [23]. In reference to (6), large switching transistors with low LO current are applied to minimize the flicker noise in the direct mechanism. In contrast, a large switching transistor indirectly translates flicker noise to the mixer output due to the presence of large tail capacitance at the switches as described in the previous section. The inherited parasitic capacitance also limits the bandwidth, hence promoting the exploration of inductive peaking technique as illustrated in Figure 2.
The inductor (1,2) is placed at the tail of the switches to enhance the bandwidth through a peaking at high frequency without consuming additional power and voltage headroom. The aspect ratio of transistors 5,6 and switching transistors are selected appropriately to form two suitable parasitic capacitors (1,2) and (1,2) at nodes (1,2) and (1,2) , respectively. These capacitors form a virtual -network along with inductor (1,2) , relaxing the requirement of integrating additional capacitors which degrade the CG and NF. From the perspective of transient analysis, the current charges the two capacitors ( , ) separately through the inductor (1,2) , at different point of time, resulting in the charging time to be reduced leading to an enhancement in bandwidth. In further analyzing the operation of the peaking inductor (1,2) , in reference to the frequency response, the LO transistor is modelled as an ON-OFF switch [28] while the resistor sw represents the resistance at the source terminal of switching transistor as illustrated in Figure 3. Based on this approximated model, the overall conversion gain of the mixer is computed by the following expression: where RF = RF is the RF input frequency and IF = IF is the IF output frequency.  (16) and (17), respectively, while the transfer function of [ IF ( IF )/ RF ( RF )] can be derived adapting Fourier series analysis by approximating the LO signal as an ideal square wave, which is given by (18) V gs ( RF ) Since the impedances looking through the transistors 1,3 at node 1 and transistor 5 at node 1 are relatively large, hence the intrinsic resistances = 1 3 and 5 in Figure 3 are neglected. With the integration of the peaking inductor, the frequency response of the RF signal in (9) is computed as in (19). The transfer function in (19) can be rewritten in expressing a single real pole and two complex poles as follows: . (20) Comparing (19) and (20), the pole factor , the real pole frequency 0 , and the complex pole frequencies 1 can be expressed as follows: The Scientific World Journal 7 Notably, the bandwidth extension is heavily dependent on the value of parasitic capacitances (1,2) and (1,2) , inductor (1,2) , and resistors sw and fb (1,2) . The real pole results in gain and bandwidth reduction at the frequency higher than its value, whereas the complex poles can be adjusted to provide a peaking in frequency response which compensates this adverse effect. Since the real pole is the dominant parameter in achieving a high bandwidth and gain, it should be peaked at the highest frequency as possible, while the location of complex poles are adjusted accordingly to compensate for the gain drop at high frequencies by introducing a peaking and further extending the bandwidth. However, bandwidth enhancement using this approach introduces in-band ripples. Increasing the potentially enhances the gain at the peaking; however increasing excessively would result in bandwidth reduction. Similarly increasing 1 shifts the peaking to higher frequencies; however when 1 is increased excessively, it results in the reduction of gain in reference to (21) and (22). Therefore, 1 and are optimized appropriately to obtain relatively flat and high gain response over the wide bandwidth of operation.
The mixing point of RF and LO signals is located at the node (1,2) . The switching quad 7 -10 is biased in the vicinity of the threshold voltage at low bias current, thus reducing the DC offset and flicker noise while resulting in a substantial increase in switching efficiency. The low bias current allows the integration of larger load resistance, thus increasing the CG of the mixer and relaxing the constraint of voltage headroom consumption. Load capacitor (1,2) couples with the load resistor (1,2) presenting a low-pass filter at the IF output with the output real pole equal to IF = 1/ based on (17). This integration suppresses the feed components of sin( LO ) , sin( RF ) , and other unwanted harmonics including the higher-order mixing spurs such as sin( LO ± RF ) , where and are integers. Ultimately, the overall conversion gain of the presented wideband mixer at the desired output spectrum is given by 1.08 mm 1.00 mm

RC-Extracted Simulation Results
The proposed wideband mixer of Figure 2 has been designed and simulated using 0.13 m CMOS standard process for regulated CR applications. The layout parasitic extraction (LPE) is executed and validated under Cadence Spectre-RF and Mentor Calibre platform. In an interest of perfect matching and the minimization of mismatch parasitic coupling effect, the components and metal paths in the designed mixer circuit were placed as symmetrical as possible. The physical layout of the circuit including the RF ESD pads is illustrated in Figure 4 with a total chip area consumption of 1.08 × 1.00 mm 2 . The postlayout simulation results were carried out with a total power consumption of 3.5 mW at respective voltage headroom of 1 V. The RF input of the wideband mixer is matched to 50 Ω termination and the respective simulated input return loss, 11 , is illustrated in Figure 5. The 11 of the optimized RFCR wideband mixer is achieved well below −12 dB across the operating frequency ranging from 50 MHz to 10 GHz. Figure 6 shows the simulated NF versus RF frequency from 50 MHz to 10 GHz with a fixed IF output at 10 MHz while the LO power is set to be 0 dBm. The simulated minimum and maximum NF of the wideband mixer are 10.8 dB and 12.8 dB, respectively. This wideband mixer exhibits a flat NF with a variation of ±1 dB across the entire frequency range. Figure 7 shows the simulated CG versus RF frequency in a comparison plot with the presence of the peaking inductor and absence of the peaking inductor. At low frequency, the CG is observed to be around 16 dB. However, at high frequency range, the CG is achieved to about 8 dB without the peaking inductor in place and about 14 dB with the integration of peaking inductor, resulting in 6 dB of gain improvement. This plot reveals and confirms that the peaking inductor in RFCR mixer had improved the CG at high frequency range. The proposed wideband mixer achieves a high gain with a flatness variation of ±1.4 dB where 8 The Scientific World Journal  the maximum CG of 16.3 dB is observed at 500 MHz and a minimum of CG of 13.5 dB is observed at 5.5 GHz.
In observing the linearity response, the center frequency of 5 GHz from the operating bandwidth is selected. With an LO power of 0 dBm at LO = RF + 10 MHz, the P1dB is simulated to be −15.8 dBm. Applying two-tone test with 1 MHz frequency offset, the simulated IIP3 is −6.3 dBm as shown in Figure 8. Figure 9 depicts the overall performance of the simulated P1dB and IIP3 against RF frequency of the mixer over the range of 50 MHz to 10 GHz. The mixer   The overall performance of the proposed mixer can be weighed comparatively with other reported works using a figure-of-merits (FOM). Generally, the mixer performance was compared in terms of CG, NF, linearity (IIP3 or input P1dB), and power consumption [29,30]. However, a trade-off The Scientific World Journal 9  exits between power dissipation and bandwidth in wideband mixer design. Hence, it is essential to include the operating bandwidth parameter into FOM calculation for the fair comparison with the reported works [31]. As a result, a modified FOM is introduced for wideband mixer, which is given as FOM = 10 log ( 10 CG max /20 ⋅ 10 (IIP3 max −10)/20 10 NF min /10 ⋅ ⋅ − √ ) , where and represent lower cut-off frequency and upper cut-off frequency, respectively. is the power consumption in Watts. CG max is the maximum conversion gain, IIP3 max is the maximum input third-order intercept point, and NF min is the minimum noise figure. The simulated results of the proposed architecture along with other reported results of the recent works are tabulated in Table 1. The proposed mixer achieves 26.14 dB which is the highest FOM compared to other mixers.

Conclusion
In this work, a new wideband mixer for CR receiver has been successfully designed and simulated in 0.13 m CMOS process. A -match LC network is embedded at the input of RFCR architecture to simultaneously enhance the input impedance matching and NF while encapsulating an operating bandwidth as large as 10 GHz. The RFCR adaptation enables the proposed mixer to achieve high gain by summing up the transconductance of NMOS and PMOS in the transconductance stage. The peaking inductor achieves a flat CG response by compensating the gain degradation at high frequencies, while extending the bandwidth. Additionally, the complementary current-reuse technique is implemented at the output stage to further boost the CG without dissipating additional power. The proposed wideband mixer operates from 50 MHz to 10 GHz with an RF input return loss better than −12 dB, a high CG of 14.9 ± 1.4 dB, a flat NF of 11.8 ± 1 dB, an P1dB of −15.3 ± 1.7 dBm, and an IIP3 of −6.3 ± 1.8 dBm. This mixer operates at a low voltage headroom of 1.0 V while consuming only 3.5 mW of power. This characteristic of proposed wideband mixer serves to be a compatible architecture to meet the future growing demands in CR application.