2.4 GHz CMOS Power Amplifier with Mode-Locking Structure to Enhance Gain

We propose a mode-locking method optimized for the cascode structure of an RF CMOS power amplifier. To maximize the advantage of the typical mode-locking method in the cascode structure, the input of the cross-coupled transistor is modified from that of a typical mode-locking structure. To prove the feasibility of the proposed structure, we designed a 2.4 GHz CMOS power amplifier with a 0.18 μm RFCMOS process for polar transmitter applications. The measured power added efficiency is 34.9%, while the saturated output power is 23.32 dBm. The designed chip size is 1.4 × 0.6 mm2.

Regarding the issue of low gain of CMOS power amplifiers, the mode-locking technique is one of the most successful solutions [32]. Accordingly, the concepts of the modelocking technique have been vigorously adapted in previous work. In this study, we also focused on the improvement of gain of the CMOS power amplifier. While the modelocking technique was adapted to a common-source amplifier in previous work, here, we propose a method for the modelocking technique to be adapted to the cascode structure. The cascode structure is essential to overcome the low breakdown voltage problems of CMOS devices. To prove the feasibility of the proposed structure, we designed a 2.4 GHz CMOS power amplifier using the proposed structure. Figure 1 provides examples of CMOS power amplifiers using typical mode-locking technique. The structure shown in Figure 1(a) is the primary structure of the amplifier using the mode-locking technique. In Figure 1, for the sake of simplicity, the switch to control the oscillation is omitted. As shown in Figure 1(a), the differential structure is essential to adapt the mode-locking technique. Moreover, the differential structure provides an advantage for generating a virtual ground node and hence for minimizing the gainreduction problems induced by the bond wires. As can be seen in Figure 1(a), the cross-coupled transistors ( CC ) were used to construct the mode-locking structure. Although the input signal enters through the gate of the common-source transistors ( CS ), the CC also acts as the amplifier stage.  Accordingly, the mode-locking structure can elevate the gain as compared to a typical common-source amplifier.

Typical Mode-Locking Technique
Recently, as the CMOS technology has been scaled down, the cascode structure has become the most commonly used one for CMOS power amplifiers, to moderate breakdown voltage problems. Figure 1(b) shows the cascode structure adapted for the mode-locking technique. In Figure 1, the drain voltage of is used as the input of CC . In a previous work [33], to moderate the excessive voltage swing of input of CC , the series capacitor was inserted between the drain of and the gate of CC . However, the conceptual operation principle presented in Figure 1(b) is identical to that in Figure 1

Proposed Mode-Locking Method with the Cascode Structure
Although the feasibility of the mode-locking technique merged into the cascode structure was successfully proven in previous work [33], the time delay between input of CS and input of CC of the structure shown in Figure 1(b) may obstruct maximization of the advantages of the mode-locking technique. To investigate the time delay problems indicated in Figure 1(b), we simplified the structure shown there with on-resistances as shown in Figure 2. In Figure 2, CS , , and CC denote the on-resistances of CS , , and CC , respectively. If the time delay between IN+ (or IN− ) and + (or − ) is CS , the time delay, CC , between IN+ (or IN− ) and OUT+ (or OUT− ) can then be calculated as follows: Here, OUT is the equivalent capacitance at OUT+ or OUT− . In (1), we ignored effects induced by the load impedances connected to OUT+ and OUT− . If the effects of load impedances are considered, the time constant, , increases. Additionally, we assumed that the OUT is fully discharged or charged after five time constants. Figure 3 provides the ideal voltage waveforms of the device in Figure 2.
Given that CC should perform the identical function of the CS in general, the value of CC needs to be minimized to maximize the advantage of the mode-locking technique. Undesired, excessive time delay, CC , may cause the undesired effects, even harmonics. Additionally, the excessive value of CC may prevent switching conditions that would be ideal for high efficiency of the switching-mode power amplifier.
Here, we proposed a modified, mode-locking technique for the cascode structure to minimize the time delay, CC of (1). In the proposed structure (Figure 4), the input of the CC is connected to the drain of CS . The time delay between input of CS and input of CC is reduced to CS .
Compared to the typical structure shown in Figure 1(b), the time delay is reduced with amount of 5 of (1). Although the time delay, CS , still exists, the undesired effects induced by the excessive time delay may be minimized with the proposed structure.

Results of 2.4 GHz CMOS Power Amplifier with Proposed Mode-Locking Technique
To verify the feasibility of the proposed structure, we designed a 2.4 GHz power amplifier using 0.18 m RF CMOS technology with one poly, and six metal layers. Top metal layer was composed of aluminum 2.3 m thick. The power amplifier is designed as switching mode amplifier for polar transmitter, or sensor network, applications. All of the input and output matching networks are fully integrated, including test PADs and transformers. Important design parameters, including the transistor size, are provided in Figure 5. The input and output transformer were designed using an electromagnetic simulator. To minimize the loss induced by the resistance of the output transformer, the width of the output transformer is wider than that of the input transformer. The supply voltage of the amplifier enters through the center tap of the primary part of the output transformer. To minimize the gain reduction problems induced by the bond wires, a differential structure was adapted. All of the resistors for the bias are 2 kΩ. Figure 6   shows the chip photograph of the newly designed power amplifier. The chip size is 1.4 × 0.6 mm 2 . Figure 7 shows the measured output power and power added efficiency (PAE), according to the operating frequency, with a fixed supply voltage ( DD ) of 3.3 V. As provided in Figure 7, the output power and PAE at 2.4 GHz were 23.32 dBm and 34.9%, respectively. Figure 8 shows the PAE versus the output power according to DD ranging from 0.5 V to 3.3 V.

Conclusions
In this study, we proposed a mode-locking technique for a cascode CMOS power amplifier. Using the drain voltage of    a common-source transistor as the input of the cross-coupled transistor, the time delay between the common-source and cross-coupled transistors was minimized to maximize the advantage of the mode-locking technique. To prove the feasibility of the proposed technique, we designed a 2.4 GHz CMOS power amplifier with a 0.18 m RFCMOS process for polar transmitter applications. The measured power added efficiency is 34.9%, while the saturated output power is 23.32 dBm. The size of the newly designed chip was 1.4 × 0.6 mm 2 .