We propose a mode-locking method optimized for the cascode structure of an RF CMOS power amplifier. To maximize the advantage of the typical mode-locking method in the cascode structure, the input of the cross-coupled transistor is modified from that of a typical mode-locking structure. To prove the feasibility of the proposed structure, we designed a 2.4 GHz CMOS power amplifier with a 0.18 μm RFCMOS process for polar transmitter applications. The measured power added efficiency is 34.9%, while the saturated output power is 23.32 dBm. The designed chip size is 1.4×0.6 mm2.
1. Introduction
Currently, CMOS (complementary metal-oxide semiconductor) devices are the most popular for RFIC (radio frequency integrated circuit) design due to their low cost [1–15]. In particular, CMOS RFICs can more easily be integrated with other analog or digital ICs than with GaAS (gallium arsenide) RFICs [16–21]. Although GaAs devices are regarded as more suitable than CMOS ones, there have been vigorous studies about how to reduce unit costs of CMOS power amplifiers [22–27]. If a successful CMOS power amplifier is developed, the potential for creating a fully integrated, front-end IC should increase. Nevertheless, compared to those using GaAs, CMOS power amplifiers still have drawbacks, including (1) low breakdown voltage, (2) lossy substrate, (3) low linearity, and (4) low gain. The issues related to the breakdown voltage and substrate loss have been successfully investigated and resolved using the distributed active transformer (DAT) proposed by Aoki et al. [22]. Additionally, techniques to solve the low-linearity problem of CMOS power amplifiers have also been intensively studied, and some successful techniques have been introduced [28–31].
Regarding the issue of low gain of CMOS power amplifiers, the mode-locking technique is one of the most successful solutions [32]. Accordingly, the concepts of the mode-locking technique have been vigorously adapted in previous work. In this study, we also focused on the improvement of gain of the CMOS power amplifier. While the mode-locking technique was adapted to a common-source amplifier in previous work, here, we propose a method for the mode-locking technique to be adapted to the cascode structure. The cascode structure is essential to overcome the low breakdown voltage problems of CMOS devices. To prove the feasibility of the proposed structure, we designed a 2.4 GHz CMOS power amplifier using the proposed structure.
2. Typical Mode-Locking Technique
Figure 1 provides examples of CMOS power amplifiers using typical mode-locking technique. The structure shown in Figure 1(a) is the primary structure of the amplifier using the mode-locking technique. In Figure 1, for the sake of simplicity, the switch to control the oscillation is omitted. As shown in Figure 1(a), the differential structure is essential to adapt the mode-locking technique. Moreover, the differential structure provides an advantage for generating a virtual ground node and hence for minimizing the gain-reduction problems induced by the bond wires. As can be seen in Figure 1(a), the cross-coupled transistors (MCC) were used to construct the mode-locking structure. Although the input signal enters through the gate of the common-source transistors (MCS), the MCC also acts as the amplifier stage. Accordingly, the mode-locking structure can elevate the gain as compared to a typical common-source amplifier.
CMOS power amplifiers using mode-locking technique: (a) typical and (b) modified structures.
Recently, as the CMOS technology has been scaled down, the cascode structure has become the most commonly used one for CMOS power amplifiers, to moderate breakdown voltage problems. Figure 1(b) shows the cascode structure adapted for the mode-locking technique. In Figure 1, the drain voltage of MCG is used as the input of MCC. In a previous work [33], to moderate the excessive voltage swing of input of MCC, the series capacitor was inserted between the drain of MCG and the gate of MCC. However, the conceptual operation principle presented in Figure 1(b) is identical to that in Figure 1(a).
3. Proposed Mode-Locking Method with the Cascode Structure
Although the feasibility of the mode-locking technique merged into the cascode structure was successfully proven in previous work [33], the time delay between input of MCS and input of MCC of the structure shown in Figure 1(b) may obstruct maximization of the advantages of the mode-locking technique. To investigate the time delay problems indicated in Figure 1(b), we simplified the structure shown there with on-resistances as shown in Figure 2. In Figure 2, RCS, RCG, and RCC denote the on-resistances of MCS, MCG, and MCC, respectively. If the time delay between VIN+ (or VIN-) and VM+ (or VM-) is tCS, the time delay, tCC, between VIN+ (or VIN-) and VOUT+ (or VOUT-) can then be calculated as follows:
(1)tCC≈tCS+5τ(τ=RCGCOUT).
Simple equivalent circuit of cascode structure with mode-locking method.
Here, COUT is the equivalent capacitance at VOUT+ or VOUT-. In (1), we ignored effects induced by the load impedances connected to VOUT+ and VOUT-. If the effects of load impedances are considered, the time constant, τ, increases. Additionally, we assumed that the COUT is fully discharged or charged after five time constants. Figure 3 provides the ideal voltage waveforms of the device in Figure 2.
Ideal voltage waveforms of the cascode structure with mode-locking method.
Given that MCC should perform the identical function of the MCS in general, the value of tCC needs to be minimized to maximize the advantage of the mode-locking technique. Undesired, excessive time delay, tCC, may cause the undesired effects, even harmonics. Additionally, the excessive value of tCC may prevent switching conditions that would be ideal for high efficiency of the switching-mode power amplifier.
Here, we proposed a modified, mode-locking technique for the cascode structure to minimize the time delay, tCC of (1). In the proposed structure (Figure 4), the input of the MCC is connected to the drain of MCS. The time delay between input of MCS and input of MCC is reduced to tCS.
Proposed mode-locking technique for the cascode structure.
Compared to the typical structure shown in Figure 1(b), the time delay is reduced with amount of 5τ of (1). Although the time delay, tCS, still exists, the undesired effects induced by the excessive time delay may be minimized with the proposed structure.
4. Experimental Results: Design and Measured Results of 2.4 GHz CMOS Power Amplifier with Proposed Mode-Locking Technique
To verify the feasibility of the proposed structure, we designed a 2.4 GHz power amplifier using 0.18 μm RF CMOS technology with one poly, and six metal layers. Top metal layer was composed of aluminum 2.3 μm thick. The power amplifier is designed as switching mode amplifier for polar transmitter, or sensor network, applications. All of the input and output matching networks are fully integrated, including test PADs and transformers. Important design parameters, including the transistor size, are provided in Figure 5. The input and output transformer were designed using an electromagnetic simulator. To minimize the loss induced by the resistance of the output transformer, the width of the output transformer is wider than that of the input transformer. The supply voltage of the amplifier enters through the center tap of the primary part of the output transformer. To minimize the gain reduction problems induced by the bond wires, a differential structure was adapted. All of the resistors for the bias are 2 kΩ. Figure 6 shows the chip photograph of the newly designed power amplifier. The chip size is 1.4×0.6 mm2.
Schematic of the proposed power amplifier.
Photograph of the newly designed power amplifier.
Figure 7 shows the measured output power and power added efficiency (PAE), according to the operating frequency, with a fixed supply voltage (VDD) of 3.3 V. As provided in Figure 7, the output power and PAE at 2.4 GHz were 23.32 dBm and 34.9%, respectively. Figure 8 shows the PAE versus the output power according to VDD ranging from 0.5 V to 3.3 V.
Measured output power and efficiency according to operating frequency.
Measured output power and efficiency according to supply voltage.
5. Conclusions
In this study, we proposed a mode-locking technique for a cascode CMOS power amplifier. Using the drain voltage of a common-source transistor as the input of the cross-coupled transistor, the time delay between the common-source and cross-coupled transistors was minimized to maximize the advantage of the mode-locking technique. To prove the feasibility of the proposed technique, we designed a 2.4 GHz CMOS power amplifier with a 0.18 μm RFCMOS process for polar transmitter applications. The measured power added efficiency is 34.9%, while the saturated output power is 23.32 dBm. The size of the newly designed chip was 1.4×0.6 mm2.
Conflict of Interests
The authors declare that there is no conflict of interests regarding the publication of this paper.
Acknowledgment
This work was supported by the Basic Science Research Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Education, Science and Technology (2012-044627).
ChangJ.-N.LinY.-S.A high-performance CMOS power amplifier for 60 GHz short-range communication systems2013555115511602-s2.0-8487542425810.1002/mop.27522OhJ.KimH.KimM.-S.HanS.HamJ.SeoM.JungS.ParkC.-S.YangY.Integrated CMOS RF transmitter with a single-ended power amplifier20135512052102-s2.0-8486939636410.1002/mop.27257KongJ.JeongJ.Linearization of stacked-FET RF CMOS power amplifier using diode-integrated bias circuit2013555101110142-s2.0-8487544439010.1002/mop.27472OhJ.KuB.HongS.A 77-GHz CMOS power amplifier with a parallel power combiner based on transmission-line transformer2013617266226692-s2.0-8487778728210.1109/TMTT.2013.2261087YousefK.JiaH.PokharelR.AllamA.RagabM.KanayaH.YoshidaK.CMOS ultra-wideband low noise amplifier design2013201362-s2.0-8487799503310.1155/2013/328406328406KooB.NaY.HongS.Integrated bias circuits of RF CMOS cascode power amplifier for linearity enhancement20126023403512-s2.0-8485702029110.1109/TMTT.2011.2177857VoicuM.PepeD.ZitoD.Performance and trends in millimetre-wave CMOS oscillators for emerging wireless applications2013201362-s2.0-8487657652710.1155/2013/312618312618LeeS.-Y.ItoH.AmakawaS.IshiharaN.MasuK.An inductorless cascaded phase-locked loop with pulse injection locking technique in 90 nm CMOS20132013112-s2.0-8487551149010.1155/2013/584341584341ParkC.HanJ.KimH.HongS.A 1.8-GHz CMOS power amplifier using a dual-primary transformer with improved efficiency in the low power region20085647827922-s2.0-4194908966610.1109/TMTT.2008.918152ParkC.KimY.KimH.HongS.A 1.9-GHz triple-mode class-E power amplifier for a polar transmitter20071721481502-s2.0-3384770459510.1109/LMWC.2006.890345TangsriratW.Gm-realization of controlled-gain current follower transconductance amplifier20132013810.1155/2013/201565201565JalilJ.ReazM. B. I.BhuiyanM. A. S.RahmanL. F.ChangT. G.Designing a ring-VCO for RFID transponders in 0.18 μm CMOS process20142014610.1155/2014/580385580385TangF.BermakA.AmiraA.BenamarM. A.HeD.ZhaoX.Two-step single slope/SAR ADC with error correction for CMOS image sensor20142014610.1155/2014/861278861278AljarajrehH.ReazM. B. I.AminM. S.HusainH.An active inductor based low noise amplifier for RF receive201319549522-s2.0-8487796911810.5755/j01.eee.19.5.2158Guerra-GomezI.Tlelo-CuautleE.Sizing analog integrated circuits by current-branches-bias assignments with heuristics201319108186LeeY.HongS.A dual-power-mode output matching network for digitally modulated CMOS power amplifier2013614157015792-s2.0-8487603016810.1109/TMTT.2013.2246525KimJ.KimD.ChoY.KangD.ParkB.KimB.Envelope-tracking two-stage power amplifier with dual-mode supply modulator for LTE applications20136115435522-s2.0-8487291491610.1109/TMTT.2012.2225532KaoK. Y.HsuY. C.ChenK. W.LinK. Y.Phase-delay cold-FET pre-distortion linearizer for millimeter-wave CMOS power amplifiers2013611245054519ArefA. F.NegraR.A fully integrated adaptive multiband multimode switching-mode CMOS power amplifier2012608254925612-s2.0-8486471846410.1109/TMTT.2012.2201746SonK. Y.KooB.HongS.A CMOS power amplifier with a built-in RF predistorter for handset applications2012608257125802-s2.0-8486465605910.1109/TMTT.2012.2198230AlouiS.LeiteB.DemirelN.PlanaR.BelotD.KerherveE.High-gain and linear 60-GHz power amplifier with a thin digital 65-nm CMOS technology2013616242524372-s2.0-8487878555110.1109/TMTT.2013.2258169AokiI.KeeS. D.RutledgeD. B.HajimiriA.Distributed active transformer—a new power-combining and impedance-transformation technique2002501316331ParkJ.LeeC.ParkC.A brief review: stage-convertible power amplifier using differential line inductor201234189194JooT.LeeH.ShimS.HongS.CMOS RF power amplifier for UHF stationary RFID reader20102021061082-s2.0-7674915840210.1109/LMWC.2009.2038552WilkS. J.LepkowskiW.ThorntonT. J.32 dBm power amplifier on 45 nm SOI CMOS20132331611632-s2.0-8487499938010.1109/LMWC.2013.2245413ChenJ. H.HelmiS. R.JouA. Y. S.MohammadiS.A wideband power amplifier in 45 nm CMOS SOI technology for X-Band applications20132311587589ChenJ.-H.HelmiS. R.PajouhiH.SimY.MohammadiS.A wideband RF power amplifier in 45-nm CMOS SOI technology with substrate transferred to AlN20126012408940962-s2.0-8487173923610.1109/TMTT.2012.2223229ChungH.-Y.KuoC.-W.ChiouH.-K.A full X-band power amplifier with an integrated guanella-type transformer and a predistortion linearizer in 0.18-μM CMOS2013559222922322-s2.0-8487961957410.1002/mop.27804KwonK.NamI.A linearization technique for a transconductor using vertical bipolar junction transistors in a CMOS process20136111952032-s2.0-8487284009710.1109/TMTT.2012.2226602FrançoisB.ReynaertP.A fully integrated watt-level linear 900-MHz CMOS RF power amplifier for LTE-applications2012606187818852-s2.0-8486182046010.1109/TMTT.2012.2189411ChowdhuryD.HullC. D.DeganiO. B.WangY.NiknejadA. M.A fully integrated dual-mode highly linear 2.4 GHz CMOS power amplifier for 4G WiMax applications20094412339334022-s2.0-7294908889310.1109/JSSC.2009.2032277TsaiK.-C.GrayP. R.A 1.9-GHz, 1-W CMOS class-E power amplifier for wireless communications19993479629702-s2.0-003336607010.1109/4.772411LeeC.ParkJ.ParkC.X-band CMOS power amplifier using mode-locking method for sensor applications2012265-66336402-s2.0-8486457800410.1080/09205071.2012.710783