Multi-Level Logic Synthesis Based on Kronecker Decision Diagrams and Boolean Ternary Decision Diagrams for Incompletely Specified Functions

This paper introduces several new families of decision diagrams for multi-output Boolean functions. The introduced families include several diagrams known from literature (BDDs, FDDs) as subsets. Due to this property, these diagrams can provide a more compact representation of functions than either of the two decision diagrams. Kronecker Decision Diagrams (KDDs) with negated edges are based on three orthogonal expansions (Shannon, Positive Davio, Negative Davio) and are created here for incompletely specified Boolean functions as well. An improved efficient algorithm for the construction of KDD is presented and applied in a mapping program to ATMEL 6000 fine-grain FPGAs. Four other new families of functional decision diagrams are also presented: Pseudo KDDs, Free KDDs, Boolean Ternary DDs, and Boolean Kronecker Ternary DDs. The last two families introduce nodes with three edges and require AND, OR and EXOR gates for circuit realization. There are two variants of each of the last two families: canonical and non-canonical. While the canonical diagrams can be used as efficient general-purpose Boolean function representations, the non-canonical variants are also applicable to incompletely specified functions and create don’t cares in the process of the creation of the diagram. They lead to even more compact circuits in logic synthesis and technology mapping.


INTRODUCTION
the AT 6000 series of FPGAs from Atmel (formerly Concurrent Logic, Inc. [9]) have been brought to market. The AT6000 FPGA series are finegrain FPGAs with a cellular architecture (local connections) and very limited routing resources. There exist also other similar chips, fabricated or in development, by Algotronix [1] (now part of Xilinx), Toshiba, Plessey, Pilkington, Motorola [22], and National Semiconductor, in addition to other companies and Universities. However, high quality logic synthesis software tools for these families are still missing.
The work presented in this paper was partially supported by NSF grant MIP-9110772.
One possible approach is to adopt BDD-based methods. However, all these methods are based on the "unate paradigm" [7]. The "unate paradigm" is the assumption that most of the practical logic functions occurring in logic design are unate or nearly unate. The meaning of unate and nearly unate for logic minimization purposes is that the circuit realization of a (nearly) unate function with AND and OR gates is not greater in terms of the number of gates than a circuit using the AND and EXOR gates. On the other hand the meaning of linear or nearly linear for logic minimization purposes is that the circuit realization of a (nearly) linear function with AND and EXOR gates is not greater in terms of the number of gates than a circuit using the AND and OR gates (it is usually smaller). Although the unate paradigm holds for many control logic circuits, it is not valid for many data path circuits. Also the theoretical studies in EXOR logic by Sasao [30, 31 and others [27] confirm the usefulness of EXOR gates. Arithmetic functions like counters, adders, multipliers, signal processing functions and error correcting logic that belong to the class of (nearly) linear functions 16] cannot be efficiently minimized for circuit speed and area using BDDs only. To address these deficiencies, the concepts of: Adaptive logic trees [14] and Functional Decision Diagrams (FDDs) [33,18] have been developed and applied to FPGA mapping. The adaptive logic trees were introduced for multi-level representation of switching functions based on Reed-Muller [10] canonical expansion. The Functional Decision Diagrams were introduced for completely specified functions as a generalization of adaptive logic tree structures into directed acyclic graph (DAG) structures.
Free, multiple-valued decision diagrams for incompletely specified functions were first introduced in [23]. These diagrams, called orthogonal, include binary Kronecker Functional Decision Diagrams and other diagrams presented here. The same paper also presented an efficient algorithm for the construction of diagrams, in which variable order and expansion type selections were based on self-learning. A comprehensive presentation of various tree, DAG and flattened structures for AND/ EXOR networks was given in [23,24,25]. These papers introduced for the first time several new decision diagrams and synthesis algorithms, both for binary and multiple-valued logic.
Some of these concepts were next implemented in software tools: Permuted (free) Reed-Muller trees [36] use Positive and Negative Davio expansions and were applied for technology mapping to AT6000 for completely specified functions. Kronecker Functional Decision Diagrams (KEDDs) introduced in [29,32,12] were used for AT6000, Actel and Xilinx technology mapping for both completely and incompletely specified functions. Pseudo KDDs and Free KDDs were introduced in [15] and were used for ATMEL 6000 technology mapping for completely specified functions.
While the number of families of canonical and noncanonical diagrams introduced in the above papers is very large, and most of them have not been implemented yet, we continue here our more detailed study of some of these families. This paper has two main contributions: an efficient algorithm for generating KDDs, in sections 3 and 4, and the introduction of several efficient new families of decision diagrams, in sections 2, 6, and 7. Section 2 defines the Kronecker Decision Diagrams (KDDs), the Pseudo Kronecker Decision Diagrams (PKDDs), the Free Kronecker Decision Diagrams (FKDDs), and some other types of diagrams. The basic ideas of the algorithm to create KDDs for incompletely specified multi-output functions are presented in section 3. This algorithm uses the new concept of constrained don't cares, also explained in section 3. Section 4 discusses one more important aspect of this algorithm: redundancy conditions for the selection of expansion variables. Analysis of benchmark results is given in section 5. Compared to other algorithms for the generation of decision diagrams (DD), our algorithm proves that particularly compact KDD diagrams can be obtained for incompletely specified functions. Encouraged by this result, which points to the usefulness of don't cares and constrained don't cares, we develop in section 6 new families of decision diagrams which take additional advantage of these don't cares. We create families of non-canonical variants that are applicable to both incompletely specified functions and completely specified functions. The algorithms to construct such diagrams create don't cares and constrained don't cares in the process of creating the diagrams. The first class of diagrams are called Boolean Ternary DDs (BTDDs). The word "Boolean" is to denote that they are for Boolean logic, the word "Ternary" denotes that there are three outgoing edges from each node, instead of the usual two edges. The second class are called Boolean Kronecker Ternary DDs (BKTDDs). Those are diagrams which have two kinds of nodes: binary nodes as in KDDs, and ternary nodes as in BTDDs. BKTDDs are better for efficient logic optimization and technology mapping by creating diagrams with even less numbers of nodes. In section 7, we introduce certain diagrams which are canonical counterparts of BTDDs and BKTDDs and are used for efficient general-purpose representation and manipulation of switching functions.
Nodes in KDD diagrams correspond to two-input multiplexers and AND/EXOR gates. Nodes in BTDDs are combinations of multiplexers and AND/EXOR gates with two-input OR, EXOR and inhibition (A B) gates. Therefore, all these nodes can be readily realized with cells of the AT6000 series, Motorola's MPA10XX, or other fine-grain FPGAs. This makes the new diagrams a useful tool for fine-grain FPGA synthesis.

DEFINITIONS OF VARIOUS TYPES OF KRONECKER FUNCTIONAL DECISION DIAGRAMS
In this section, the representation of switching functions based on various Kronecker Functional Decision Diagrams will be presented. The definitions of decision diagrams are essentially due to Bryant [8] and will be reviewed in the following. All decision diagrams will be introduced systematically. Because many different names are used in papers, we will refer to the names assigned by the original creators of the diagrams, or to names that are already used by more than one author. Some names used here are the result of discussions at the First International Workshop of Applications of the Reed-Muller Expansion in Circuit Design, Hamburg, September 1993 [27]. Definition 1: A decision diagram is a rooted, directed acyclic graph with vertex set V containing two types of vertices. A terminal vertex v has as attribute a value value(v) {0, 1 }. A non-terminal vertex v has as attributes an argument index index(v) { 1 n) and two successors low(v), high(v) V.
It is possible to set restrictions on the decision diagrams based on the order and the number of times the variables are encountered. The first of these classifies the DDs according to the number of times the variables are encountered.
Definition 5: A free decision diagram is a decision diagram such that every variable occurs at most once in any path from the root to the terminal vertices. A repeated decision diagram is one in which a variable x occurs more than once in a path from the root to the terminal vertices.
Letter F will stand for free in various DDs. A different restriction is based on the order in which the variables are encountered.
Definition 6: An ordered decision diagram is a decision diagram such that for any non Definition 7: An ordered BDD is called an Ordered Binary Decision Diagram (OBDD). An ordered KFDD is called an Ordered Kronecker Functional Decision Diagram (OKFDD).
Furthermore, an ordered decision diagram can be reduced. This reduction, as given by Bryant, is obtained by removing isomorphic subgraphs and redundant vertices.  [5,6]. Shared KFDDs (SKFDD) can be defined for multi-output switching functions.

Definition 11: A Kronecker Decision Diagram (KDD) is a Shared Reduced Ordered Homogeneous Non-repeated Kronecker Decision Diagram (SROHNKFDD).
This decision diagram has been also called SROKFDD, Shared Reduced Ordered Kronecker Decision Diagram [32].
Having thus defined syntactically several families of decision diagrams, we will now relate them to Boolean functions. It is known [10,25] that there exist three single-variable decompositions over Galois Field (2): Let x be an input variable of function f. One important property of these three expansions is that the functions fx, and fg; obtained by applying any of the three expansions for x i, will be independent of the variable x i. The circuit realization of Equation (1) is given by a multiplexer gate (Fig. 1c), while Equations (2) and (3) describe an AND-EXOR gate structure, shown in  18]. The FDD is created from an order free adaptive logic tree by using reduction operations. (The concept of FDD has also been expanded to Negative Davio nodes). Ifall three expansions are applied to all variables, the Kronecker Reed-Muller tree 10, 24, 25] is obtained, and next reduced with standard DD reductions to a KDD.
There are two interesting binary families of KFDDs that include KDDs as a special case: Pseudo-KDDs, and Free KDDs.
This decision diagram is obtained by recursively applying expansions (1), (2) and (3), and preserving the same order of variables in all branches of the diagram. In addition, for any variable (in an ordered DD a variable corresponds to a level of the diagram) any combination of expansion types can be applied to the nodes on this level (this will be defined as a non-homogeneous DD).
This decision diagram is obtained by recursively applying expansions (1), (2) and (3) and allowing no fixed order of expansion variables in the diagram (allowing free order of variables in the branches). For any node of the tree, any expansion variable and expansion type can be applied, so the orders of variables can be different in various branches. (The FKDD is thus neither homogeneous nor ordered).
As we see, the FKDD is the most general kind of the above-introduced KFDDs. It includes all the FDDs 18, 33], the OKFDDs from [12,32], and the Permuted RMTs from [36] as its special cases. The PKDDs and FKDDs are reduced. Similar to BDDs with negated edges [21,5], one can define the PKDDs with negated edges and the KFDDs with negated edges. (In DDs with negated edges, additional inverters may exist on inputs and outputs of the DD nodes).
The concept of a free diagram can be applied to a decision diagram with any type of expansion nodes. Similarly, the concept of a Non-repeated DD can be applied to any type of a diagram. In free diagrams, every variable occurs at most once along a branch. In repeated-variable decision diagrams, a variable can occur more than once along a branch. Repeated variables are necessary when new types of DDs are created by combining non-isomorphic subgraphs of the initial decision diagram.
Such concepts of free diagrams and repeated-variable decision diagrams are applicable to all kinds of diagrams, hence also to BDDs. However, the concept of Kronecker  tin certain regular architectures, it is possible to combine nonisomorphic nodes. For integrity of the function, however, it would be necessary to re-introduce some of the used variables again.
The three types of generalization: free order, repetition of variables, non-homogeneity, can be used for any of the decision diagrams introduced in sections 6, and 7 since each of these decision diagrams has more than one expansion type.
From now on, it will be assumed that all the decision diagrams are reduced, shared, free and can have negated edges.

BASIC ALGORITHM FOR KDD GENERATION
The crucial part of the KDD synthesis is the determination of the expansion variable ordering and the expansion type selection. In our algorithm for the KDD generation, the expansion variable order selection and the expansion type selection are performed concurrently. However, in the variable selection process, the same expansion variable is tested with each of the three expansions. Therefore, we first discuss the expansion variable selection.
gates the conditions for a next level node to be redundant.
When calculating Davio expansions, the function g fx, f, is calculated. Let us observe that when function f has don't cares, the operations fx,f,=-l, The basic algorithm to obtain a good variable ordering is based on finding the expansion variable and the selection of the expansion type of the current level nodes such that the number of necessary next level nodes is minimal. To limit the search space for obtaining a good variable and expansion combination, we restrict the selection to being the same for a level. Thus, the three functions fx! f! and g are computed for each of the output functions f[k] of the current level and from this, the expansion that leads to the least number of next level modules for variable xj can be easily determined. Finally, the variable x and its corresponding expansion having the least number of next level modules is selected.
In order to determine the minimal number of the next-level nodes, it is necessary to find the redundant nodes on the next level. A node is redundant if it is trivial (it is either 0, 1, or equal to x;) or if it can be merged with the existing node on this level (this node can belong to any output function f[k]). Therefore, Section 4 investi-Denoting f, by U, the value of fx, fi will become U (see Fig. 2a).
The values of f; and fx, f, are, therefore, mutually constrained. This fact must be used in any synthesis program that attempts at optimal results for incompletely specified functions using Davio expansions.
Similarly, when f, and fxi ( f, are calculated for the Positive Davio Expansion; f, and fx, 0, the following cases are possible: if fx, 0, then fx, fx; 0 and if f, 1, then fx, f, 1. Denoting , by U, the value of fx, F, becomes U. This is also illustrated in Fig. 2a. Value U serves thus as a "constrained don't care". Every symbol U can take any arbitrary value in f.. But, when, as a result of logic minimization, for certain cube, C (minterm C) in f; a value of zero or one is assigned to U, this cube in function fx, f, must take the respective constrained value (U or t3"), as in one of the above two cases. This value is next used in the minimization Of fx f,. The order of minimizing the functions fx; f; and fx, f; is arbitrary, but the constraint U's must be always propa-  Fig. 2f, one gets f a. 1 3 (bcd + bcd + bcd) a (bcd + bcd + bcd).
In another variant, the function from Fig. 2e is minimized to 0, so symbols U for both minterms are assigned values of 0. Respectively, U values in both "constrained don't care" minterms in function from Fig.  2c get a value of 1. This leads to a new map for f,, from fa fa is illustrated in Fig. 2d. Applying rules in Fig. 2a to the map in Fig. 2d produces the equivalent map shown in Fig. 2e. Value U is treated in all minterms as a don't care, and the function in Fig. 2e is minimized to constant value 1. This requires treating U's for both minterms as 1, so U 0 in these minterms. These values of U 0 are now transmitted to the map for of Fig. 2c which leads A sub-function at a node will be referred to as its "input -function". Every KDD node has two such functions. Every BTDD node has three such functions. By # we denote the sharp operation [11]. We assume that the initial function is represented by the ON (true cubes) and DC (don't care cubes) sets. While creating a KDD from a root vertex, in some cases it is not necessary to realize the input functions (fx, fx, or g) of a node with extra nodes. Whether it is necessary or not, depends on the selected expansion type and the selected expansion variable. For brevity, f/and f stand for any of the three functions fx, fz, and g. We will also define: ff. x, f' x f" g' 0 r" x) ) (f" .). Analogously, f and f' stand for any of the three functions f, f-, and g '. This section investigates how to specify the don't care part of the incompletely specified Boolean function in order to select the expansion variable to obtain the minimal KDD.
There exist three basic conditions for which a nextlevel node is redundant.

Condition 1: An input function f is a trivial function:
fi 0 f,.
The above conditions can be verified by the following cube calculus operations.
Verification of Condition 1: The case that an incompletely specified input function, f, can be specified such that fi 0 can be checked by: f'i fac (13) where fac is a function that consists of only don't care terms.
The case that an input function can be specified such that f can be verified by" To An incompletely specified function, f, can be specified to be dependent on only one variable, xj, when Equations (15) and (16) are both satisfied: f xj xj (15) and f j fac (16) Here fdc consists only of the "don't-care" terms. A similar formula is used for the complement, yj. =f .fj (17) fc having no common cubes in the ON part of function fi.
f f'c f'i#f'c fac, (18) and having no common cubes in the ON part of function fj.
fj. f'c f #f'c fa,_ (19) where fa, and fac2 are certain functions of only don't care cubes and # stands for the sharp operation. If the Equations (18) and (19) are true, the don't care parts of f} andf can be specified in such a way thatfi fj. Verification of Condition 3: For the assignment of the don't care part of the incompletely specified Boolean function such that the two input functions are complements of one another, Equations (20) and (21) have to be true.
f'i fj fac (20) to verify that the ON parts of both functions have no common cubes, and f'i---)l + f--l Xi (21) in order to verify that the sum of both functions is dependent only on the chosen expansion variable. Here means the assignment of the don't care cubes of the function to true cubes. If both formulas are satisfied, the don't care part of the input functions f'i and fj can be chosen in such a way that f'i

EVALUATION OF BENCHMARK RESULTS
The results obtained by our implementation of the algorithm to obtain a KDD for several MCNC benchmark functions are given in Table 1. The column ASYL gives the number of nodes in the ASYL SROBDD, [5]. The columns dl, d2, and d3 give the number of nodes in the KDD if only Shannon, Positive Davio, or Negative Davio expansions are applied, respectively. Thus, column dl gives the number of nodes in a SROBDD with negated edges and the columns d2 and d3 give two special cases of the FDDs [25,33,36]. The sub-column neg in each of the columns dl, d2, d3 gives the respective number of negatededges. The results in the column mix are obtained by selecting the expansion at each level that leads to the least number of next level nodes.
It can be seen that out of the functions that were also minimized in [5], our program gave a better solution in 8 cases, with ASYL giving a better solution in 7 and one function being of the same cost. As it can be seen, in one case, apex7, the solution is 30 percent better than in ASYL. This kind of improvement may be very important for large functions.
Since ASYL uses SROBDDs and our program uses KDDs that are more general; the only reason that our program gives sometimes worse result is the non-optimal selection of variables and expansions for them. Table 2 gives the corresponding timing results. The time in seconds was obtained on a Sun Sparc 10/40 with memory limit set to 16 Mbytes. The results for ASYL (in  0  156  98  2  88  rd53  15  5  15  0  12  2  12  3  17  rd73  29  9  23  0  21  20  4  31  rd84  40  13  34  0  28  4  28  4  42  sao2  79  11  101  3  120  3  79  13  81   squar5   35  3  26  2  35  3  24  3  t481  20  3  20  2  14  17  4  vg2  96  2  144  0  182  2  95  94  xor5  4  3  4  0  4  0  4  3 seconds) were obtained on a Sun 4/65 with 25 Mbytes denotes the part of the function which is dependent on [5]. Next, any of the three expansions used in KDDs; Shannon, Positive Davio, and Negative Davio, is applied to fdep" This adds up to 3 .* 3 9 different possible combined expansions. The 9 possibilities come from one out of three dependency expansions and one out of three KDD-type expansions. A BTDD node corresponding to this equation has three input functions, fd, flow, and fhigh" All nine types of nodes, relJresented by a circuit with one expansion variable and three input functions, are presented in Fig. 3.
The main idea here is that in all previous decision diagrams, the fnd part of the function is carried through all levels. Here, it is proposed that this part of the function be decomposed separately.  Therefore, assuming OR gate, this expansion is unique (canonical). Function f can then be considered as an OR off.,d and a "remainder" function, calledfdep. In a similar way, for the AND expansion, the ON set of f/,d will be the smallest function that includes the ON set of function f. Therefore, this expansion is also unique for an INHI-BITION gate (a similar expansion can also be defined for an AND gate). Thus, the above two combined expansions are canonical.
However, in the case of the EXOR gate, in principle any two-input function of functions fx and f can be applied for fi,a, since each of these functions is independent of xi. Hence there are many more possible canonical dependency expansions for EXOR. Our choice of EXOR as the two-input functions shown is, in a sense, arbitrary.
It is, however, motivated by EXOR being simple and distinctly different from OR and INHIBITION, so possibly leading to searching larger space.
Example: Let function f be given as shown in Fig. 4a.
By applying OR type expansion to variable a, one obtains functionf/,d shown in Fig. 4b  an OR/MUX, the realization of Fig. 5a is transformed to that of Fig. 5b. By treating the OR/MUX gate as a node, and rotating Fig. 5b so that OR/MUX node would be on the top, one creates the first node of a BTDD. Next the expansions are applied to circuits described by the AND gates from Fig. 5b, and a complete BTDD is created. Fig. 5c presents the same function f as in Fig. 5a, realized using a standard MUX (a BDD node). This figure illustrates the advantage of the BTDD nodes over standard MUX nodes used to implement BDDs: the product cd, which is independent of variable a, is split in the MUX realization into two products, acd and a cd, which are realized by the paths through the "high" and "low" inputs of the MUX, respectively. These two paths have a common part cd which would be present at both inputs of the MUX. As it can be seen, this approach makes the MUX circuit both slower and larger. It is slower since signal cd has to go through the OR gates and the MUX (which is slower than the OR). It is larger since the OR gates on the inputs of the MUX are now necessary. The advantage of BTDD over BDD can be also illustrated on other types of functions. In general, for both incompletely specified and completely specified Boolean functions, these expansions are not unique and thus lead to non-canonical diagrams. The expansions for completely specified functions are not canonical since the OR and INHIBITION expansions produce don't care terms in the expansion process. Starting with a completely specified function f, every level of variable expansions adds more don't care terms to fnd and fdep functions of lower levels. This property, not shared by the algorithms to create DDs, is very advantageous in synthesis, since functions with many don't cares can be better minimized. However, the same property causes these diagrams to be non-canonical. Thus, they can not be used for a general-purpose Boolean function representation.
All standard concepts for DDs: free, ordered, reduced, shared, repeated variable, pseudo, can be applied to the non-canonical diagrams created as above.
BTDDs and BKTDDs can now be formally defined. find fx fx (34) fdep f # (fx fx) (35) The canonical INHIBITION type expansion for canonical BTDDs is defined as follows: find fx + f (36) fdep ( KDD diagrams allow also to represent some distinctly large functions that can not be represented by BDDs and FDDs. An example of a such function is given in [4]. An important question remains: "are there such functions among industrial benchmarks?" Pseudo-KDDs and Free KDDs make further use of the possibility of mixing types of expansions on a graph level, and changing orders of variables in its sub-graphs. The PKDDs and FKDDs are more difficult to be used as canonical representations than the KDDs. Further work must be thus devoted to create standard DD type algorithms to manipulate such diagrams. However, the PKDDs and FKDDs are already very useful for synthesis 15], since they produce diagrams with clearly less nodes than all the other diagrams.
The Boolean Ternary Diagrams have more powerful nodes than KDDs, so it is very likely that they will have less nodes. Since there are 9 instead of 3 possible expansion types for every expansion variable, the solution space of all diagrams is much larger, and we expect that more compact diagrams will be generated if good heuristics for variable and expansion type selections are found. The canonical BTDDs may be thus good candidates for canonical representations. Similarly, since the circuit realization of a BTDD node is not much more complicated than the-realization of a KDD node, and because of decreased diagram size, the canonical B.TDDs may be good candidates for synthesis of both completely and incompletely specified Boolean functions.
Finally, the canonical Boolean Ternary Kronecker Decision Diagrams include all the node types of KDDs, and still preserve their canonicity. For selecting the expansion type, one has only one choice in BDDs and original FDDs, two choices; in PRMTs and modified FDDs, three choices in KFDDs, nine choices in BTDDs, and twelve choices in BKTDDs. There is no danger of loosing good choices in BKTDDs, since the three standard expansions of the KDD are still available in them. Therefore, the exact BKTDD is never worse than the exact KDD.
Concluding, the introduced classes of decision diagrams open a very wide research area with many possible applications. It should be investigated whether they can drastically improve over BDD-based algorithms in such applications as spectral methods, mapping, decomposition, factorization, transduction, cellular logic synthesis, verification, testing, modeling and simulation, and technology mapping to FPGAs, especially fine-grain FPGAs.