An O ( NlogN ) Algorithm for Region Definiti , on Using Channels / Switchboxes and Ordering Assignment

For a building block placement, the routing space can be further partitioned into channels and switchboxes. In general, the definition of switchboxes releases the cyclic channel precedence constraints and further yields a safe routing ordering process. However, switchbox routing is more difficult than channel routing. In this paper, an O(NlogN) region definition and ordering assignment (RDAOA) algorithm is proposed to minimize the number of switchboxes for the routing phase, where N is the number of vertices in a channel precedence graph. Several examples have been tested on the proposed algorithm, and the experimental results are listed and compared.


INTRODUCTION
n VLSI layout design, most of the layout problems[ have been proven to be NP-complete, and heuristic approaches have been applied to reduce the complexity of those problems. Thus, many efficient algorithms have been proposed to obtain near-optimal solutions in reasonable time complexity. Basically, these layout problems are classified into the following main subproblems: placement, global routing, region definition and ordering assignment (RDAOA), detailed routing, and compaction. In this paper, we consider the RDAOA problem and propose an efficient algorithm for the problem. Consider the building block placement shown in Figure 1 and suppose that regions A, B, C, and D are all to be routed as channels. From the viewpoint of channel definition, the terminals in region B are not fixed, so region A must be routed before region B. For the same reason, region B must be routed before region C, region C must be routed before region D, and region D must be routed before region A. As a result, the iterative phenomenon of the precedence relation will construct a precedence cycle, and the cyclic constraint is named a cyclic channel precedence constraint [2]. Clearly, as a building block placement is with any cyclic channel precedence constraint, the placement will not be a slicing placement and the routing space will not be only decomposed into linear channels. In general, the cyclic channel prece-dence constraints are released by the definition of switchboxes or L-shaped channels. The solutions for breaking cyclic channel precedence constraints in the RDAOA problem have been studied for many years. Many various approaches have been proposed and discussed extensively in previous papers. For example, Otten [3] restricts the acceptable placements of slicing structures in order to avoid cyclic channel precedence constraints. Hence, it is clear that there is no cyclic channel precedence constraint in the given placement. On the other hand, a given placement may be modified to avoid cyclic channel precedence constraints by converting a nonslicing structure into a slicing structure. For example, Chiba [4] perturbs the placement to convert a non-slicing structure into a slicing structure, and Kimura [5] shrinks the placed modules to perform the same conversion. However, these techniques are to avoid the appearance of cyclic channel precedence constraints and not to break cyclic channel precedence constraints in a building block placement.
In recent years, the cyclic channel precedence constraints in a placement have been broken by introducing switchboxes [6][7][8] or by combining linear channels into L-shaped channels [2] [9][10]. From the viewpoint of routability, the width of a switchbox or an L-shaped channel is fixed and the routing completion is not guaranteed. In addition, switchbox routing or L-shaped channel routing is difficult than linear channel routing.
Hence, it is important for the completion of the routing phase to reduce the number of switchboxes or L-shaped channels. As a result, the purpose of the RDAOA problem will be to study how to introduce and minimize the number of switchboxes or L-shaped channels to break all of the cyclic channel precedence constraints in the building block placement. Recently, For the reduction of the number of switchboxes, Cai and Wong[ 11 propose a graph-theory approach that makes use of an O(N3) algorithm for computing minimum clique covers of triangulated graphs to minimize the number of switchboxes in 1991. However, the algorithm is too complicated and its time complexity is too inefficient. According to the properties of cyclic channel precedence constraints, we will propose an efficient algorithm for the RDAOA problem. For a cyclic channel precedence constraint, we can refer again to the building block placement shown in Figure 1. First, the height of region A can be estimated and fixed according to the routability consideration. The topological wiring paths on the junctions terminals between region A and region B will be generated and fixed in the global routing phase [12]. Then region B, region C and region D can now be routed sequentially as linear channels in that order. Subsequently, region A becomes a switchbox with fixed terminals on three sides and is routed by a switchbox router. As mentioned above, the cyclic channel precedence constraint will be broken by introducing a switchbox. By the same process, all the cyclic channel precedence constraints in the given placement will be broken by the definition of several switchboxes.

B FIGURE
A cyclic channel precedence constraint.
According to the previous description in the RDAOA problem, all the building blocks can be located on fixed positions by a macro-cell placement algorithm. In general, the routing space between any pair of adjacent blocks can be applied to route all of the nets in the routing phase. In order to guarantee the completion of the routing phase, the routing space must be partitioned into channels and minimum switchboxes, and the routing channels and switchboxes must be further assigned in a safe order. In this paper, we propose an O(NlogN) algorithm to partition the routing space into channels and minimum switchboxes and assign their routing ordering of these channels and switchboxes.

PRELIMINARIES AND DEFINITIONS
For the RDAOA problem, the following assumptions must be assigned to the proposed algorithm. Firstly, assume that all of the building blocks belong to rectangular modules. The routing space between any pair of adjacent blocks is represented by one horizontal or vertical line segment. Thus, the intersection points of the line segments represent the junction routing areas. From the geometrical relation of line segments and intersection points, all of the line segments and intersection points will construct a floorplan graph in the building block placement. Such a floorplan graph can be generated from a building block placement by a transformation algorithm [3]. The floorplan graph can be further applied to define the channels and switchboxes and assign their routing order. In Figure 2 (a)(b), a building block placement and its related floorplan graph are shown.
Secondly, as a floorplan graph has been generated from a building block placement, it is necessary to focus on two conditions of empty rooms and "+" type junctions [2]. Fortunately, the conditions of empty rooms and O(NLOGN) ALGORITHM 13 "+" type junctions have been studied and solved in the previous related papers. Based on these solutions, whenever there exists any empty room in the floorplan graph, the room will be removed by recursively removing one wall segment from each empty room until none are present in the floorplan graph [13]. Thus, it may be assumed that all of the empty rooms in the floorplan graph have been removed for the RDAOA problem. On the other hand, for the "+" type junctions, some algorithms were proposed to split one "+" type junction into two "T" type junctions [14]. In general, those splitting algorithms always remove all the "+" type junctions successfully in the floorplan graph by creating two "T" type junctions. Therefore, it may be assumed that the "+" type junctions in the floorplan graph have been separated into two "T" type junctions by a splitting algorithm for the RDAOA problem.
Based on the assumptions as mentioned above, a floorplan graph for the RDAOA problem only consists of horizontal and vertical line segments. Basically, each horizontal or vertical line segment in the floorplan graph can be represented as a linear channel. As two rows of terminals on one channel are fixed, the channel will be successfully routed by a channel router. In general, each "T" type junction in the floorplan graph consists of one horizontal channel and one vertical channel, and the base channel of the "T" type junction must be routed before the top channel of that. Therefore, the "T" type junction can be solved by a precedence routing relation. Based on the routing precedence relation, we can formally define a channel precedence graph from a floorplan graph and the related definitions can be discussed as follows: Definition 1" For a floorplan graph, E a channel precedence graph, G(F) (V, A), is a directed graph defined as follows: Each line segment in the floorplan graph is represented as a vertex of V. Each directed edge (u, v) is in A if and only if the line segments corresponding to u and v form a "T" type junction in the floorplan graph, and the one corresponding to u is the base of the "T" type junction.
From the construction of a channel precedence graph, if the graph is acyclic, the routing space will be decomposed into horizontal and vertical linear channels, and the order of these channels will be decided by the topological sorting in the graph. It is clear that the RDAOA problem can be solved by a topological sorting algorithm and no switchbox is assigned in the building block placement. Hence, it is unnecessary to minimize the number of switchboxes in the RDAOA problem. On the other hand, if the graph is cyclic, the RDAOA problem will not be solved by a topological sorting algorithm, and some vertices in the channel precedence graph must be defined as switchboxes to break all the cyclic channel routing constraints. Therefore, it is necessary for the RDAOA problem to remove a feedback vertex set from the channel precedence graph. The feedback vertex set in a directed graph will be defined as following: From the viewpoint of the RDAOA problem, if a channel precedence graph is cyclic, some vertices will be removed from the graph to generate a new acyclic channel precedence graph. As the removed vertices are defined as switchboxes, all the cyclic channel precedence constraints in the placement will be successfully broken and the vertices in the remaining acyclic channel precedence graph will be further defined as channels and ordered by a topological sorting. Therefore, the RDAOA problem in a building block placement will correspond to the minimum feedback vertex set (MFVS) problem in a channel precedence graph.
In general, the MFVS problem remains NP-hard [15] for a general directed graph. However, a channel precedence graph contains available graphical properties, and these properties can be applied to solve the MFVS problem. These graphical properties will be described in the following: Lemma 1: Let G be a channel precedence graph for a building block placement, G has the following graphical properties: Planar. Bipartite. Maximum out-degree is equal to 2. If IWl -> 4, then there are at least four vertices whose out-degree is not more than 1. The length of the smaller cycle, the minimal cycle, is 4.
Proof: The statement (1)-(4) have been proven in Cai and Wong's paper [ 11 ]. Furthermore, the proof of statement (5) can be explained as follows: one edge in any cycle is constructed by the "T" relation between one vertical segment and one horizontal segment. Hence, the number of vertical segments is equal to the number of horizontal segments in a cycle. Since the length of no cycle is 2, the length of the smaller cycle is 4. Q.E.D.
According to the topological position of building blocks, there will exist some minimal cycles in a channel precedence graph. From another viewpoint, each vertex in the graph may be located on at most four minimal cycles. For any vertex in the graph, the number of minimal cycles containing the vertex will be used as heuristic to minimize the number of switchboxes in the RDAOA problem.
For assigning the number of minimal cycles Ncycl for each vertex, it is necessary to detect all the minimal cycles in a channel precedence graph. Basically, the detecting process is a depth-first search. During one vertex visiting, an exhaustive search is applied to detect all of the minimal cycles. As a result, the number of minimal cycles for any vertex can be obtained after the depth-first search. Since the length of a minimal cycle is 4 and the out-degree of each vertex is at most 2, the detection of all of the minimal cycles during one vertex visiting will take 16 (2 4 searches in an exhaustive search. Clearly, the time complexity of an exhaustive search during one vertex visiting is in O(1) time. In addition, if the adjacent list is applied to store a channel precedence graph, the time complexity of assigning the number of minimal cycles for all vertices will be in O(IVI + IAI) time. On the other hand, because the out-degree of each vertex is not more than 2, the total number of edges in a channel precedence graph is not more than 2N, where N is the number of vertices in a channel precedence graph. As mentioned above, by statement (4), there are at least four vertices whose out-degree is not more than 1. Hence, the number of edges in a channel precedence graph is at most 2N-4, in other words, O(IAI) O(IVI) O(N). Hence, the time complexity of assigning the number of minimal cycles for all vertices is in O(N) time.

AN O(NLOGN) RDAOA ALGORITHM
In this section, an O(NlogN) RDAOA algorithm is proposed to minimize the number of switchboxes and assigning the ordering. As mentioned above, the MFVS problem is the most important issue in the RDAOA problem. Therefore, the solution of the MFVS problem for a channel precedence graph will be combined into the RDAOA algorithm.

RDAOA Algorithm
Due to the properties of a channel precedence graph, the properties will be used as heuristics to develop an efficient algorithm for the minimization of the number of switchboxes and the ordering assignment. By statement (1) and (3) in Lemma 1, the graph is planar and the maximum out-degree of any vertex is 2. Hence, (Ncycle, out-degree, in-degree) of any vertex can be applied to express the precedence condition for any vertex in the graph. In general, the comparison of (Ncycle, out-degree, in-degree) is determined by comparing Ncyce, out-degree and in-degree in a lexicographical order. The RDAOA algorithm is performed as follows: if the in-degree of one vertex in the graph is 0, the vertex will be defined as a channel, assigned an order and deleted from the graph. On the other hand, if the in-degree of no vertex in the graph is 0, the vertex with the largest (Ncycle, out-degree, in-degree) will be defined as a switchbox and deleted from the graph. Finally, all the defined switchboxes will be assigned the ordering. According to the algorithmic statements, a channel precedence graph is used as the input data and the RDAOA algorithm is Table I. Clearly, the time complexity of the RDAOA problem is reduced from O(N3) described in the Cai and Wong's paper to O(NlogN) in the proposed algorithm. In addition, for the example Ex6, the floorplan graph contains 136 line segments (71 vertical line segments and 65 horizontal line segments) and all the line segments are routed as switchboxes and channels. Finally, 24 switchboxes indicated by thick lines and 112 channels are defined to break all cycles and shown in Figure 4 by the proposed RDAOA algorithm.

CONCLUSIONS
In a building block placement, the routing space between any pair of adjacent blocks must be defined into a channel or switchbox and assigned the routing order for the routing phase. In this paper, we only introduce linear channels and switchboxes to obtain region definition and ordering assignment. For a channel precedence graph, an O(NlogN) RDAOA algorithm based on the properties of FIGURE 4 An example 71 65 (Ex6). the graph is proposed to minimize the number of switchboxes to increase routability. Several examples have been tested for the proposed algorithm, and the experimental results show that the proposed algorithm has improvement on the number of switchboxes.