Testability-Driven Layout of Combinational Circuits

The layout of a circuit can influence the probability of occurrence of faults. In this 
paper, we develop algorithms that can take advantage of this fact to reduce the chances 
of hard-to-detect (HTD) faults from occurring. We primarily focus on line bridge faults 
in this paper. We define a bridge fault f as an HTD fault if an automatic test pattern 
generator fails to generate a test vector for f in a reasonable amount of CPU-time. It is 
common practice to drop such HTD faults from consideration during test generation. 
The chip fault coverage achieved by a test set is poor if the fault set consists of many 
HTD faults. We can combat this problem by avoiding altogether, or by reducing the 
probability of, the occurrence of HTD faults. In this paper, we consider hard-to-detect 
bridging faults and show how module placement rules can be derived to reduce the 
probability of these faults. A genetic placement algorithm that optimizes area while 
respecting these rules is presented. The placement algorithm has been implemented for 
standard-cell layout style on a SUN/SPARC and tested against several sample circuits.


INTRODUCTION
The classical stuck-at fault model is a logical fault model and does not directly relate to physical manufacturing defects [8]. Thus, a physical defect that does not manifest itself as a stuck-at fault will remain undetected even if 100% stuck-at fault coverage is attained. Similarly, if testing reveals that a certain subset of stuck-at faults occur frequently, no preventive action can be taken to correct the manufacturing processes. In the recent past, other fault models such as bridge-faults and stuck-open faults have been introduced to alleviate *Corresponding author.
'347 this problem [4,5,7,6,8]. Jacomet introduced fault models which are influenced by the layout of the circuit [4,5]. In [6], Koeppe uses local transformations of the transistor-level layout to avoid the occurrence of certain stuck-open faults. In the same vein, Levitt [7]. In this paper, we consider bridge fault testability and its relation to circuit layout.
A bridge fault x@y occurs between two lines (signals) x and y if there is an electrical short between the two lines [1]. The effect of a bridge fault is to give rise to a wired-AND or a wired-OR between lines x and y. Bridge faults can be further classified into Feedback Bridge Faults and Nonfeedback Bridge Faults. A non-feedback bridge fault occurs when two lines which do not depend on one another are shorted; e.g a short between two primary inputs. On the other hand, when a bridge fault occurs between the output line and an input of a combinational circuit, the resulting feedback effect may give rise to sequential behavior. Such bridge faults cannot be satisfactorily modelled as stuck-at faults; recently IDDQ testing has been employed to test for the occurrence of bridge faults. Chakravarty and Thadikaran have introduced IDDQ test generation and fault simulation algorithms for both feedback and non-feedback bridge faults [2]. However, in their work bridge faults between all pairs of lines are considered for fault simulation. If there are n signal lines in the circuit, this would mean a fault set of size n. (n-1)/2a very large number for VLSI circuits. Knowledge about the layout of the circuit can be used to reduce the size of the fault set. Thus if two lines x and y are placed sufficiently apart in the layout, then the bridge fault x@y can be dropped from the fault set. An analysis of the layout is required for this purpose. In such an approach, the presumption is that layout will be performed first, and test generation and fault simulation will follow the layout phase. In this paper, we consider the synthesis of layout based on the results of a bridge fault simulation. Thus we present an approach where all the n.(n-1)/2 bridge faults will be considered and through efficient IDDQ test generation and fault simulation algorithms, we can identify a small set of hard-to-detect bridge faults. Chakravarty and Thadikaran have shown that such a fault simulation can be carried out in a reasonable amount of CPU time even for large combinational circuits [2]. Our approach is to use layout rules, which will reduce the chances of HTD faults during manufacture. Table I summarizes the .relative merits and demerits of the layout synthesis for testability approach and the post layout fault simulation analysis approach.

Confidence of Testing
Let H be the set of hard-to-detect (HTD) faults deived from the a fault simulation of an IDDQ test set T which considers all n. (n-1)/2 bridge faults possible in a circuit with n lines. The faultcoverage FC of the test set T is given by FC x 100% (1) where Fc is the set of faults covered by T and F is the fault set. If the layout of the circuit can be influenced by the knowledge of H to avoid a subset HcEH, then the fault coverage of a test set T improves to In this paper, we use a bridge fault simulator to derive the set of HTD faults (See Section 2). Layout techniques can be used to reduce the probability of occurrence of a bridge fault x@y; in this paper, we only consider module placement rules which help us in this direction (Section 3). In Section 4, we discuss a genetic placement algorithm which minimizes the chip area while conforming to these placement rules. Results and conclusions are presented in Section 5.

HARD-TO-DETECT BRIDGE FAULTS
We used the procedure shown in Figure

TESTABILITY-DRIVEN PLACEMENT
We define a pair of nets x, y as a critical pair if x@y is an HTD bridge fault. A testability-driven layout algorithm must ensure that the nets x and y are placed sufficiently far apart so that fault x@y is unlikely to occur. We define the bounding box of a net x as the smallest rectangle which includes all the pins of net x. Let BB(x) and BB(y) refer to the bounding boxes of the nets x and y in the circuit layout. If x @ y H and an overlap does not exist between BB(x) and BB(y), the bridge fault has low chance of actually occurring. This probability decreases rapidly as the distance between the rectangle increases. We shall define the distance between BB(x) and BB(y) as the smallest of the Euclidean distances of the form dist(P, Q), where P and Q are corner points of BB (x) and BB (y) respectively. A cost function can be formulated to evaluate the testability property of a given layout for a given set of HTD bridge faults. Let Overlap (x, y) be defined as shown in Equation 3 for two nets x and y. The procedure TestCost shown in Figure 2 computes the testability cost. In the next section, we shall use a genetic algorithm which minimizes the testability cost of the layout. Computationally, the testability evaluation procedure is fast and requires O(IHI) time. A faster (but less accurate) testability estimation procedure can be devised by omitting the else part in the procedure of Figure 2.
Overlap (x, y) -1 if BB (x) f3 BB( y) =, 0 otherwise 4 GENETIC ALGORITHM Genetic algorithms are inspired by the biological process of evolution and natural selection; they .have been used to solve many optimization problems [3,9]. A genetic placement algorithm called GENIE was presented in [3]. A standard-cell placement program based on the genetic algorithm, called GASP, is described in [9]. The genetic algorithm maintains a population of solutions, which are treated as individuals in a society. A crossover operator is applied to a pair of solutions (parents) to obtain a third solution (offspring). The offspring shares properties of both the parents. In addition, sometimes a randomized operator known as mutation is applied to the offspring to introduce new characteristics that are not present in either of the parents. A number of offspring are generated and the survival of the fittest rule is applied to maintain the size of the population at the original level. This completes a single generation of the genetic algorithm; at the end of each generation, the average cost of the population improves. The genetic algorithm runs through several generations until convergence is achieved; convergence may be defined as the condition when the best individual in the population has not improved in terms of cost function over a predefined number of generations.
We used the genetic algorithm for solving the testability-driven placement problem. The motivations for using the genetic algorithm are the algorithm can handle a number of objective functions such as testability cost, wiring length, and wiring congestion; the algorithm can lead us to global optimal solutions since it explores a much larger search space than other competing algorithms [9].
The overall algorithm is shown in Figure 3. The procedures used within the genetic algorithm are summarized in Table II. A solution to the placement problem is represented in the form of 2-dimensional array 79, where 79(i, j) contains the number of modules placed in the i-th row and j-th column. The placements which constitute the initial population were generated using a constructive placement algorithm similar to the one used in [3]. The crossover operator used in our implementation works by copying a patch of placement from parent M and the remaining placement from parent F. Figure 4 shows the details of the crossover operator. If the patch (set of locations) selected in the crossover operator corresponds to the bounding box of a net x which is part of a critical pair, the resulting offspring is less likely to have overlaps. The objective of the mutation operator is to reduce the bounding rectangle of a randomly selected net, which is achieved by a constructive procedure. When selecting a net n for mutation, priority is given to a net which belongs to a critical pair; this improves the testability of the resulting layout by reducing the chances of overlap of BB(n) with bounding boxes of other nets.
The fitness measure used in our placement algorithm is a weighted sum of three cost functions which represent the total wirelength, wiring congestion, and the bridge-fault testability. The bridge-fault testability cost is estimated using the procedure shown in Figure 1. The estimators of wire length and congestion are well known in literature; we refer the reader to [3,9]. 5

RESULTS AND CONCLUSIONS
We have implemented the testability-driven placement algorithm on a Sun-SPARC workstation in the C programming language. Standard-cell layout style is a assumed in our implementation. We also implemented a parallel version of the genetic placement algorithm on a 32-node Meiko transputer; parallelization was achieved by decomposing the parameter space. We ran multiple copies of the genetic algorithm on different nodes of the transputer, each of them using a different set of genetic parameters. The important genetic parameters are the convergence parameter Pmax, the population size P and the mutation probability #. We experimented with several combinational circuits and the results are tabulated in Table III. The Table shows the percentage of the testability constraints satisfied by the final placement and the increase in the wiring cost to achieve testability. As explained in the previous section, a testability constraint requires two nets x and y to be placed far apart, where x, y belong to a critical pair. The increase in wiring cost is measured against the wiring cost when the testability requirement is turned off by setting the weight of the testability cost to zero in the composite cost function.

Conclusions
In this paper, we have presented a genetic algorithm for testability-driven placement. The fault model considered in this paper includes bridge faults which relate closely to the physical design of the circuit. We found that at the cost of a marginal increase in the total wiring cost, the confidence level of a bridge-fault test can be improved significantly. Our work can be extended by considering the testability constraints in other stages in physical design such as global routing and channel routing. A global router implements each net in the form of a Steiner tree; one can consider global routing as a constrained optimization problem, where the Steiner trees corresponding to nets of a critical pair are to be constructed in a non-overlapping fashion. Despite testabilitydriven placement and global routing, there may be violations of testability constraints; a channel router can handle these leftover constraints by placing the nets of a critical pair in two different layers.