Signature Analysis for Test Responses of Sequential Circuits*

Many test schemes use signature analyzers to compact the responses of a circuit under test. Unfortunately, there can be some faulty circuits with erroneous test responses but exactly the same signature as in the fault-free case. Hence, methods are required to determine how many faults become undetectable due to aliasing. Whereas previous work concentrated on combinational circuits, this paper investigates signature analysis for a wide range of sequential circuits, where the errors in successive responses are correlated. It is shown that for almost all faults of these circuits the probability of aliasing in a signature analyzer with k bits asymptotically approaches 2 - or is 0 if a signature analyzer with an irreducible characteristic polynomial is used and certain test lengths are avoided. The limiting value can be used as a good approximation for practical test lengths. These results are particularly useful for advanced built-in self-test techniques with low hardware overhead.


INTRODUCTION
Built-in self-test (BIST) is one of the most promising techniques for solving the test problems of large and complex circuits and systems [1]. Built-in pattern generators produce patterns that are applied to a (sub-)circuit under test (CUT). The test responses at the outputs of the CUT are collected by an integrated compactor. At the end of the test, the contents of the compactor (i.e., the signature of the CUT) are compared to the signature of the fault-free circuit. If they do not agree, the CUT is considered faulty.
Due to a loss of information during compaction, however, even some response sequences that differ from the error-free sequence can lead to the *Signature Analysis and Aliasing for Sequential Circuits by A. P. Stroele  A.P. STROELE error-flee signature (aliasing). Thus, the CUT may contain a fault that causes errors in the test responses, but is not detected by a differing signature. In order to assess the quality of the applied selftest, it is important to determine how many of the faults can escape.
In principle, the exact number of masked faults can be determined by simulating the CUT and the response compactor for every single fault over the whole test length. But for large circuits, this is computationally unfeasible, in particular, if the simulations have to be done multiple times.
An alternative is to model the response compaction process in a probabilistic way and derive an analytical expression for the probability of aliasing. Then the portion of masked faults can be estimated simply by evaluating this formula. Most BIST techniques apply a large number of pseudorandom patterns resulting in an equally large number of test responses. Thus, the limiting value of the aliasing probability for large test .lengths is the key point for evaluating the performance of a response compactor. Fast computation of this limiting value allows us to easily compare different types of compactors and to optimize the parameters of a compactor with respect to a minimal number of aliased faults.
For test response compaction, usually signature analyzers based on linear feedback shift registers [2] and cellular automata [3] are preferred since they can be implemented with a relatively small hardware overhead and achieve good compaction performance. Signature analysis for the responses of combinational circuits is well understood (see the review of previous work in Section 2). Successive test responses of combinational circuits and also the errors contained in them are statistically independent. The results of previous work can be used for BIST schemes that partition the circuit into purely combinational subcircuits and integrate all the flip-flops into scan paths or test registers. However, implementations of these BIST schemes require a relatively large hardware overhead and may slow down the circuit due to the slower scan flip-flops.
In contrast, with advanced BIST techniques only a subset of flip-flops is enhanced to scan flipflops or test register cells [4][5][6][7][8][9][10]. Thus, the hardware overhead is reduced significantly and in many cases performance degradation can be avoided. Again, in the test mode the circuit is segmented into subcircuits that are surrounded by scan registers or test registers (e.g., BILBOs [11]). But now the subcircuits contain flip-flops. As a consequence, errors in the test responses of the subcircuits can be correlated in time. All the previous results on aliasing which are based on the assumption of statistically independent test responses are not applicable; a new approach is required. This paper deals with the sequential subcircuits that typically occur with advanced BIST techniques. To avoid excessive test lengths, these subcircuits usually have an acyclic structure at gate level such that they can be initialized easily. The assumptions that we use to derive our results on aliasing are significantly more general than in previous work, and many findings of recent years are included as special cases. In all situations where these assumptions hold, the aliasing probability tends to the smallest value that can be achieved, namely 1/2 for a signature analyzer with k flipflops.
The paper is an extension of [12]. It is organized as follows. Section 2 introduces a formal description of the test response compaction process and reviews previous work. Section 3 first gives an example of a sequential circuit where dependencies between successive response errors increase the probability of aliasing drastically compared to the probability predicted under the assumption of statistically independent errors. Then we propose a set of more general assumptions that hold for most circuits with BIST, In Section 4, the probability of aliasing in a signature analyzer is investigated under these general assumptions, and its limiting value for increasing test lengths is derived. Section 5 shows that numerous situations of practical importance are included. Experimental data, which have been obtained by simulation, are presented in Section 6 followed by conclusions in Section 7. The pattern generator, the CUT, and the response compactor are clocked synchronously. In the time interval between t-1 and t, a pattern d(t-1) is applied to the inputs of the CUT (see Fig. 2). At time a new state z(t) is stored. Immediately after time t, a new pattern d(t) is applied. This causes the outputs to get a new value r(t) that depends on d(t) and z(t). With the following clock pulse at time / 1, the test response r(t) is compacted and the compactor reaches a new state s(t + 1).
All the patterns, states, and test responses can be described by column vectors whose components are elements of GF (2). 0 denotes the all-zero vector. The bijective mapping bin: {0, 1,..., 2 k-} {0, }k maps each integer n E {0, 1,..., 2 -) to its binary representation, bin(n): (n_l, nk-2,..., no)T, where n E {0, 1} for u 0, 1,..., k-1 .2 2 and :0n -n. In this paper, boldfaced letters like n stand for binary vectors, and italics like n denote the corresponding integers. Figure 3 shows a signature analyzer based on a general linear finite state machine. As special cases, linear feedback shift registers and cellular automata are included. The contents of the register (k bits) are fed to a linear network, whose mapping  {0, 1}. The vector at the output of this network and the test response of the CUT (k-bit vector r) are added bitwise modulo 2. The sum gives the next state of the signature analyzer, s(i+ 1)= C. s(i)(R) r(i). After a sequence of test responses has been fed to the signature analyzer, the register contains the signature s(t) Us(0) Ct-l-ir(i) where )i0x(i) denotes the bitwise sum x(0) x(1) 0... x(n). As signature analysis is a linear operation, it is sufficient for the investigation of aliasing to consider the bitwise differences between the observed test responses r(i) and the error-free test responses ref(i), namely the error vectors e(i):= r(i)Oref(i) [13]. Without restriction of generality, we initialize the signature analyzer to s(0)= 0, and feed to it only the error vectors e(i). Then the signature at time is s(t)= 1I-Ct--ie(i) (Actually, this corresponds to the difference between the signature for the observed responses r and the signature 130 A.P. STROELE for the error-flee responses r,f). For an error-flee response sequence, e(0) e(1) e(t-1) 0, we get s(t)= 0. Aliasing occurs when erroneous test responses have been compacted, but still the signature of the error-flee case is observed.

DEFINITION
The probability of aliasing at time t, pa(t), is the probability that the contents of the signature register at time do not differ from the fault-flee case and at least one nonzero error vector has occurred, p(t) := Pr(s(t) 0) Pr(e(0) e(t-1) 0). In recent years, several different ways to model the errors have been proposed. The symmetric channel error model [14,15] assumes that the errorfree response vector occurs with probability P0 and all the possible erroneous test responses have an equal probability of (1-p0)/(2 -1). In the independent error model (e.g. [16]), error bits at different outputs of the CUT are statistically independent and can have different probabilities. The more general error model of [17] and [18] specifies the probabilities of all the 2 possible error patterns individually. The common assumption of these error models is that errors in successive responses are statistically independent. This is valid for purely combinational circuits and faults that do not introduce sequential behavior. A multitude of results has been derived under these models including closed form expressions, simple bounds, and limiting values of the aliasing probability [14-17, 19, 20]. In particular, it has been proved that for every fault (regardless of the error probabilities) the aliasing probability of a signature analyzer is zero or tends to 2for long test lengths provided that certain test lengths are avoided and the characteristic polynomial ofthe feedback matrix C is irreducible. 2is the smallest asymptotic value that can be achieved if the error-flee test response is not known a priori [21]. Simulation experiments have demonstrated that the asymptotic value is a good approximation of the actual aliasing probability if the test length is not extremely short [22][23][24].
However, if the CUT exhibits sequential behavior, errors in successive responses can be corre-lated. This makes the analysis of aliasing more complex. First studies dealt with conditions for aliasing and analyzed aliasing in presence of burst errors [16,25,26]. Recently, the symmetric channel error model has been extended to account for time correlation. The probability of an erroneous response is increased by a constant factor if the previous response has been erroneous [27]. Aliasing has also been studied for combinational circuits with stuck-open faults and delay faults [28,29], for full scan designs with combinational faults [30], and for sequential circuits with fault-free hardware reset [31]. But these results are not sufficient for advanced BIST techniques which now are in the center of interest (see Section 1).
The transition probabilities of the signature analyzer depend on the probabilities of the error patterns in the test responses. These in turn depend on the probabilities of the input patterns and on the current state of the CUT. So in general, the transition probabilities are not constant in time.
Moreover, since the current state of the CUT depends on the previous state and on the previous inputs, the transition probabilities are correlated in time. Hence, in many cases the stochastic process (S(t))t>_o is not a Markov chain, and the well-known Markov models [16,17,19]

BASIC ASSUMPTIONS
Before the stochastic chain (S(t))t>_o is analyzed in order to derive results for the aliasing probability, the basic assumptions have to be discussed. We begin with an example of a sequential CUT where dependencies between errors in successive test responses increase the probability of aliasing compared to the probability predicted under the assumption of statistically independent errors.
Let E be the set of patterns that can occur as error vectors at the outputs of the CUT, tional CUTs with combinational faults, the aliasing probability approaches 2 -k for long test lengths provided that at least two error patterns can occur, IE[ >_ 2, and the multiple input signature register (MISR) has an irreducible characteristic polynomial [16,19]. If the same MISR is employed to compact the test responses of sequential CUTs where [E _> 2 also holds, but the errors are correlated in time, then limt-Pal(t) 2 -k cannot be guaranteed. As an example we consider a CUT that includes a modulo 5 counter and some combinational logic and has 4 primary outputs. The circuit is tested using random patterns, the test responses are compacted by a 4-bit MISR with characteristic polynomial x 4 / x + (see Fig. 4).
The feedback matrix of the MISR is Let the CUT have a fault that can be observed at its outputs only if the embedded counter is in a specific state, e.g., the state that is reached periodically at 5i / 4, 0, 1,... Furthermore, we assume that at these times the error vectors 0 and a # 0 occur with probabilities P0 and 1-P0, respectively, 0 < P0 < 1. All the other test responses are error-free.
In this case the sequence of MISR states at times  It can be shown that choosing any other characteristic polynomial of the same degree or replacing the MISR with external XORs by a MISR with internal XORs cannot improve the situation. Generally, whatever the features of the MISR are, sequential CUTs and faults can be found such that the aliasing probability converges to a limiting value much larger than the optimal value 2-k.
But on the other side, useful circuits do not have arbitrary structures. Design for testability and particularly built-in self-test lead to restrictions of the design space. These restrictions can be exploited when test response compaction and aliasing are analyzed. The following assumptions consider typical BIST environments, but they are also valid in many other cases. In the next section, it will be shown that these assumptions guarantee that the aliasing probability tends to 2 -k for increasing test lengths.
(i) The input patterns are chosen randomly.
(ii) For at least one state z0 of the CUT a synchronizing sequence exists. The synchronization state z0 as well as the synchronizing sequence may be different for circuits with different faults.
(iii) For a faulty circuit initialized to a synchronization state z0, there are input sequences d(0), d(1),..., d(t-1) and d'(0), d'(1),..., d'(t-1) that transfer the CUT to the same state, z(t) z'(t), but result in different signatures, s(t) :/: s'(t). (iv) The characteristic polynomial det (xI-C) of the matrix C, which specifies the linear feedback network of the signature analyzer, is irreducible, i.e., it cannot be factored. (I is the identity matrix.) Motivated by numerous BIST schemes which apply pseudorandom patterns, all the known probabilistic models implicitly or explicitly assume that test patterns are applied randomly (assump-tion (i)). The input patterns can have different probabilities of occurrence.
A synchronizing sequence is defined as an input sequence whose application is guaranteed to leave the circuit in a certain final state regardless of its initial state. Signature analysis testing requires that the signature of the fault-free circuit is known. This is possible only if the circuit is initialized to a known state before testing begins. Thus a synchronizing sequence must exist.
Moreover, many partial scan and partial intrusion BIST techniques break all cycles of the circuit structure by inserting scan flip-flops or test register cells [4-6, 8, 10]. Then every state of the resulting acyclic circuit can be reached with a number of input vectors that corresponds to the sequential depth of the circuit. So synchronizing sequences exist for all states. And we can expect that also for the faulty circuit there is a synchronizing sequence for at least one state, and assumption (ii) is valid.
In order to point out that assumption (iii) holds in almost all cases, we consider the two situations  In order to change the contents of the signature register from s(/) to s(i + 1), the error vector e(i) s(i + 1) (R) Cs(/) must occur.
In general, e(/) is a function of d(/) and z(i). This function g(d, z) is implicitly implemented by the combinational part of the faulty circuit. The number of possible functions g is 2 knnz where nd is the number of possible input patterns and nz is the number of possible states.
In the special situation considered, the error vector e(/) is determined by the next state function of the CUT and the mapping f. Since the next state function is fixed and the number of possible mappings f is 2k'nz, the portion of functions g that satisfy the imposed restrictions is 2k'm/2 k'nd'nz 1/2 k'(nd-1)'nz. This value is extremely small. Even for a very small circuit with 5 inputs (32 possible input patterns), 3 outputs, and 10 states, we get 1/2 k'(nd-1)'nz 1/233110 < 10-270.
So we can conclude that assumption (iii) holds for almost all faulty circuits where the error vectors are not identical.
For statistically independent error vectors, only the signature analyzers with irreducible character-istic polynomials can guarantee the asymptotic aliasing probability limit of 2 - [17]. Since statistically independent error vectors are a special case of the situation considered here, a condition weaker than (iv) cannot be sufficient for a limiting value of 2-. In contrast to the error models of previous approaches, which make assumptions on the distribution of the errors at the outputs of the CUT, the assumptions used here refer to the CUT directly. So it should be easier to verify them for a specific CUT.

PROBABILITY OF ALIASING
This section shows that the assumptions stated in the previous section are sufficient for the aliasing probability to converge to the limiting value 2-k.
We proceed in the following way. First, it is proved that the stochastic chain (S(t))t>o, which describes the sequence of states of the signature analyzer, is irreducible and aperiodic. Its transition matrices are doubly stochastic. Then, using these facts we prove that (S(t))t>_o has a limiting distribution. Finally, the limit of the aliasing probability is derived from this distribution.
As the transition probabilities of the stochastic chain are not constant in time, the definition of the terms "irreducible" and "aperiodic" must consider time explicitly. The following definitions include the corresponding definitions for time homogenous Markov chains [32] as a special case. DEFINITION 2 A state is reachable from state j if for each time > 0 there is a number nt such that the nt-step transition probability ,/ (t) is nonzero. It can easily be proved that for a signature analyzer with irreducible characteristic polynomial the transition matrices P(t) of the stochastic chain (S(t))t>_o are doubly stochastic (i.e., every row sum and also every column sum gives 1).
The distribution 7r (1/2k,..., 1/2k)r is a stationary distribution of the stochastic chain (S(t))t>_o since 7r P(t). 7r holds for every doubly stochastic matrix P(t). The following theorem shows that this stationary distribution is the unique limiting distribution. THEOREM 2 Let (S(t))t>_o be the stochastic chain that describes the state sequence of a signature analyzer with an irreducible characteristic polynomial of degree k. If the assumptions (ii) and (iii) hold, the limiting distribution of (S(t))t>_o exists and its value is limtr(t) (1/2,..., 1/2/)r.
Proof In order to prove that the distribution r(t) converges to (1/2g,..., 1/2) ', it is sufficient to show that the difference between the maximum and the minimum of the state probabilities, 7rmax(t)"-max0<i<2_l {ri(t)) and 7rmin(t) := min0<i<2_l {Tri(t)), respectively, tends to 0 for cx. limt_ (Trmax(t) 7rmin(t)) 0 implies that the probabilities of all states become equal and tend to 1/2 k. Every m-step transition matrix P(m)(t)-P(t + m-1) P(t), m > 0, is doubly stochastic since it is a product of doubly stochastic matrices. Let

a'max(t) --Pmin(t)" ('a'max(t) 7rmin(t))
In a similar way, is obtained. Combining the last two inequalities we get The difference 7rmax(t)--Trmin(t) is monotonically decreasing with the increase of the test length t.
As the stochastic chain (S(t))t>o is irreducible and aperiodic (Lemma 1), a constant m0 exists such that for arbitrary >_ 0 each state s(t 4-m0) can be reached from each state s(t). (The proof of Lemma gives mo k'u4-tsync). Every m0-step state transition is caused by at least one specific input pattern sequence of length m0. Let q be the smallest nonzero probability of occurrence of all possible m0-pattern input sequences. Then we certainly have mo) min (t) _ q > 0 for all t> 0. According to (,), at time h.mo the difference 7rmax(t)-7rmin(t) is at most (1 2q) h. Because of limh(1 2q) h 0 we finally get limt_(Trmax(t)-rmin(t))=0, which completes the proof. Q.E.D.
Finally, the following corollary gives the limit of the aliasing probability.
COROLLARY Let a signature analyzer with irreducible characteristic polynomial of degree k compact the test responses of a combinational or sequential circuit. If the assumptions (ii) and (iii) hold, the probability of aliasing converges to limt_o Pal(t) 2-k. Proof Since in the error vector sequence at least two different values occur with nonzero probabilities, the probability that the sequence of test SIGNATURE ANALYSIS 135 responses is error-flee tends to 0 as the test length tends to infinity, limtPr(e(0) e(t-1)= 0)=0. Using Definition and Theorem 2, this gives limt-pat(t) limt Pr(s(t) 0) Taken together, Theorem and Corollary show that for almost all faults the probability of aliasing in the signature analyzer asymptotically approaches 2 -k and in special cases it is zero provided that certain test lengths are avoided.

IMPORTANT CASES
The result of the previous section includes many results known from literature as special cases, e.g. [16,17,19,[28][29][30][31]. In order to demonstrate the broad range of circuit and fault classes that are covered by the assumptions described in Section 3, we show for some important cases that the assumptions are satisfied (in particular assumptions (ii) and (iii)).

Combinational Circuits with Combinational Faults
Combinational faults (e.g., stuck-at faults) change the function of the circuit, but in contrast to delay faults and stuck-open faults they do not introduce sequential behavior. Thus the CUT is always in the same state, and explicit synchronization is not required. The synchronizing sequence has length 0. If the fault is detected by some but not all input patterns, or more general IEI _> 2, then input patterns d(0) and d'(0) exist that lead to error vectors e(0) e'(0) and thus s(1)s'(1). So assumptions (ii) and (iii) h01d, and Theorem 2 and Corollary 1 include the results that have been proved in [16,17,19] for the limiting value Ofpat(t).

Combinational Circuits with Delay Faults that Cause Errors Lasting One Clock Cycle
Delay faults most frequently do not exceed one clock period. If two successive input patterns are identical, d(t-1) d(t), then the response r(t-1) may be erroneous due to the delay fault, but the response r(t) is error-flee. Generally, r(t) depends on d(t) and in case of a delay fault also depends on d(t-1), but not on any input patterns applied before time t-1. Hence, an arbitrary pattern d(t-1) can serve as a synchronizing sequence because it uniquely determines the transient state of the circuit at time t. Testing such a delay fault requires a pair of input patterns applied at speed. The first pattern initializes the circuit, the second pattern makes the fault observable at a primary output of the circuit. Consequently, assumption (iii) holds.

Combinational Circuits with Stuck-open Faults
Stuck-open faults in CMOS circuits make it impossible to charge or discharge a circuit node when certain input patterns are applied. In this way, sequential behavior is introduced without creating feedback connections. The state of the circuit is determined by the charge stored at the nodes. 136 A.P. STROELE As the faulty circuit still has an acyclic structure, input sequences exist that set the circuit to specific states regardless of the initial state. Let the circuit be initialized to an arbitrary, but fixed state at time t-0. If the considered single or multiple stuckopen fault is detectable, there must be an input sequence (d(0),..., d(t 3), d(t 2), d(t 1)) with d(t-2) d(t-1) that gives an error sequence combinational FIGURE 6 Test configuration for a circuit with full scan.

Full Scan Circuits with Combinational
Faults Figure 6 illustrates the test configuration for a circuit with full scan. Every input pattern contains one bit for the serial input of the scan path, the other bits are applied to the primary inputs of the combinational part of the circuit (or ignored). Let be the length of the scan path. Each input sequence of length is a synchonizing sequence since it sets the circuit to a new state regardless of the previous state. After that, the immediate response at the primary outputs is compacted by a MISR, and the next state response is latched in the scan path. Concurrently to shifting a new bit sequence into the scan path, the bits of the next state are shifted out and compacted by a single input signature analyzer (SISR). Test response compaction for the combinational part of the circuit has already been considered at the beginning of this section. Here we consider aliasing in the signature analyzer connected to the serial output of the scan path. Only the clock pulses for shifting the scan path and simultaneously compacting its contents are counted.
If the SISR has a characteristic polynomial of degree k that is irreducible, the state transition diagram of the SISR operating under constant input 0 consists of cycles that all have the same length nc and one cycle of length [33]. Of course, nc must be a divisor of 2 k-1. Lemma requires synchronizing sequences of length u where u is relatively prime to nc (see appendix). In the special situation considered here, synchronization can be achieved only after 1,21,31,... input vectors.
Hence, Lemma applies if and only if the length of the scan path is relatively prime to nc, i.e., gcd (l,n) 1, and then Theorem 2 and Corollary hold. This is a more general result than presented in [30] where the limiting value limt--,pat(t)= 2 -k has been proved only for signature analyzers with primitive characteristic polynomials and gcd (l, 2 k-1)= 1. In addition, the derived limiting value is also valid for stuck-open faults in the combinational part of the CUT.

Sequential Circuits with Hardware Reset
Under the assumption that the reset mechanism is not degraded to partial reset in the faulty circuit, every input pattern with active reset bit is a synchronizing sequence. If not all the error patterns are identical, then assumption (iii) holds (see also [31]), and again we have the same limiting value of the aliasing probability. ments are described where successive error vectors are strongly correlated. It was assumed that a part of the circuit under test behaves like a resettable counter with a cycle of length w. At time 0 the CUT was initialized to a known state z0 for which a synchronizing sequence existed. After state z0 had been left, only the w-th, 2w-th, 3w-th,... test response could be erroneous. At these times nonzero error patterns occurred with probability l-p0. All the other test responses (including the test responses in state z0) were error-free. The CUT was forced to state z0 again at times that were kept fixed throughout an experiment. Before the experiment started, these synchronization points were chosen randomly, each point of time was selected as a synchronization point with a given probability Psync.
The first set of experiments dealt with a CUT having 4 outputs. Using a random number generator, 100000 test response sequences were generated according to the above specification with w 5, P0 0.5, possible error patterns (0, 0, 0, 0)7and (0, 0, 1, 0)7-, and different sequences of synchronization points (Psync 0.1). Compaction with the same 4-bit MISR as in Figure 4 was simulated, and the aliasing events were counted for each time separately. At time an aliasing event occurs if some nonzero error vectors have appeared, but the signature s(t) is 0. The probability of aliasing was estimated by 6

. EXPERIMENTAL RESULTS
In practice, the signature of the fault-free circuit must be known. So the pattern sequence applied to the inputs can be chosen arbitrarily, but for all chips implementing the same design the pattern sequence must be the same. This implies that the times where the circuit is forced to a synchronization state are the same for most of these chips. Due to different faults, however, the applied patterns can cause a multitude of different error sequences at the outputs of the CUTs.
In order to emphasize the difference to signature analysis for combinational circuits, here experi-  Figure 8 shows the results.
In both cases, the number of nonzero error vectors was almost the same. But due to the larger number of different error patterns, in case (b) the aliasing probability approaches its limit faster. For comparison, test response sequences of combinational circuits were also considered. Each test response was faulty with probability 1-P0 0.1. The nonzero error pattern was always (0, 0, 1, 1, 1, 0, 0, 0) 7corresponding to situation (a), or every nonzero error pattern occurred with equal probability corresponding to (b), respectively. With these sequences of statistically independent error vectors, the probability of aliasing in the 8-bit MISR converges faster. For > 50 and _> 39, respectively, Pal(t) differs from 2 -8 by less than 10% (see Fig. 9). Independently of the chosen irreducible characteristic polynomial, two observations are made. If the number of different error patterns that occur with nonzero probability is reduced, the probability of aliasing approaches its limiting value more slowly. Convergence is also slower if correlation between successive error vectors is stronger and the number of times at which different error patterns can occur is reduced. In summary, convergence is slower if correlation in time and/or in space is stronger.

CONCLUSIONS
If the number of test responses is large, compaction is necessary. In order to choose an appropriate response compactor, to optimize its parameters, and to assess test quality, the portion of faults that do not lead to an erroneous signature must be determined. An efficient way is to employ a probabilistic model ofthe compaction process and estimate the portion of undetected faults by the probability of aliasing. This paper has investigated signature analysis for sequential circuits. When test responses of sequential circuits are compacted, strong correlations between errors in successive responses can significantly increase the probability of aliasing.
However, the situation is much more favorable if the circuit under test can be set to a fixed state by applying a certain sequence of input vectors. This requirement is met in particular by a large variety of circuits with built-in self-test. For most faults of these circuits, the probability of aliasing in a signature analyzer with an irreducible characteristic polynomial of degree k tends to 2 -k as test lengths increase. For some other faults, aliasing does not occur if certain test lengths are avoided.
The portion of faults for which these results do not hold has been shown to be extremely small. Experiments have demonstrated that the limiting value can be used as a good approximation of the actual aliasing probability at practical test lengths.
The results are important for advanced BIST techniques with low hardware overhead. Recently developed techniques integrate only a subset of the flip-flops into scan chains and test registers, the subcircuits between the scan chains and test registers contain the remaining flip-flops. Now signature analysis can be applied to these sequential subcircuits in a similar way as to combinational subcircuits.