Advanced Readout System IC Current Mode Semi-Gaussian Shapers Using CCIIs and OTAs

Novel CMOS current mode shapers for front-end electronics are proposed. In particular, six semi-Gaussian shaper implementations based on second generation current conveyors and operational transconductance amplifiers are designed using advanced filter design techniques. Although all shaper architectures are fully integrated, they satisfy a relatively large peaking time. The topologies are analytically compared in terms of noise performance, power consumption, total harmonic distortion (THD), and dynamic range (DR) in order to examine which is the most preferable in readout applications. Design technique selection criteria are proposed in relation to the shaper structures performance. Analysis is supported by simulations results using SPICE in a 0.6 μm process by Austria Mikro Systeme (AMS).


INTRODUCTION
Recent developments in semiconductors detectors, VLSI electronics, and information technology enabled the adaptation of radiation detecting systems used in high energy physics experiments in various imaging applications. These radiation detecting systems require compact, low-cost, and low-noise electronics with a high number of channels. Several motivations suggest that most of these applications can benefit from the use of ASIC (application specific integrated circuit) readouts instead of discrete solutions. The most crucial motivation is that the implementation of readout electronics and semiconductor detectors onto the same chip offers enhanced detection sensitivity thanks to improved noise performances [1][2][3][4][5]. Placing the very first stage of the front-end circuit close to the detector electrode, without using external wires, may reduce the amount of material and complexity in the active detection area and minimize connection-related stray capacitances. This method allows the noise optimization theory predictions [6,7] to be satisfied more effectively, especially in the case of silicon sensors with very low-anode capacitance (silicon drift detectors, CCDs, pixels). On the other hand, the use of discrete transistors, with their relatively high (a few picofarads) gate capacitances, as front-end elements of hybrid circuits cannot comply with the stringent low noise requirements. As a result, continuous efforts were performed in order to implement readout systems in monolithic form, and CMOS technologies have been chosen due to the high integration density, relatively low-power consumption and capability to combine analog and digital circuits on the same chip.
The preamplifier-shaper structure is commonly adopted in the design of the above systems. A block diagram of such a detection system is shown in Figure 1. An inverse biased diode (Si or Ge) detects radiation events by generating electron-hole pairs proportional to the absorbed energies. A low-noise charge sensitive preamplifier (CSA) is widely used at the front end due to its low-noise configuration and insensitivity of the gain to the detector capacitance variations. The generated charge Q is integrated onto a small feedback capacitance C f , which gives rise to a step voltage signal at the output of the CSA with an amplitude equal to Q/C f . This is fed to a main amplifier, called pulse shaper, where pulse shaping is performed to optimize the S/N system ratio. The resulting output signal is a narrow pulse suitable for further processing.
Although the above typical voltage mode architecture was sufficiently studied mainly in terms of the charge sensitive preamplifier (CSA) input transistor for noise reduction  Figure 1: Block diagram of a detector readout system. [6][7][8], few studies have been performed on pulse shapers and especially on current mode designs.
After all, many current mode preamplifiers were so far suggested [9][10][11][12][13]. This is due to the fact that a current mode structure could be an attractive alternative to the more typical voltage mode one, since the signal is processed in the current domain, avoiding charging and discharging of the parasitic capacitance to high-voltage levels and keeping the internal nodes of the circuit at low-impedance values [14][15][16][17][18].
In this work, current mode S-G shaper designs based on second generation current conveyors (CCIIs) and operational transconductance amplifiers (OTAs) are proposed. Advanced filter design techniques [19,20], which provide full integration, are used and novel CR-RC 2 implementations are suggested. All the implementations are compared in terms of noise performance, power consumption, total harmonic distortion (THD), and dynamic range (DR) in order to conclude which the optimum one is.

SEMI-GAUSSIAN SHAPER ANALYSIS
Pulse shaping filters are used in electronics spectrometer instruments to measure the energy of charge particles [21]. The purpose of such filters is to provide a voltage pulse whose height is proportional to the energy of the detected particle.
The theory behind pulse shaping systems, as well as different realization schemes, can be found in the literature [21][22][23]. It has been proved that a Gaussian shaped step response provides optimum signal-to-noise characteristics. However, the ideal S-G shaper is noncasual and cannot be implemented in a physical system. A well-known technique to approximate a delayed Gaussian waveform is to use CR-RC n filter [21]. Such shaper principal schema is shown in Figure 2. A high-pass filter (HPF) sets the duration of the pulse by introducing a decay time constant. The low-pass filter (LPF), which follows, increases the rise time to limit the noise bandwidth. Although pulse shapers are often more sophisticated and complicated, the CR-RC n shaper contains the essential features of all pulse shapers, a lower frequency bound, and an upper frequency bound and it is basically a (n + 1) order band pass filter (BPF), where n is the lossy integrators number. The transfer function of an S-G pulse shaper consisting of one CR differentiator and n lossy integrators (Figure 2) is  given by [6] H(s) = sτ d 1 + sτ d where τ d is the time constant of the differentiator, τ i of the integrators, and A is the integrators dc gain. The number n of the integrators is called shaper order. Peaking time is the time that shaper output signal reaches the peak amplitude and is defined by τ s = nτ i . The order n or the peaking time τ s , depending on the application, can be predefined by the design specifications or not. The operating bandwidth of an S-G shaper is given by Most of the work done on pulse shaping filters is addressed on discrete systems using operational amplifiers as the basic active building block and not in integrated structures [24]. This is due to the fact that the main problem in the design of VLSI shaping amplifiers for nuclear spectroscopy is the implementation of long shaping times of the order of μs for which high value resistors (in the MΩ range) and/or capacitors (in the 100 pF range) are demanded. In fact, the practical values in terms of occupied area that can be integrated are in the tens of kΩ range for the resistors and in the pF range for the capacitors. However, considering the above shaper models, and using specific advanced filter design techniques, and transconductance circuits and current conveyors as the basic building cells, fully integrated SG shapers with long shaping times can be provided. Figure 3: third-order band pass RLC minimum capacitance two port filter representing a second-order S-G shaper. In order to design fully integrated shaper structures, advanced filter design methods were used [19,20]. The respective passive minimum capacitance third-order band pass filter RLC equivalent two port circuit and the signal flow graph (SFG) of a second-order current mode SG shaper are shown in Figures 3 and 4, respectively.
The output current of the RLC BPF describing the SFG is given below providing basically the respective transfer function of the RLC equivalent circuit of Figure 3, From the above SFG and using three advanced filter design methods the Leapfrog (LF) technique, the Ladder simulation method by element replacement, and the typical cascade filter technique with element replacement [25], three fully integrated current mode S-G shapers are designed using CCIIs and three respective structures using OTAs.
In order to calculate the values of the RLC two port equivalent passive elements and consequently the shaper passive elements, the total system transfer function should be studied in the time domain.
The total CSA second-order S-G Shaper system transfer function is given by where A pr is the preamplifier gain and τ pr is its rise time constant.
If the system input signal is a dirac pulse δ(t), by taking the inverse Laplace transform of the product, the output signal in the time domain is given by By solving the above integral, the output signal of the readout system is found, where k 1 , k 2 , k 3 , and k 4 are constants. Their values are given below: Using the above equations, the values of all shaper model passive elements (R, L, C) and consequently the final integrated shaper structure elements are selected in order to design shaper structures which would satisfy the respective peaking time specification.

CURRENT MODE S-G SHAPERS USING ADVANCED DESIGN TECHNIQUES
Six current mode second-order S-G shaper topologies were designed. The first three topologies were based on a second generation current conveyor (CCII) and the other three on an operational transconductance amplifier (OTA). All the configurations were designed for a specific low-energy Xrays strip detector (for a specified preamplifier rise time constant equal to 1.83 μsec, differentiator time constant equal to 1.5 μsec and integrators time constant of 0.5 μsec) [26] and provide an operating bandwidth (BW) of 230 kHz which respects to a peaking time equal to 1.7 μs. The passive element values of the RLC band pass filter of Figure 3 where the Leapfrog and the LC Ladder configurations are based, and provide the ideal ac response, are R s = 100 kΩ, R L = 100 kΩ, L 1 = 103.3 mH, L 2 = 74.4 H, and C = 11.71 pF.

CCII-based current mode shapers
Three second-order shapers are designed using the Leapfrog (LF), the Ladder simulation method by element replacement,

VLSI Design
CCII y x Figure 5: CCII-based LC ladder second-order S-G shaper using simulation by element replacement.
and the typical cascade filter technique. The basic circuit block of all three shapers is a second-generation current conveyor (CCII). Figures 5, 6, and 7 show the LC ladder shaper with simulation by element replacement, the leapfrog shaper, and the CCII cascade method shaper, respectively. In all the above CCII shaper systems, the same passive element simulator based on two CCII and one operational transconductance amplifier (OTA) is applied [25]. The passive elements and the OTA transconductances of all the above configurations are given in Table 1. The passive elements simulated value and the specific simulation topologies are shown in Table 2. Figure 6: CCII-based leapfrog second-order S-G shaper. Figure 7: CCII-cascade method second-order S-G shaper with inductor simulator.

OTA-based current mode shapers
Three respective current mode shaper structures were also designed using operational transconductance amplifiers (OTAs). Figures 8, 9, and 10 show the LC ladder shaper with  simulation by element replacement, the leapfrog shaper, and the OTA-based cascade method shaper (cascading of a differentiator and two lossy integrators), respectively, using only OTAs as the shaper building blocks. OTA-based inductance and capacitor boosting topologies are used in the cascade OTA shaper and the LF shaper, respectively [19].
The passive elements and the OTA transconductances of all the above configurations are given in Table 3. The respective OTA-based passive elements simulators [27,28] are given in Table 4.

SIMULATION RESULTS
All the above shaper implementations were designed in a 0.6 μm process by Austria Mikro Systeme (AMS). The power supplies are V dd = −V ss = 2.5 V. Simulations were performed using SPICE (BSIM3V3.2 MOSFET model, Level 49).

CCII-based current mode S-G shapers
A typical CMOS second generation current conveyor was designed in order to implement the above CCII based shaper structures. The respective CCII schematic is shown in Figure 11. This CCII structure can provide one or multiple outputs (inverting Z− and noninverting Z+) and consequently ensures a more flexible system design. The design concept of the second generation current conveyors that were used in the shaper implementations is clearly demonstrated 6 VLSI Design Figure 10: OTA-cascade method second-order S-G shaper with inductor simulator.  Figures 11(a) and 11(b), where the transistor level synthesis is given with the respective circuit symbol. The operational transconductance amplifier (OTA) is implemented using a CMOS configuration with a cascade structure ( Figure 12) [26].
The MOS dimensions of the OTAs and the CCII circuit which were used in the implementation of the CCII-based shaper structures are given in Table 5. The bias current I 0 in the CCII circuit was 50 μA and the bias voltages were V bias1 = 0.7 V and V bias2 = 0.3 V. The bias voltage of each OTA circuit was −1.5 V.
The CCII-based shapers have the same operating bandwidth (BW) at 230 kHz. Their frequency response is given in Figure 13.
The difference of the output current amplitude signal and in particular the lower gain of the LC Ladder and the Leapfrog structures is caused by the fact that the specific filter design methods reduce the output signal amplitude by half.
The total performance characteristics of each shaper are listed in Table 6.
The higher maximum bias current is observed in the CCII cascade shaper and the lower minimum in the CCIIbased LC ladder shaper and the CCII leapfrog shaper. The first two configurations appear to be low power in comparison to the cascade band pass filter. The third implementation, as the first one, provides a dynamic range equal to 35 dB.
Floating inductor Grounded capacitor in− in+ C eq = C g m1 g m2 g m3 g m4 Table 5: MOS dimensions of the OTAs and the CCII circuit.  Concerning the noise performance, the CCII leapfrog structure is the optimum since the output rms noise current is much lower in relation to the ladder shaper and the cascade one. The above characteristics, despite the fact that the same implementation is the worst in terms of the total harmonic distortion, render it suitable for applications where the DR is not required to be very high but the noise and power consumption limits are the main factors that determine the application as in the readout front ends. Figure 14 shows the signal-to-noise ratio of the three CCII-based shapers. As it can be seen, the Leapfrog configuration has the better SNR.    The total harmonic distortion (THD) of each CMOS CCII-based shaper topology is shown in (Figures 15-17).

OTA-based current mode S-G shapers
The same CMOS operational transconductance amplifier ( Figure 12) was also used in order to implement the OTAbased shaper structures. The bias voltage of each OTA circuit was also −1.5 V.
The MOS dimensions of the transconductance circuits that were used in the implementation of the OTA-based shaper structures are given in Table 7.
Their frequency response (BW = 230 kHz) is given in Figure 18.
The total performance characteristics of each shaper system are listed in Table 8.
The higher maximum bias current is observed in the OTA cascade shaper and the lower minimum in almost the same in all three configurations. All the shapers appear to be low power, but the LC ladder shaper provides the optimum power consumption performance. Additionally, the cascade and the LF structure provide a dynamic range equal to 22 dB, far lower than the 32 dB value of the LC ladder topology. Concerning the noise performance, all the structures appear to have low rms output noise, with the cascade shaper being slightly worse in comparison to the other two.  The above characteristics, and in relation to the fact that the LC Ladder architecture is the optimum in terms of the total harmonic distortion and the DR, render it as the most optimum among the other topologies. Figure 19 shows the signal-to-noise ratio of the three OTA-based shapers.
The total harmonic distortion (THD) of each CMOS OTA-based shaper topology, is shown in (Figures 20-22).

Comparison of CCII-and OTA-based S-G shapers
In Figure 23, a comparison between the OTA-based shapers and the CCII shaper topologies is clearly shown. As it is obvious, the OTA-based shaper structures appear to be more advantageous in comparison to the CCII ones. The main differentiation is shown in the total harmonic distortion and in the power consumption performance. In particular, the OTA shaping structures provide much lower power consumption and distortion levels in comparison to the CCII topologies.
Considering the above advantages and in relation to the fact that in the OTA shaper topologies no resistors are used, the OTA structures seem to be the optimum selection.

CONCLUSIONS
In this paper, a detailed examination of current conveyor and operational transconductance amplifiers-based semi-Gaussian shapers suitable for readout applications is performed. Specifically, respective current mode shaper structures of each kind are proposed to be used in front-end applications. All shaper implementations are designed using advanced filter design methods such as the Leapfrog and the Ladder LC technique by element replacement. The shapers used in this work provide large peaking time, however they are fully integrated configurations and not discrete systems. A CMOS CCII and an OTA circuit were designed in order to be used in the implementation of the above shapers. The filter configurations are analytically compared in terms of power consumption, total harmonic distortion, dynamic range, and noise performance. The CCII Leapfrog architecture is proved to be the optimum among the CCII-based shapers according to the output noise, SNR, and consumption and on the other hand, the OTA LC Ladder architecture seem to be the more suitable in the OTA topologies, considering the output noise, SNR, power consumption, and total harmonic distortion. Although both categories of topologies, and the CCII and the OTA structures provide satisfactory performance, the OTA based shapers seem to be the more optimum selection considering the power consumption performance and the total harmonic distortion.