Figure-of-Merit-Based Area-Constrained Design of Differential Ampliﬁers

A new methodology based on the concept of ﬁgure of merit under area constraints is described for designing optimum performance di ﬀ erential ampliﬁers. First a ﬁgure of merit is introduced that includes the three performance parameters, namely, input-referred noise, di ﬀ erential dc gain, and unity-gain bandwidth. Expressions for these parameters have been derived analyti-cally and ﬁnally arrived at an expression for the ﬁgure of merit. Next it is shown how these performance parameters vary with the relative allocation of the total available area between the input and load transistors. The ﬁgure of merit peaks at a certain value of relative area allocation in the range of 60% to 80% of the available area to the input transistors. The peak value of ﬁgure of merit is a function of area. However, it is independent of biasing current (and, therefore, power consumption) subject to the minimum current (and, therefore, a minimum power) required to keep all the transistors biased in the saturation region. The peak ﬁgure of merit and minimum power required to achieve the peak ﬁgure of merit are also plotted as a function of area. These analyses help in synthesizing optimal di ﬀ erential ampliﬁer circuit designs under area constraints.


INTRODUCTION
The first stage of an operational amplifier and several types of comparators is typically a differential amplifier that needs to provide sufficient gain and bandwidth while introducing as little noise as possible. Moreover, if this is desired with a constraint on area, the problem becomes more difficult. The classical noise optimization techniques for low noise amplifier (LNA) design presume a device given with fixed characteristics, and thus offer no explicit guidance on how to best exercise the IC designer's freedom in tailoring device geometries under the constraints of area [1].

CONCEPT OF FIGURE OF MERIT
To compare different solutions for an analog circuit design, first a figure of merit must be agreed upon. One of the key issues is the design of a circuit with maximal figure of merit under constraints of area. Here, a figure of merit has been proposed that takes into account the three key perfor-mance parameters, that is, the differential dc gain, unity-gain bandwidth, and input-referred noise. The proposed figure of merit in this paper is given by where UGB is the unity-gain bandwidth, Ad is the differential dc gain, and IRN is the peak input-referred noise spectral density; the differential amplifier is illustrated in Figure 1.

Noise model for MOST
Each semiconductor device in the circuit introduces noise. Various types of noises that could be possible in a device are shot, thermal, flicker (1/ f ), avalanche, burst, and so forth. At low frequencies, flicker (1/ f ) noise dominates all other noises. Therefore, here only flicker noise has been considered to introduce the concept developed. There exist numerous models for flicker noise in the MOS transistor [2][3][4][5][6][7][8][9][10]. In accordance with the most popular model [10], the flicker noise due to a MOS transistor can be lumped as a voltage source at the gate and is given by in the noise bandwidth of Δ f at frequency f . W eff and L eff are the effective width and length of the gate of the MOS transistor, K F is the flicker noise coefficient for the MOS transistor, and C OX is the gate capacitance per unit area. However, the overall circuit noise depends on the circuit configuration.

Input-referred noise
For the differential amplifier shown in Figure 1, there are four voltage noise sources connected at the gate of each transistor. If all these sources are lumped together at the gate of transistor M1, the mean-square value of the equivalent noise voltage source at input (gate of M1) for the total circuit noise is given by where V 2 eq1 , V 2 eq2 , V 2 eq3 , V 2 eq4 are the noise sources at the gates of transistors M1, M2, M3, and M4. g mi and g ml are the transconductance of the input (M1 and M2) and load (M3 and M4) transistors, respectively, and are given by where W i , W l , L i , and L l are the widths and lengths of input and load transistors, respectively, k n and k p are the process transconductance parameters for n-channel and p-channel MOS transistors, and I o is the tail current of the differential amplifier.
Using (2), (3), and (4), the power spectral density of noise at the gate of M1 is written as Therefore, root-mean-square value of spectral power density better known as input-referred noise at frequency f is written as

Unity-gain bandwidth
Unity-gain bandwidth of the circuit, UGB, is given by as C L is the total load capacitance at the output node.

Differential dc gain
The differential dc gain, Ad, of the differential amplifier is given by where g di and g dl are the drain to source conductance of input and load transistors, respectively. The drain to source conductance g d is approximated as where (dx d /dV DS ) (known as channel-length modulation parameter) is a process parameter [11], and its value has been taken as 0.1 μm/V for NMOS and 0.05 μm/V for PMOS transistors.

Figure of merit
Substituting the values of UGB, Ad, and IRN from (6), (7), and (8) in (1), we get the following: A. Agarwal and C. Shekhar

MAXIMIZATION OF FIGURE OF MERIT UNDER AREA CONSTRAINTS
If A is the total area available for the devices in the differential amplifier, then let us assign x% of A, that is, x·A to the input transistors and (1−x)·A to load transistors. Then, writing the expressions for UGB, Ad, and peak IRN (at f = 1) in terms of x, area (A), bias current (I o ), and technology parameters, we get Hence, from (1) and (11) From (12), the following conclusions can be drawn. (v) Length of load transistor L l should be as large as possible under the constraints of area since it maximizes the last two product terms and hence maximizes figure of merit FoM. Figure 2 shows the variation of differential dc gain as a function of relative area allocated to input transistors at different values of total area. It is clear that as the total area increases, the differential dc gain increases. But it does not keep on increasing with the increase in input transistors area. The peak value of dc gain is obtained for x in the range of 0.6 to 0.8. Figure 3 shows that the unity-gain bandwidth is a monotonically increasing function of x.

ANALYTICAL RESULTS
The variation of peak value of input-referred noise as a function of x is shown in Figure 4. For larger values of x, the noise is reducing because with increasing x, the gate area of input transistors is increasing and their noise contribution is decreasing. But it is interesting to note that it starts increasing beyond a point for all the values of A. It implies that beyond this point, the contribution of noise from load transistors over and above the contribution of input transistors increases. Next the figure of merit is plotted as a function of percent area allocated to input transistors. Figure of merit is a peaking function of x in the range 60% to 80% as shown in Figure 5. It is clear that figure of merit increases with total area A. It also indicates that for a fixed value of total area, about how much percent of total area should be assigned to input transistors to obtain a maximum value of figure of merit. Peak value of figure of merit as a function of total area is plotted in Figure 6. The value of figure of merit is independent of bias current I o . However, a minimum value of power is essential to keep all the transistors in saturation. Figure7 shows the minimum bias current required for keeping all the transistors in the circuit in saturation region (and in strong inversion) as a function of total area. It implies that for a given area, a minimum power has to be provided. To increase the figure of merit, area increase alone is not enough; more power is also required to keep the transistors in saturation.

SIMULATION RESULTS
Simulations using Tanner Tools Pro also validated the analytical results. To perform this task, a value of total area was chosen. The total area was divided between input and load transistors in a predefined ratio. Then, for this distribution of areas, all combinations of aspect ratio of input and load transistors were simulated to obtain the differential dc gain, unity-gain bandwidth, and peak value of input-referred noise. The figure of merit was computed from these parameters. The peak figure of merit as a function of input transistor area in percent (ratio of area allocated to input transistors to the total available area A) for various values of total area is plotted as shown in Figure 8. This plot matches well with the analytical results shown in the previous section.   In order to demonstrate the utility of figure of merit as a tool to optimize the design, we define three new parameters as follows: Ad% is the differential dc gain at peak figure of merit as a percentage of maximum differential dc gain achievable for a given area;   UGB% is unity-gain bandwidth at peak figure of merit as a percentage of maximum unity-gain bandwidth achievable for a given area; IRN% is input-referred noise at peak figure of merit as a percentage of minimum input-referred noise achievable for a given area.
A. Agarwal and C. Shekhar   Table 1 compares the analytical and simulated values of peak figure of merit, Ad%, UGB%, and IRN% for constant area. In most cases, value of Ad% is more than 95%, and the value of UGB% is more than 91%. IRN% is less than 101% in all cases.

CONCLUSION
The concept of figure of merit is a suitable tool for synthesizing optimal design of differential amplifiers under area constraints and leads to the realization of differential dc gain, unity-gain bandwidth, and input-referred noise values that are also very close to their individually achievable maximum values under the same area constraints. The above analyses validate that the idea of FoM may be deployed in a CAD tool for automatically synthesizing the differential amplifiers and can be extended for many other building blocks for low frequency applications. The paper also highlights the dependence of peak figure of merit and the minimum power required to achieve it on the area available for the circuit.