A 3 . 22 – 5 . 45 GHz and 199 dBc / Hz FoMT CMOS Complementary Class-C DCO

This paper implements a complementary Class-C digitally controlled oscillator (DCO) with differential transistor pairs. The transistors are dynamically biased by feedback loops separately benefiting the robust oscillation start-up with low power consumption. By optimizing three switched capacitor arrays and employing fractional capacitor array with sigma-delta modulator (SDM), the presented DCO operates from 3.22GHz to 5.45GHz with a 51.5% frequency tuning range and 0.1 ppm frequency resolution. The design was implemented in a 65 nm CMOS process with power consumption of 2.8mA at 1.2 V voltage supply. Measurement results show that the phase noise is about −126 dBc/Hz at 3MHz offset from a 5.054GHz carrier frequency with the 1/f3 corner frequency of 260KHz.The resulting FoMT achieves 199.4 dBc/Hz and varies less than 2 dB across the frequency tuning range.


Introduction
Combining the high spectral purity, wide FTR, and low power consumption is still one of the most challenging targets in the design of frequency synthesizers, especially for the cellular GSM/WCDMA/LTE applications.In recent years, ADPLLs are deeply researched and widely used in cellular applications because of their downscaled area, low power consumption, and improved phase noise performance in advanced CMOS technology [1,2].DCO is one of the most challenging design blocks because good phase noise performance should be ensured with low power consumption and it needs to satisfy the wide FTR and high-frequency resolution simultaneously in ADPLL.
Compared with traditional LC-tank oscillators, the differential transistor pairs based Class-C oscillator delivers briefer and taller pulses and maximizes the output oscillation amplitude, which leads to a minimization of the phase noise [3].It means that the phase noise can be improved theoretically with the same current consumption.
This paper implements a wide FTR and high FoMT Class-C DCO based on 65 nm 1P9M CMOS process.Two feedback loops ensure the robust oscillation start-up of DCO [4,5], which is achieved by adjusting the DC biasing voltage of the differential transistor pairs synchronously reducing power consumption.The FTR and frequency resolution of the presented DCO are improved and optimized by employing the three capacitor arrays and the fractional array with SDM.
The remaining paper is divided into three parts.Description of the presented complementary Class-C DCO is given in Section 2 and measurement results are shown in Section 3. Conclusion is described in Section 4.

Complementary Class-C DCO
2.1.Architecture Description.Figure 1 shows the complementary Class-C DCO architecture.Two cross-coupled pairs  1 / 2 and  3 / 4 provide negative resistance to recover the energy losses in the resonant load.The current mirror is made up of  1 / 2 and  1bias / 2bias to provide the dc current bias, and it also has a high enough transconductance initially by using the negative feedback to ensure a robust start-up oscillation.Moreover, in steady state, the bias voltage  BN falls from its start-up value which maximizes the output swing [4]. 5 works as a level shifter to provide dc bias voltages  BP and   through the common-mode negative feedback.LC-tank is composed of a tapped inductor and three capacitor arrays.
For coarse array,  DCO C is proportional to the inductor value , Δ, and the cube of  CKV as shown in (2): Equation ( 3) gives the -domain open loop transfer function of ADPLL [2],  and  are loop parameters,   is reference clock, and KDCO is the normalized gain of DCO.In coarse array,  DCO C changes 4.85 times (≈(5.45/3.22) 3 ) across the entire FTR, and ADPLL's  ol () also changes with  DCO C as (3), which will result in instability of ADPLL loop.Therefore, varactors with different Δ value are adopted at different frequency points realizing a constant  DCO C to ensure the loop stability.
For LC-DCO, the  th  DCO C and the ( + 1) th  DCO C can be calculated by (4), where Δ −1 , Δ  , and  are the  th Δ, the ( + 1) th Δ, and all the capacitors of the coarse array, respectively.In order to get constant  DCO C ,  DCO, should be equal to  DCO,+1 , which means From ( 5), it can be concluded that the linearity of  DCO C only depends on Δ  /.Finally, the coarse array is designed according to (2)∼(5) with constant 24 MHz/LSB's  DCO C which is equal to the reference clock 24 MHz.89 varactors make up the coarse array to cover the wide FTR and they are decoded from 7 bits coarse oscillator tuning word (OTW), as shown in Figure 1; the postfixes C, M, FI, and FF are, respectively, the OTW of coarse array, medium array, integral fine array, and fractional fine array.
For the wide FTR application, the coarse array has the varactors with the biggest Δ in the resonant tank.For PMOS varactor shown in Figure 2, the relevant parasitic capacitance can be classified into three parts as shown in Figure 2: (1) the oxide layer capacitance between gate and channel:  1 =  OX , where  OX is the capacitance of gate oxide layer per unit area and  and  are the gate width and gate length, respectively; (2) the depletion layer capacitance between substrate and channel:  2 = √ si  nwell /(4  ), where  is a charge constant,  si is the dielectric constant of silicon,  nwell is the doping concentration of N-well, and   is the built-in potential; (3) the overlapping capacitance among gate, source, and drain:  3 and  4 equal to  OV , where  OV is the overlapping capacitance per unit width.
Therefore, when the PMOS varactor operates in inversion region, capacitance is maximized to  max .When the PMOS varactor operates in depletion region, capacitance is minimized to  min .
So the capacitance ratio is Because  OV > √ si  nwell /(4  ),   increases when  is increased, and higher   means the wider FTR.
When PMOS varactor operates in depletion region, channel is not formed; the parasitic resistance only includes gate resistance   and metal contact parasitic resistance of source and drain   , so the  value of PMOS varactor in depletion region is However, when the PMOS varactor lies in inversion region, the  value can be inferred from [9] as the following equation shows: In ( 8),   is the gain factor of PMOS transistor,  GS is the voltage difference between gate and source, and Tp is the threshold voltage for PMOS transistor.It can be concluded that  inv is inversely proportional to the square of .
Therefore, the  value, symmetry, and   are mainly determined by the coarse array.For the coarse array, it is difficult to trade off the  value and the region of FTR.Finally, the channel length of the coarse array is set to 600 nm.As shown in the postsimulation in a 65 nm CMOS process, the  value is higher than 25 and the   is about 7.Both of them satisfy the phase noise and the FTR requirements.
However, for the medium and fine array, frequency resolution is the most important design factor.200 nm and 60 nm channel length are chosen, respectively, for high-frequency resolution and high  value.Both of them are composed of unit cap array because their FTS varies a little with the change of frequency and these two arrays' FTS have little effect on the loop stability of ADPLL.The FTR of medium and fine arrays should respectively cover several LSBs of coarse and medium arrays so that the OTW of current array will not overflow due to the process, voltage, and temperature (PVT) variations.In the process of ADPLL locking, OTW overflow means that medium tuning or fine-tuning period cannot be finished and loss-of-lock may occur.According to the possible largest frequency error due to PVT variations and the required frequency resolution of the current locking period, 6-bit medium arrays and 7-bit fine arrays are designed to cover 4 LSBs of  DCO C and 8 LSBs of  DCO M , respectively.Finally, the locking process of ADPLL can be divided into three frequency locking periods step by step without the possibility of loss-of-lock due to OTW overflow.
In order to improve the phase noise performance of the DCO, MOS varactor is controlled digitally.As shown in Figure 3, OTW (Oscillator Tuning Word) is decoded into the thermal code to control the on/off states of MOS varactor with an inverting driver.The voltage level of digital control signal   can be adjusted by  High and  Low .Figure 3 also shows the curve of a PMOS varactor capacitance versus  GS (C-V curve).MOS varactors change linearly from  1 to  2 and  0 is the output amplitude of DCO.During the whole oscillation period, the original C-V curve has to be transferred into the average C-V curve with red dashed dotted line as shown in Figure 3. Therefore, in order to stop the PMOS varactor from inducing the noise on the   , the varactor must be working in the on/off states region of the average C-V curve.Off-state The finite frequency tuning resolution introduces the quantization noise and contributes the output phase noise of the ADPLL and hence a small tuning step is desired.The frequency resolution requirement is 0.1 ppm, but the smallest FTS is limited by the smallest Δ in 65 nm process.Figure 4 compares the phase noise contribution among MASH 1, MASH 1-1, and MASH 1-1-1 SDM; it can be seen that MASH 1-1-1 SDM has the lowest in-band phase noise contribution and the best noise shaping character.Moreover, their out-band phase noise contributions are almost the same.Therefore, 10bit OTW FF is dithered with MASH 1-1-1 SDM to control 6-bit fractional capacitor arrays to improve the frequency resolution and decrease the noise contribution.The phase noise contribution of SDM to ADPLL is simulated with MATLAB as shown and it is below −150 dBc/Hz, which means it affects in a small way the whole phase noise performance.In Figure 5, Eq 1 (), Eq 2 (), and Eq 3 () are the quantization noise of each accumulator.Therefore, the output frequency of SDM can be deduced from Voltage (V)

Class-C DCO's Negative Feedback Loops.
In Figure 1, current  BP is chosen to bias  5 providing a level shift voltage.A RC network is used to provide a dc bias voltage, and  BP is higher than the tank common-mode voltage, which permits a larger resonator swing before the  3 / 4 is pushed into the triode region.This is the same technique employed to bias the  1 / 2 .Moreover, a high RC constant of the RC biasing network is used to low-pass filter the noise introduced to  BN and  BP , optimizing the phase noise [5]. tail not only integrates the difference between  BN and the current exhausted by the DCO but also filters the high-frequency noise contribution from  1bias / 2bias , improving the phase noise [4].
The simulated transient voltage of DCO is given in Figure 6   Referring to the noise analysis in [10], the proposed DCO's noise from feedback loop can be inferred in (10), where V 2   , V 2  0 ,5 , and V 2   are, respectively, the white noise voltage power spectral density by bias resistor   , bias MOSFET  5 , and bias MOSFET  1bias / 2bias .  is the single pole in the feedback loop.The  2 nl (  )Γ 2 osc (  ) is the amplification and frequency translation that the feedback loop noise must undergo first.
Therefore, the total amount of phase noise can be deduced in (11) where  is Boltzmann constant,   is the absolute temperature in Kelvin,  is the capacitor in LC resonant bank,  OSC is the oscillation amplitude of DCO, 2R is the parasitics losses, and  is the technology coefficient. cp ( OSC ) and  fl ( OSC ) are, respectively, weighing factors of cross-coupled MOSFETs and feedback loops.

Measurement Results
The Class-C DCO was fabricated in a standard 65 nm CMOS process.Figure 7 [2,[6][7][8].Without the SDM, this DCO has achieved the frequency resolution of 120 KHz, which is close to other references, but it can be 117 Hz after SDM.Reference [8] is also a complementary Class-C DCO, but this work has better performance than it.Reference [6] is traditional LC-DCO; this work shows higher FoM than it due to its Class-C mode.This design works at close frequency with [6][7][8] while displaying wider FTR and better FoMT due to the design and optimization of capacitor arrays.

Conclusion
This paper presented a complementary Class-C digitally controlled oscillator (DCO) with differential transistor pairs.With three optimized capacitor arrays and a fractional array dithered by SDM, the DCO works from 3.22 GHz to 5.45 GHz with 51.5% FTR and less than 0.1 ppm frequency resolution.Through two feedback loops, the start-up oscillation is ensured and low power consumption is realized.The achieved phase noise is −126 dBc/Hz at 3 MHz offset from 5.054 GHz with the 1/ 3 corner frequency of 260 KHz while consuming only 2.8 mA at 1.2 V voltage supply.The final FoM and FoMT are 185.2dBc/Hz and 199.4 dBc/Hz, respectively.

−Figure 8 :
Figure 8: Measurement results of phase noise @ 1 MHz offset versus Coarse Code (a) phase noise of Class-C DCO at 5.054 GHz (b) and frequency spectrum with/without SDM (c).

Figure 9 :
Figure 9: Measurement results of frequency range and frequency step of coarse array.

Figure 10 :
Figure 10: Measurement results of frequency range and frequency step of medium array (a) and fine array (b).
offers the die photo of Class-C DCO; it occupies the area of 0.21 mm 2 without PADs.Figure8(a)shows that the different phase noise measurement results in 1 MHz frequency offset at the different resonant frequency, which changes with coarse array code from −118.3 dBc/Hz to −114.8 dBc/Hz.The phase noise measurement results of Class-C DCO with SDM and without SDM at 5.054 GHz are shown in Figure8(b); the 1/ 3 corner frequency is about 260 KHz.Although brings spurs, it can be seen that the phase noise performance with SDM is still better than the phase noise performance without SDM.With SDM, it is −116 dBc/Hz and −126 dBc/Hz at 1 MHz and 3 MHz frequency offset, respectively.Figure8(c)shows the frequency spectrum of DCO at 3.34 GHz; it can be seen that SDM brings spurs about 10 dBc at point 3 and point 4 on the frequency spectrum of DCO, but it can be suppressed by the loop character of ADPLL.Figure9shows that the frequency and  DCO C change versus the coarse array code.The measured  DCO C is around 24 MHz/LSB with a maximum deviation of 1.64 MHz/LSB.Figure10(a) displays the  DCO M at different frequency points, the red line and the blue line show the  DCO M at 3.32 GHz and 5.45 GHz, respectively, and  DCO M  DCO F will be divided by 210, so the final frequency resolution varies from 117 Hz to 444 Hz, which is less than 0.1 ppm.When all the varactors change from on-state to off-state, the DCO will work from 3.22 GHz to 5.45 GHz, with the FTR of 51.5%.Table1shows the comparison table of state-of-the-art LCtank oscillators changes from 1.5 MHz/LSB to 7.4 MHz/LSB across the whole FTR because  DCO M is proportional to the cube of  CKV as (2) shows.Figure 10(b) gives the  DCO F at different frequency points, and it changes from 120 KHz/LSB to 455 KHz/LSB through the whole FTR, with the same reason of  DCO M .After 10-bit SDM, fractional array's frequency resolution

Table 1 :
Comparison with the state of the art.