Techniques for Self-Checking Combinational Logic Synthesis

This paper presents techniques for designing arbitrary combinational circuits so that any single stuck-at fault will result in either single bit error or unidirectional multibit error at the output. If the outputs are encoded using Berger code or m-out-of-n code, then the proposed technique will enable on-line detection of faults in the circuit. An algorithm for indicating whether a certain fault at an input will create bidirectional error at the output is presented. An input encoding algorithm and an output encoding algorithm that ensure that every fault will either produce single bit error or unidirectional multibit error at the output are proposed. If there are no input fault which produces bidirectional error, no internal stuck-at fault will result in such an error irrespective of the way the circuit is implemented. Thus, only single bit or unidirectional multibit error will result in the presence of a fault in the circuit. The proposed techniques have been applied to MCNC benchmark circuits and the overhead is estimated.


I. INTRODUCTION
ith the increase in the complexity and density of VLSI chips, transient/intermittent faults have emerged as the dominant failure modes in VLSI circuits [1][2].Conventional off-line testing schemes do not detect transient faults since the detection of these faults requires continuous monitoring of the outputs; i.e. the circuits have to be self-checking.A self-checking circuit usually consists of a functional block that generates the encoded outputs, and a checker that checks the validity of the outputs [3][4][5].Self-checking circuits that use m-out-of-n code [6] or Berger code [7] for output encoding, detect stuck- at faults that cause single bit error or unidirectional multibit error.Designing logic circuits such that any stuck at-fault causes single bit error or unidirectional multibit error is a challenging problem.Previous work either use PLA structure, or perform algebraic factorization for two-level networks by restricting the use of inverters at the inputs and using only AND/   OR gates [8][9].Also, it is assumed that all input lines and their inversions are fault free.In [14], monotone functions and inverter free realization were used to design strongly fault secure logic net- works.Similarly, inverter free realizations were used in [15] for the design of strongly fault secure and strongly code disjoint circuits.The restriction on the type of gates and on synthesis procedures used for logic circuits usually increases the area overhead.In this paper, we propose techniques for designing bi- directional error-free combinational circuits based on input encoding and output encoding schemes that do not restrict the way the circuit is implemented.The output encoding strategy does not form code- words as used in conventional coding techniques.Our intention here is to design the functional part of a self-checking circuit such that any single stuck- at fault will create either single bit error or unidi- rectional multibit error.Thus by incorporating ad- ditional check bits, the output of the functional block can be designed to be a single and unidirectional error detecting code; e.g., Berger code and m-out- of-n code.
The techniques presented in this paper can be di- rectly applied to logic circuits described in the PLA format, where symbolic representation is used for the inputs or the outputs or both; i.e., the inputs or the outputs have not been assigned any binary codes.The aim of this paper is to encode the inputs or the 210 FADI BUSABA and PARAG K. LALA outputs so that any single stuck-at fault can only create single bit error or unidirectional multibit error at the output.Thus, these techniques will be useful only if self-checking is considered at the design level i.e., before the circuit is actually implemented.
Preliminaries and definition are given in section 2.
In sections 3, an algorithm for detection of faults that might cause bidirectional error at the outputs is presented.An input encoding algorithm and an output encoding algorithm are presented in section 4. A detailed example is given at the end of section 4 where the input and output encoding algorithm are applied to a benchmark circuit.A VLSI implemen- tation of each technique is provided, and the area overhead is estimated.The proposed techniques have been applied to MCNC benchmark circuits, and the results are reported in section 5.

PRELIMINARIES
Before presenting the proposed algorithms, we need to consider the following definitions.
Definition 1" A variable is a symbol representing a single coordinate of the boolean space (e.g.a).
Definition 2: A lierai is a variable or its negation (e.g. a or a').
Definition 3: A cube is a set C of literals such that if x belongs to C, then x' does not belong to C. Definition 4: A minlerm is a cube with only 0 and 1 entries.
Definition 5: A function is unale if in its minimal sum-of-products expression each variable appears either in a complemented form or in an uncomple- mented form but not in both.
Definition 6: The dist(C, C2) where C and C are different input cubes, is the number of bit positions in which they differ when these bit positions are either l's or a O's, but not don't cares.For example dist(C, C2) where Cl(abcd) 1010 and Ca(abcd) -110, equals to one because the two input cubes differs only in position b.Definition 7: Two output vectors O1 and O2 are par- tially bidirectional if there exist at least two outputs bits which are 10 in O1 and 01 in O2 or vice versa.
For example, O 1100 and O2 0101 are partially bidirectional whereas O 1000 and O2 1111 are not.
Definition 8: Two output vectors Oi and O are ad- jacent if dist(Ci, Ci) 1, where C and C are the input cubes corresponding to O and O respectively.Definition 9: Two input cubes Ci and C are bidirec- tionally adjacent if their corresponding outputs, Oi and O i, are partially bidirectional.Definition 10: Two input cubes are called m-bidirec- tional if they only differ in position m and their cor- responding outputs are partially bidirectional.For example, input cubes C1 and C3 in Table I are a- bidirectional.Definition 11: Bidirectionality set of two bidirection- ally adjacent cubes is the set that contains all the variables in which the two cubes differ.For example, the bidirectionality set of C and C2 in Table I is {b, c} since they differ in positions b and c.Definition 12: The num_inv(nl, n2) is the number of inversions on the path from nl to n2 modulo 2, where nl and n2 are two nodes inside a digital circuit.Definition 13: A fault f creates a unidirectional error if the correct and the faulty outputs are not partially bidirectional.Definition 14: An undirected graph G containing the set of vertices V and the set of edges E is denoted by G(V, E).G'(V', E') is a subgraph of G if V' is a subset of V, and an edge joins two vertices in G' if an edge joins the same two vertices in G.A fully connected subgraph of G is a graph G(V, E) such that V is subset of V, and any two vertices in G are connected by an edge.A graph G(V, E) covers graph G2(V2, E2) if the following are satisfied: (i) the number of vertices in E, is equal to or greater than the number of vertices in E2.
(ii) if there exists an edge between two nodes in V2, there should be also an edge between the same two nodes in V.
Definition 15" A graph, Gm, containing 2 m vertices is unidirectional graph iff (i) each vertex is uniquely represented by an m- bit number.
(ii) any two vertices are connected if they are not partially bidirectional.
The following definitions are taken from [12].Definition 16: A controlling value at a gate input is the value that determines the value at the output of the gate independent of the other inputs.For ex- ample, 0 is a controlling value for an AND gate.A noncontrolling value at a gate input has no effect on  the output of the gate.For example, 1 is a noncon- trolling value for an AND gate.
Definition 17: A path is in a combinational circuit consists of connections and gates, where connection connects gate (i 1) and gate i.In other words, an input to gate is the output from gate (i 1).
The inputs to a gate other than the output from gate (i 1) are called side inputs.Definition 18: A path is said to be statistically sen- sitizable if there exists an input cube that sets all side inputs to noncontrolling values.Definition 19: An event is the transition from 0(1) to 1(0).Definition 20: A primitigve gate is prime is none of its inputs can be removed without causing the re- suiting circuit to be functionally different.A gate is irredundant if its removal causes the resulting circuit to be functionally different.A gate-level circuit is said to be prime if all the gates are prime and irre- dundant if all the gates are irredundant.A gate-level circuit is prime and irredundant if and only if it is 100% testable for all single stuck-at faults [13].

DETECTION OF BIDIRECTIONAL FAULTS AT INPUT LINES
A fault at a node f results in unidirectional error at the outputs if the number of inversions from the fault site to the outputs is the same; in other words, num _inv(f, oi) is the same, where oi is an input line that is affected by f.
The following two lemmas identify the existence of bidirectional error due to a fault on an input line, and how to eliminate such errors.Lemma 1: If there exist two x-bidirectional input cubes, then a fault at input x may create a bidirec- tional error at the output.
Proof: Suppose cubes C and C2 are x-bidirectional, then C and C2 differ only in variable x and the out- puts corresponding to C and C2 i.e., O and 02, are partially bidirectional.Therefore, if C is activated, a fault at input x may activate C2 instead of C pro- ducing 02 instead of O, thus creating a bidirectional error.Q.E.D. Lemma 2: If no two input cubes are x-bidirectional, than a fault at an input line will always produce a unidirectional error.
Proof: If no x-bidirectional input cubes exist, then either (1) the distance between all bidirectionally ad- jacent input cubes is zero or greater than or equal to two, or (2) any adjacent outputs are not partially  bidirectional.For case (1), no fault at an input line will activate cube Cj instead of Ci where Ci and Cj are m-bidirectional; thus every fault results in uni- directional error at the output.For case (2), a fault at the input may activate C instead of Ci.Since the outputs corresponding to C and Cj are not partially bidirectional, the fault results in unidirectional error at the output.Q.E.D. [5] The following algorithm identifies which faults at the input lines might cause bidirectional error at the output.
Algorithm 1" 1.For every possible output O in a circuit, group all other outputs that are partially bidirectional with O.
2. For an output O in the group, find dist(Ci, Ci) where Ci is the cube corresponding to Oi, and C is a cube corresponding to O i. 3.If dist(Ci, Ci) equals to 1 and the two cubes differ in variable x, then add (Ci, C i, x) to the set of possible bidirectional faults.To illustrate the application of the algorithm, let us consider the truth Table description of a Full Ad- der shown in Table II.
The element (C,, C5, B) indicates that cubes C, and C5 are B-bidirectional; i.e., if C is applied to the circuit and input B gets stuck-at-i, then the input will correspond to C5, which will result in the output 01 instead of the fault free output 10.

TECHNIQUES FOR BIDIRECTIONAL ERROR ELIMINATION
Preventing faults at the input lines of a circuit from causing bidirectional error at the output can be guar- anteed by 'properly' encoding the inputs or the out- puts.The input or output encoding should be done such that no two input cubes become m-bidirectional, thus eliminating the possibility of bidirectional error at the output.(Lemma 2).We will first describe the input encoding strategy.

Input Encoding
The input encoding strategy assigns codes to two bidirectionally adjacent inputs cubes, Ci and C i, such that dist(Ci, Ci) is either >-2, or equal to 0. We consider the two cases separately.Case 1: In this case, C and C are coded such that dist(C, Ci) >-2.Consider a digital circuit with I different input symbols and O encoded outputs.The steps required to satisfy the distance requirement are" 1.For each possible input cube in a circuit, group all other input cubes that are bidirectionally adjacent. 2. Assign codes with distance greater than or equal to 2 for any bidirectional adjacent input cubes by using minimum number of encoding bits.
If the assignment is not possible, increase the number of encoding bits by one and repeat step 2.
Consider the example shown in Table III in which each input cube is bidirectionally adjacent with four other cubes.Steps 1 and 2 suggest that cubes C, C2, C3 and C4 have to be at a distance greater than or equal to two from cubes C5, C6, C7 and C8.This can be illustrated with a graph (Figure 1) which is con- structed with input cubes as vertices, and with an edge connecting two vertices if they are bidirection- ally adjacent.Thus the distance should be greater than or equal to 2 for any vertices joined by an edge.
If minimum number of bits for encoding is used and C is assigned to 000, then cubes C5, C6, C and Cs have to be coded as 101, 110, 011 and 111 respectively.Consequently, any code for C2, C3 or C4 will have a distance of one from their bidirectionally ad- jacent cubes which conflicts with the constraint in step 2. If four bits are used to encode the input, one possible input coding is: 0000 If the cubes are encoded in this manner, cubes C1, C2, C3 and C4 can be reduced to the cube 0--0, and similarly cubes C5, C6, C7, and C8 can be reduced to 1--1.Therefore, any fault at the input will result in unidirectional error at the output.
An alternative approach for input encoding is to use m-out-of-n codes since the minimum distance between any two codes is two.In addition, they are easily implemented without significant increase in the number of input lines.
Case 2: In this case, C and C are coded such that o2 dist(Ci, Ci) O. Let us assume two x-bidirectional 0 input cubes, Ci and C i, where the variable x is 0 in 0 C and 1 in C i. Encoding the input by adding one 0 more line for the variable x such that it is represented 0 by -0 in Ci and by 1-in C will make dist(C Ci) O. In the proposed input encoding strategy, a 0 and a 1 in the input cubes are replaced by -0 and 1- respectively.Consider for example two a-bidireco tional input cubes C1 (abcd) 1010 and C (abcd) 0010.Since a is a 1 in C and 0 in C2, the new input encoding, Cl(aalbcd) 1-010 and C2(aalbcd) -0010, will guarantee that dist(C1, C2) is zero, and thus the fault at input a that might cause bidirectional error at the ouput is eliminated.It is important to note that input variable a (a) appears either as a don't care '-' or as a 1 (0) in the input cubes.If for every input variable x, there exist at least two x- bidirectional input cubes, the number of input lines will be doubled because x will be replaced by two inputs x and x.Thus, in the worst case, this strategy doubles the number of input lines.In such a situa- tion, every input variable will be either present as a 0 or 1 but not both in the input cubes.
In addition, this encoding process may result in x- bidirectional input cubes even in the absence of x- bidirectional input cubes in the original specification.
For example, in Table I, C and C3 are a-bidirec- tional, and cubes C and C2 are bidirectionally ad- jacent with their corresponding bidirectionality set {b, c}.To make dist(C, C3) zero, one more input variable is added such that C1 -0101, C2 -0011 and C3 1--01.In this case, cubes C1 and C2 become c-bidirectional; that is because the bidirectionality set of C and C2 was {a, c} and by replacing a with -0 and 1in C and C2 respectively, variable a can be taken out from the set.
The input encoding algorithm proposed below sat- isfies the distance requirement.{ increase the number of input encoding bits by one as follows: substitute in all cubes the location of x by 1if it is a 1, by 0-if it is a 0 and by if it is a-(don't care).} } until there is no x-bidirectional cubes.
After applying algorithm 1 to the circuit descrip- tion of Table II, another circuit description, Table IV, is derived with different input encoding.
The new input encoding doubles the number of variables but keeps the number of literals unchanged.In this case, the output equations are: 0 ABC + A1BC + AB1C  These output functions are unate since the vari- ables either appear in their complemented or un- complemented form but not both.Lemma 3: If the minimized output functions are unate, every fault (internal or at the input lines) will cause either single bit error or unidirectional multibit error at the output regardless of the way the circuit is implemented.Proof: If the outputs functions are unate, variables appear in either complemented or non-comple- mented form but not both.Thus, if a variable appears in a non-complemented form in a function, the vari- able either does not get inverted or go through even number of inversions from the input to the output.
Similarly, if a variable appears in complemented form, it either does not get inverted or goes through odd number of inversions.Therefore, if a variable is in uncomplemented (complemented) form, and a fault occurs at the corresponding input line, this fault will create unidirectional error since there is even (odd) number of inversions from the input line to the outputs.On the other hand, if a fault exists at node x and affects k outputs, then, there will at least k different paths P1 to Pk from the fault site to the k affected outputs.Suppose node x is affected by one of the inputs, say a (Figure 2).Since the number of inversions (modulo 2) between input a and the out- puts is the same, num_inv(a, o) num_inv(a, 02) Ok).In other words, num_inv(a,  num_inv(a, x) + num_inv(x, O1) num_inv(a, x) + num_inv(x, o).This implies num_inv(x, Ol) num_inv(x, o:) o) num_inv(x, Therefore, there is same number of inversions be- tween the fault site and the outputs which makes the fault produce unidirectional error.Q.E.D. Corollary 1: If an input variable, a, is present in complemented or un-complemented form but not both in the output equations, then any fault located in a path leading from variable a to the outputs will cause either single bit error or unidirectional multibit error. Proof: Suppose that variable a is presented in its uncomplemented form in all output equations, and suppose a fault f occurred at node x.Since x is af- fected by variable a, then by lemma 3, num_inv(x, o) is the same for all outputs that are connected to x.Thus, this fault will cause unidirectional error.U] 4.2 Output Encoding Another approach to prevent any two cubes from being x-bidirectional is output encoding.The idea behind output encoding is to ensure that the outputs corresponding to two input cubes Ci and C with dist(Ci, Ci) 1, are not partially bidirectional.
To illustrate, let us consider Table I, where Z and Z2 are the symbolic outputs.In this Table, C1 and C3 are a-bidirectional.Thus, by changing the output encoding for Z from 100 to 110, it can be guaranteed that the fault on line a will not produce bidirectional error at the output.
Let us assume the specification of a logic circuit with N symbolic outputs.An algorithm for encoding the output so that there are no m-bidirectional input cubes is given below.Algorithm 3: 1. Initialize m to [lg N] where N is the number of symbolic outputs. 2. Construct an undirected graph G having the output symbols as vertices.
3. Connect Vertex Oi to vertex O if they are ad- jacent. 4. Construct a unidirectional graph Gm with 2 nodes.
If Gm does not cover G, goto 6; else, an output encoding assignment is obtained from Gm. Exit.
Increment m.Goto step 4. Figure 3 shows the unidirectional graph G3.Ver- tices which are represented by all O's or all l's are connected to all other vertices because there is no other vertex which is partially bidirectional with these vertices.The number of edges, for a vertex depends on the number of l's in the representation of that vertex.If k is the number of l's in an m-bit vertex, then the number of edges for that vertex is (2 k-1) + (2 (rek) 1).
Table V shows that the number of edges each node has in a unidirectional graph as a function of rn and k.For every (m, k) entry, the number of vertices is mt/(k!x (m-k)!).A fully connected subgraph of Gm can have a maximum of rn + 1 nodes.For example, a fully connected subgraph of G3 can have a maxi- mum of 4 nodes.
To illustrate the application of the above alg o rithm, let us consider the specification for 3-bit priority encoder shown in Table VI.Each vertex in Graph G, Figure 4, is connected to all other vertices.The unidirectional graph G: does not cover G.However,  G3 covers G (the graph in Figure 3 covers the graph in Figure 4); hence, three bits are needed for output encoding.
Step 5 of Algorithm 3 is a graph embedding prob- lem which is NP complete.Therefore solving this embedding problem by using the smallest m requires exhaustive search.A heuristic solution with poly- nomial complexity is proposed in this paper.This heuristic solution gives satisfactory results when applied to MCNC benchmark circuits.As the results show, in the worst case the number of bits used for encoding the output is only one bit more than the minimum number required.The nodes of graph G are the symbolic outputs which are denoted by Oi's.
The nodes of graph Gm are m-bit vectors which are denoted by Vi's.The graph-embedding procedure is performed as follows: graph_embedding(G, Gm) unidirectionaLset(Oi) set of all nodes that are connected to Oi; V get_max unidirectionaLset(Vi) set of all nodes that are connected to Vi; if num_edges(Oi) -< num_edges(Vi) { use the m-bit encoding for Vi to encode output Oi; form G" which is a subgraph of G' with ver- tices as unidirectional_set(Oi); form G which is a subgraph of G with ver- tices as unidirectional_set(V); graph_embedding(G", G,); G" G' (node Oi and unidirectional_set(Oi) and all edges joining the edges of these nodes); Gm Gm (node Vi and unidirectional_ set(Vi) and all edges joining the edges of these nodes) } else { m=m+l; undecode all symbolic outputs; G" G; G Gm; until all outputs are encoded; The routine get_max( returns the node that has the largest number of edges.The routine hum_ edges( returns the number of edges for the node.Unidirectional_set(Oi) is the set of nodes that are joined to Oi by an edge.The dimension of Gm will increase by 1 when the if condition in graph_embed- ding ( ) fails; in other words, when node Oi in G' could not be mapped to node V in G because O has more edges than V.When the if condition is true in the procedure, graph_embedding( ) will be recur- sively called for embedding smaller sizes graphs be- cause the cardinality of the unidireetional_set(Oi) is always less than the number of nodes in the graph containing O.
Lemma 4: The complexity of Algorithm 3 does not exceed the order of N 4 where N is the number of symbolic outputs.
Proof: The number of edges/nodes in graph G are used in the estimation of the complexity because the number of edges/nodes in Gm are equal to a constant time the number of edges/nodes in G.The com- plexity of constructing graph G in Algorithm 3 is of the order of N because for each node in G, N -1 checks are made to see if that node is connected to the other nodes (Step 3 in the algorithm).Similarly, the construction of Gm has polynomial complexity.Each call to the graph_embedding() procedure is linearly related to the number of nodes plus the num- ber of edges because routine get_max( is linearly related to the number of nodes (N), and routine hum _edges( ) takes constant time.The unidirectional_set () is constructed in a time linearly related to the number of edges (IEI).It should be noted here that the complexity of the above procedures depends on how the graphs have been stored.When the if con- dition is always true in the procedure, graph_embedding( will be recursively called for a maximum of N -1 times with each call requiring steps of order N.
Thus, the complexity is of the order of N(N + The worst case occurs when G is fully connected; thus IEI N2/2 and the complexity of step 5 will be of the order of N3.When the if condition fails in the last recursive call for graph_embedding(), order of N operations are wasted and m is increased by 1 and the whole procedure is repeated.The if condi- tion will be true when m is equal to N 1 because a fully connected subgraph from Gm of N nodes can be found.Consequently G will be covered by Gm.
Therefore, the if condition can fail up to (N 1 Jig N]) times, and for each iteration, operations of the order of N are needed, thus the worst case com- plexity is order of N4.Q.E.D.
Proof." Algorithm 2 guarantees the elimination of m-bidirectional input cubes; therefore, by lemma 2, all single faults at the input lines will cause unidi- rectional error at the output.On the other hand, since the circuit is prime and irredundant, it has to be 100% testable.Therefore, for each node, there exists at least one input pattern that makes a sensi- tizable path from an input(s) through that node to an output(s).If there is only one sensitizable path for any input pattern from an input passing through node x to an output (there might be another path, but it cannot be sensitizable for the same input pattern), a fault at node x will produce single bit error since the fault only propagates to one output.In addition, if there is k sensitizable paths from input a through node x to k different outputs (Figure 2), an event at input a will cause an event at node x which will also cause events at the k outputs.An event at input a cannot cause a bidirectional change at the output due to the output assignment in algorithm 2. Thus, a transition or a stuck-at fault at node x cannot cause bidirectional error under the given input.Moreover, there might be other paths from an input different from a through node x and to some outputs; however, similar arguments can be made to prove that a fault at node x cannot cause bidirectional error.Consequently, all possible single stuck-at fault will either cause single bit error or unidirectional multibit error at the output.Q.E.D.
The following lemma summarizes the main fea- tures of the proposed techniques.
Lemma 6: If a combinational circuit is designed such that all faults at the inputs which create bidi- rectional error at the output are removed, any fault in the circuit, internal or at the inputs, will result in either single bit error or unidirectional multibit error at the output irrespective of the way the circuit is implemented.
Proof: The proof of this lemma is similar to the proof of lemma 5.
A detailed example is considered below to illus- trate the application of the proposed techniques.
Lemma 5: If a prime and irredundant combina- tional logic circuit has its outputs encoded using al- gorithm 2, then any stuck-at fault (internal or at the input lines) will result in either single bit error or unidirectional multibit error at the output regardless of the way the circuit is implemented.Example: In this example the application of the encoding techniques on rd53 MCNC benchmark cir- cuit will be considered.Table VIIa shows the de- scription of the benchmark circuit, rd53 circuit has 5 inputs, 3 outputs, 32 product terms, 32 different input patterns and 6 different output patterns.An  .11111 000 unconstrained boolean minimization using MIS [10] is applied first to the original description of the circuit as described in the benchmark, which produces the following results: lits(sop) 45 lits(fac) 36, where lits(sop) is the number of literals in sum-of-product form, and lits(fac) is the number of literals in the factored form.
The standard cell representation of the circuit re- suits in an area of 110400 Lambdas (230 x 480 Lamb- das).
As mentioned previously, m-out-of-n codes are used for input encoding.To minimize the number of input lines, we choose rn to be [n/2].Since the num- ber of input combinations is 2, 3-out-of-7 code is used for encoding the inputs as shown in Table VIIb.It can be easily verified that by using this input en- coding, either single bit error or unidirectional mul- tibit error at the output will result in presence of a stuck-at fault.An unconstrained boolean minimi- zation using MIS is applied, and the following results are obtained" In these output equations, no variable appear in both complemented and uncomplemented form.Thus, these equations are monotonic which guar- antees that every fault will create either single bit error or unidirectional multibit error at the output (Lemma 3).
The standard cell layout for this realization results in an area of 109440 Lambdas (235 x 384 Lambdas).Thus, the overhead is (109440 110400)/110400 -0.87%; i.e., the area is actually reduced.
(33) is only used in an uncomplemented form, and the path from (33)' to {v5.2} is masked.Therefore, there will be the same number of inversions between node (33) and the outputs.
Similarly, it can be shown that if one of the paths from a node to an output, where the number of in- versions is even(odd) is sensitizable, then all other paths from that node to the outputs where number of inversions is odd (even) are not sensitizable.
The standard cell layout for the above realization results in an area of 90688 Lambdas (218 x 416 Lambdas).Thus the area overhead is (90688 110400)/110400 18%.Note that the area overhead for the standard cell layout is not the same as the overhead for lits(fac) (Tables IX and X).This is because the area in the number of literals does not take into account the routing needed in the layout.However, lits(fac) still give a good measure of the overhead of different realization.

RESULTS
The number of literals in the factored form (multilevel realization) is approximately twice the number of transistors used in CMOS implementation because each literal will be an input to two transistors (one n-type and the other is p-type).Therefore, the results reported here are the number of literals in both fac- tored form and sum-of-product form.As far as we are aware, no other input/output encoding schemes are available that have the same objectives as that proposed in this paper.Thus, for each benchmark circuit, we will have three realizations" 1) direct im- plementation of the circuit as described in the bench- mark, 2) implementation of the circuit after input encoding and 3) implementation of circuit after ap- plying Algorithm 3. The results will be reported as the number of literals for each realization.The re- suits of realization 2) and 3) are compared to the results of realization 1).The statistics of the bench- marks are given in Table VIII where #inp is the number of input lines, #out is the number of output lines, #pro is the number of product terms, #diff_i is the number of different inputs present in the pla description, and #diff_o is the number of different outputs after expanding the input cubes.An uncon- strained boolean minimization has been applied to the different circuits by using the multilevel logic synthesis tool MIS [10].
Table IX shows the number of literals obtained for realizations 1) and 2).#lit(sop) is the number of literals in sum of product form, #1it(fac) is the num- ber of products in the factored form.
The percentage overhead is given for literal counts obtained from both sum-of-product and factored rep- resentation.Negative overhead indicates that the en- coded circuit has fewer literals than the original cir- cuit.It is clear from the experimental results that one can apply the input encoding to ensure every fault result in either a single bit error or unidirectional multibit error at the output, without increasing and  in most cases decreasing the overhead.The output encoding algorithm was applied to a few benchmark circuits to get some estimate of the overhead.Table X shows the results of these benchmarks.
In Table X, #out is the number of output encoding bits used in the algorithm, ovd is the percentage over- head.As in input encoding, the average overhead for the benchmarks circuits is negative, which indi- cates that on average output encoded circuits require less overhead than the original circuit description.In addition, the number of bits used for encoding the output is only one bit more than the minimum num- ber of bits required.Finally, the output encoding algorithm gives better results than the input encoding algorithm because the output algorithm assign uni- directional codes for two adjacent outputs; this as- signment will make one output dominant resulting in fewer number of literals in the final circuit [11]. 6. CONCLUSION Input and output encoding techniques proposed in this paper guarantee that all stuck-at faults, internal or at the inputs, will cause either single bit error or unidirectional multibit error at the output.Previ- ously published work in this area was restricted to AND/OR type circuits, and both inputs and their inversions were assumed fault-free.Thus, there are no schemes or algorithms for output or input encod- ing that have the same objectives as presented in this paper.The techniques proposed allow multilevel im- plementation as well as consider the possibility of faults at the input lines.The input encoding algorithm can be applied to arbitrary circuits because m- out-of-n code is used for input encoding, so the in- crease in the input lines is not significant.The worst case theoretical complexity of Algorithm 3 is N4; however, the average experimental complexity in N (the number of bits used for encoding the output is one bit more than the minimum number of bits re- quired).Therefore, Algorithm 3 can be efficiently applied to a circuit description that has up to few hundreds symbolic outputs.
cube Ci For every input cube Cj If Ci and Cj are x-bidirectional
Since G3 covers G, a possible output encoding is as follows

TABLE Truth Table of a
Logic Circuit

TABLE IV Specification
FA After Input Encoding

TABLE VII PLA
Descriptions of the Same Circuit Using Different Input and Output Encoding Schemes

TABLE IX Literal
Count for Original and Input Encoded Circuits Plus the

TABLE X Literal
Count and Overhead for Output Encoding Algorithm