Partial Reset : An Alternative DFT Approach

Design for testability (DFT) techniques reduce testing costs at the price of extra hardware. Among the many DFT techniques that have been proposed for this task are full scan, partial scan and hardware reset. In this paper we explore a relatively new DFT method, called partial reset. Reset lines are added to only a subset of the flipflops and obtain reasonably high coverage. This approach has lower overhead in terms of test application time and hardware area when compared to previous ones. Further enhancement of the controllability is obtained by using multiple reset lines. The configuration of these multiple reset lines is described. This technique has been evaluated on the 1989 ISCAS sequential benchmark circuits and obtained favorable results.

usually with respect to a circuit with no DFT tech- niques added.)A brief review of previous methods is now presented for comparison purposes.
DFT Techniques to Improve Fault Coverage Hardware reset is a mechanism which alleviates the initialization problem by bringing the sequential ma- chine to a known initial state (usually a state where all state variables are 0).The usefulness of this arises in situations where the sequential test generator (STG) aborts faults when it cannot find a homing or synchronizing sequence [5].It also reduces the test length if a synchronizing sequence is very long.The hardware overhead includes the logic that resets the flip-flops in addition to the routing of the reset line.This price is paid for higher fault coverage and sim- plified test generation [6].TAT is usually reduced when compared to a circuit without DFT.
Full scan is a technique that permits complete con- trollability and observability [3].It transforms a se- quential circuit virtually to a combinational circuit.This is done by having a scan mode where the mul- tiplexed flip-flops (FFs) are connected in a serial shift-register.Under normal operation, the FFs be- have in the ordinary fashion where they all load val- ues in parallel from their respective inputs.In test, or scan mode, any arbitrary value can be shifted, or scanned, into the FFs.Their values can be examined by shifting, or scanning out, the contents.The num- ber of test vectors generated for a given fault cov- erage is less than for a circuit without scan since the test generation is simplified.However, TAT may be high due to the required scanning in/out of vectors.Furthermore, full scan can have a hardware overhead from 5% to well over 30% depending on the type of scan design used and the ratio of combinational logic to latches [3].
Partial scan reduces the hardware overhead of full scan by requiring only a subset of the FFs be included in the scan path.For circuits with a large number of FFs, the TATs may be reduced since less scan clocks are required in between regular clocks.Fault cov- erages approaching those of full scan can sometimes be obtained with partial scan.A myriad methods for selecting the FFs to be scanned have been proposed.Trischler has suggested using testability measures as heuristics for selecting FFs [7].In [8], the authors generate test vectors and then select FFs that, if scanned, would make all remaining undetected faults detectable.In [9], a minimal set of FFs that break cycles was presented.Lee and Reddy have expanded the cycle cutting method with that of minimizing se- quential depth in [10].The authors in [11] have de- scribed an algorithm that is fault-oriented and uses testability measures to rank the FFs in the order of their effect on the fault coverage.The OPUS-2 [12] algorithm expanded the method of selecting the optimal solution from structural analysis with a procedure to select FFs that aided most in detecting faults aborted by a test generator.Scan designs have several disadvantages.The rout- ing of multiple lines and the more complex FFs con- tribute to the larger silicon area required.Scan de- signs will require at least three additional I/O pins unless the PIs and POs are multiplexed.Testing of each individual chip may take longer since the test vectors will have to be scanned in before the faults can be detected.To detect timing faults, the FFs are even more complex [13].The overall circuit clock speed may have to be reduced due to the additional logic in the scan path FFs.
DFT Techniques to Reduce TAT As stated above, the time and resources required to test each individual chip is just as important a con- sideration as fault coverage.The test application times, specifically, should be minimized [14].Many methods have been suggested towards this end.Wil- liams and Angell suggested that the "shift-register" used in testing can be split into several shorter ones [15] (called multiple scan chains).BIST techniques [3] usually have low TATs since no off-chip delays exist.Lee and Shin propose partial parallel scan where FF inluts are multiplexed with PIs and POs [14].The FFs are divided into N scan groups.The k FFs in each scan group are multiplexed to different PIs and POs so that all k FFs in each group can be scanned (in or out) in parallel.So, all FFs can be scanned in, at most, N clock cycles.Pradhan and Saxena have combined an STG and full scan to re- duce TATs [16].This method uses full-scan to ini- tialize the circuit and the STG to activate and prop- agate the faults without using scan.Thus, the need to scan-in and scan-out vectors between regular clock cycles is eliminated.Gupta et al have developed a system which partitions a hierarchical description of a circuit, generates test for the individual parts and combines the tests for all of the combinational logic [17].This method has to be used in conjunction to a DFT technique.In general, these TAT reduction DFT techniques have high area overhead.
A method that does not rely on any additional hardware is the one presented by Wang et al [18].
The authors demonstrate that the number of vectors can be reduced during the test generation process by choosing the next target fault based on a fault selec- tion measure.This method can be used in along with our DFT technique to reduce TAT even further (with deterministic STGs).

A New Alternative
Recently it was suggested that a selected subset of the FFs can be reset if a synchronizing sequence is prohibitively long or nonexistent [19].This technique has been dubbed partial reset (PR), and the conven- tional reset method is hereafter called full reset (FR)   [20].The suite of DFT techniques previously avail- able did not provide the tradeoff in fault coverage, TAT and hardware overhead as PR does.We dem- onstrate that PR is a good addition to the set of DFT techniques allowing more flexibility to designers.
With PR, there is not a unique state to which that the sequential machine returns as with FR [20].FR, as a consequence, can only be used once in a test vector sequence (usually at the beginning).PR, on the other hand, can be used within test sequences to give additional controllability.Direct transfers be- tween two states that differ only in the resettable state variables are possible.
In [20], the authors were the first to show that PR improved fault coverage and reduced test length over FR, using state space information.In this paper we examine the effect of PR on fault coverage and TAT for circuits described at the structural (gate) level using the single node stuck-at fault model.This al- lows the processing of larger circuits.
The following section describes PR and motivates its use.Next, we describe the FF selection process and reveal how multiple reset lines can be used to augment controllability.Lastly, we present discus- sion and results obtained using the ISCAS 89 se- quential benchmarks [21] and concluding remarks.

PARTIAL RESET
PR's main strength is its simplicity.Only a small subset of the FFs in most sequential circuits cause initialization problems.PR only resets those FFs.Due to this, the PR line can be treated as normal input to the sequential machine, after the circuit is initialized.The small number of FFs selected reduces the interference in state transitions when compared to FR.Thus, PR can be used at the beginning of a test sequence to initialize the circuit, as well as within a sequence to increase controllability.
PR promises lower routing/hardware (than scan designs) and higher fault coverage (than the original circuit) at the price of a slightly more complicated test generator.(The MOSIS Service's CMOSN stan- dard cell family's resettable D-FF is only 14% larger than the normal D-FF, as compared to the scannable DoFF which is 57% larger [22].)Furthermore, PR facilitates relatively faster TATs since it does not re- quire the scanning in of test vectors as with partial or full scan.Thus, the testing proceeds at normal clock speeds.
Pomeranz and Reddy have shown, with experi- ments on the MCNC synthesis benchmarks using the single transition fault model, that fault coverage either remained the same or increased (for all the circuits for which they generated tests) with PR when compared to FR. Test sequence length and test gen- eration time were usually reduced with PR than with FR.The tradeoff is in the higher test generator com- plexity, since a homing or synchronizing sequence needs to be generated to initialize the sequential ma- chine without FR capability.This paper will expand on these results.
In a previous work dealing with PR which was based on state transition faults, the reset mechanism is assumed to be fault-free.Our method makes no such assumption and the fault coverages we present include the effect of faults on the reset lines.One of two events occur when the reset line is faulty.
1.If the reset line is stuck-at the inactive value, the FFs affected will not be able to reset.They will behave as one of the unselected FFs (assuming a single stuck-at fault).
2. If the reset line is stuck-at the active value, the affected FFs will be stuck at the reset value.PR is illustrated using the circuit shown in Figure 1 with the indicated stuck-at fault.This particular fault manifests itself as a single transition fault [23] (darker transition arrow) as shown in the state tran- sition graph (Figure 2).A faulty circuit with this fault will go to state XoXl 11 instead of XoX 01 when output state =x the input of 1 is applied in the state XoX 00.The arrows are labeled with input/output values.
It is first shown that this fault is untestable without any DFT techniques.All possible transitions from state X0Xl 00 (the state from which the faulty tran- sition originates) are shown in Figure 3.The fault is activated by applying the input value 1 causing the machine to arrive at state 01/11, where the notation is good-state/faulty-state.The output produced in this transition is 0 for both circuits.Finally, when either 0 or 1 is applied, both the good and faulty circuits arrive at identical states and produce iden-  tical output sequences.Note that having FR does not assist in detecting this fault since this is not an ini- tialization problem.
If the FF which is represented by the state variable X is modified so that it resets to 0 when the reset input is activated, the fault becomes detectable.If the reset is applied (along with the normal input), the state transition graph would change as shown in Figure 4.The good and faulty transitions are shown for the state x0x 00.
The sequence that detects the fault is shown below.
Any STG that can initialize both the good and faulty circuits can be used.In the sequel, the notation of A ) B indicates that a transition is made from Og/Of state A to B when the input is applied producing the output O g and o i in the good and faulty circuits respectively [20].When the good machine is in state A and the faulty one is in B, A/B is used for state representation.The input Or implies that 0 is applied to the circuit's normal input along with reset.When both of the circuits produce the same value, only one  ----0 0 10 0/1 00" Some points require further elaboration.The reset input is activated twice; the first time is to aid in initializing.The good circuit becomes fully specified (initialized) before the faulty one.The states for both circuits become the same after the third input vector.The reset input is utilized the second time to activate the fault.Thus the fault is detected when the PR technique is implemented.
Finally, we note in passing that the observability can possibly be improved in a manner similar to which PR improves controllability.A subset of unob- servable FFs can be selected to be probed in some manner, taking into consideration the aliasing problem.

VALUES
The first problem in using the PR method is choosing the FFs which should be made resettable for the best results.In the example above, the fault will not be detected if state variable x0 was made resettable.Therefore, it is important to select the right reset- table FFs.
Our FF selection is made based on the circuit struc- ture.A graph called an s-graph is constructed to aid in this task.The s-graph is a directed graph G (V, E) where vertices and edges represent FFs and paths between FFs, respectively.An edge (v;, o) exists in the s-graph if there is a path through combinational logic from the FF represented by oi to the FF rep- resented by o.The main issue in adding testability to most sequential circuits involves the cycles of stor- age elements and combinational logic [9]. (Synchron- ous sequential circuits are assumed.)Logic values circulate within the sequential machine due to the cycles and reduce the controllability from the pri- mary inputs.If the cycles can be broken, the circuit will become easier to initialize and test.The cycles are "broken" by making one of the FFs in the cycle resettable.The s-graph allows a better view of the circuit's cyclic structure.The problem, then, is to find a minimum set of vertices V' so that G V' is acyclic.This is similar to the NP-complete problem known as "feedback vertex set." A lesser contributor to difficulties in sequential test generation is the sequential depth.PR produced bet- ter results for most circuits when it was tailored to tackle the problem of cycles rather than sequential depth.
The problem of breaking cycles has been attacked by researchers concerned with partial scan FF selec- tion.Lee and Reddy have proposed a near-minimal solution [10].We have adopted their techniques to select FFs that are made resettable.With partial scan design, the selected FFs can be controlled to any desired value independently.(Observability is provided as well.)PR only allows controllability to one value for each FE The selected FFs cannot be reset to this value independently.The benefit, however, comes in lower hardware requirements (e.g.routing of multiple lines, I/O pins).Note that in highly timing-dependent designs, the FF selection method can be modified so that FFs on the critical path are not selected.
Once the FFs to be reset have been selected, the next task is to select the reset values.Traditionally, the reset value of a FF is assumed to arbitrarily be 0. We propose a design where the selected FFs are allowed to reset to either 0 or 1, whichever will be more beneficial to the testing process.Note that this is not the same as having both preset and clear inputs, which requires more silicon area.The FF will only reset to one of the values in {0, 1}, which is deter- mined a priori at design time.In this scheme, the selected FFs do not all have same reset values.
Reset values are selected in one of two ways.The first is based on SCOAP [24].SCOAP is a testability measure that indicates the degree of controllability and observability of the nodes in a circuit.(Observ-ability values were not used here.)Selected FFs were reset to the value v {0, 1} where v is the value that had a lower controllability value.In some circuits, the 0and 1-controllabilities of a node may both be the same, preventing SCOAP from providing any helpful information.This is especially true in highly sequential circuits where many nodes are equally un- controllable to either value.In such cases, a second method utilizing simulation of random vectors was used.The number of times 0 and 1 occur at the output of the selected FFs are counted.The logic value {0, 1} having the minimum occurrence count is used as the reset value.A random reset value is chosen if neither of these two methods are helpful.This procedure is outlined in Figure 5.

MULTIPLE RESET LINES
Up until now, only a single reset line controlling all selected FFs has been considered.To provide more alternatives a method utilizing multiple reset lines is described.If designers have the freedom to add ad- ditional PI pins, this technique might improve fault coverage for a small cost.The number of resettable FFs is not increased.Two different schemes utilizing multiple reset lines were investigated below.

Selectable Reset Value
The first approach to increase controllability is to allow selected FFs tO change to either 0 or 1.This is similar to partial scan in that the FFs can be con- trolled to both values but is different since the FFs do not have individual control.This technique using two reset lines has been implemented.The function of the reset lines are described in Table I.  reset to 0 set to the reset lines have on a particular FF depends on its assigned reset value.The assigned reset value is only used to separate the selected FFs into groups so that they do not all reset to the same value at the same time.This potentially doubles the number of transitions from each state when compared to single reset.Note that some FFs will reset to 0 while others reset to 1 depending on the assigned reset value.This method is a simple extension of the single reset technique.

Partitioning FFs
The second method is slightly more complex.It par- titions resettable FFs into various sets.Each reset line, which is a PI, will reset the FFs in one of the sets.Fig. 6 shows pictorially how multiple reset lines can be used if the selected FFs are partitioned into two groups.Some heuristics for partitioning the FFs have been developed which produced encouraging results.
How partitioning is helpful is illustrated using the circuit from [25] which has the state transition graph shown in Figure 7.The graph shows a faulty tran- sition due to the stuck-at 0 fault at the node marked "w" in the circuit of Figure 8.The fault can be ac- tivated from the state PlP2P3 01X (with input 0), but only 010 is a valid state.The circuit makes the transition 01X 0 0o.Since states PlP2P3 110 and 010 are equivalent, the fault is not detect- able.Assume that the FFs representing Pl and P2 are chosen to be made resettable to 1 and 0 respectively.By resetting both FFs simultaneously while applying 0 to the input, both the good and faulty circuits arrive at state 100.Therefore, the single PR technique does not help.If the FFs were given independent control, denoted rl and r2, the following sequence would de- tect the fault: XXX lr'r2 0 ) 100 ) 010 X 0: 100 0 010 000 1/0 0--'" The number of transitions in the state diagram is increased when additional inputs are added to the sequential machine.output lines do.By partitioning the FFs into separate groups, the machine has more independent control over them.The freedom to reset all the selected FFs simultaneously is also retained.Figure 9 illustrates the maximal number of transitions from a state S for a single-input sequential machine lines.In general, the factor of transitions multiplied from each state is upper bounded by Elt- (19, where lr is the number of reset lines.

Partitioning Criterion
The selected FFs are put into a new graph, called the c-graph, that will be colored so that each color will represent a distinct reset line.A c-graph's nodes are the selected FFs and there is an edge between every node that is in the same strongly-connected component in the s-graph.The c-graph edges will be initially weighted according to the distances between the selected FFs in the s-graph.This graph may be a disconnected set of cliques, where selected FFs in the same strongly connected components in the s- graph are in a clique together.Next, the c-graph is colored taking into consid- eration the edge weights.If there is no edge between two nodes, there is no dependence on the colors that .maybe assigned to these two.Therefore, if two FFs are not in the same strongly-connected component in the s-graph, they can be assigned the same reset line (color) without affecting their independent con- trollability.The larger the edge weights (distance between selected FFs), the more likely the nodes will be assigned the same color.Distance is calculated as the number of gates between two points in the circuit.Our premise here is that FFs that are closer to each other will benefit more from being controlled by dif- ferent reset lines since FFs far apart affect different parts of the circuit.
Another heuristic is based on the following ob- servation" two FFs that fan out to the same combi- national logic block should be assigned different reset lines for more controllability.Higher controllability of the fanout nodes can be obtained by using inde- pendent reset lines than if the FFs were both con- trolled by the same reset line.The procedure adjusts the appropriate edge weights so the coloring will re- flect this heuristic.We found that by randomly per- turbing the edge weights slightly, more of the circuits could be successfully.partitioned.Graph coloring is known to be NP-complete and no good polynomial-time approximations exist [26].
Since the problem at hand is simpler and more flex- ible than general graph coloring, heuristics can be used to get results in a fairly efficient manner.The coloring procedure is shown in Figure 10.Non-zero positive integers represent the colors.(There are as many colors as reset lines.)Starting with the node of highest degree, the procedure assigns each node a random color that has not been used by any of its neighbors that are closer than a threshold edge sort c-graph nodes by degree set edge threshold do for each node (in decreasing order of degree) weight.(If there is a problem assigning a random color, the procedure next tries assigning the lowest numbered color that is not used by any neighbors.)This ensures that the neighbors that are closer than a specified threshold will be assigned different colors.
If the number of reset lines (colors) allowed does not permit the current graph to be colored, the threshold is reduced and coloring is attempted once more.Effectively, this reduces the number of neigh- bors that the coloring procedure has to deal with when attempting to assign different colors to the neighbors.The random color selection in the col- oring procedure is used to allow the FFs to be par- titioned in a somewhat uniform manner.Otherwise, the lowest numbered reset line would get more of the FFs assigned to it.The randomness appears to provide better results.
The overall partitioning method is summarized in Figure 11.

RESULTS
These algorithms were implemented into a C program and we ran them on the ISCAS '89 sequential create c-graph find distances between FFs adjust weights according to fanouts perturb weights randomly color c-graph benchmarks.They process all of the circuits within a few minutes.
The test generator we used in our experiments is CRIS, a new hierarchical (including switch-level) pseudo-random STG that uses genetic algorithms [27].CRIS has been developed on the Sun 4 platform at the University of Illinois.CRIS generates test vec- tors quicker than traditional deterministic test generators at the price of slightly lower fault coverage.
Table II describes the benchmark circuits that were used to obtain the results.The "Selected flip-flops" column indicates the number of FFs that were made resettable.
Fault Coverage with Single Reset Line As a basis for comparison, test vectors for the circuits of Table II without any DFT techniques were gen- erated.The number of faults injected and fault cov- erages are shown in Table Ill(a).
Table Ill(b) contains the number of faults injected and fault coverage obtained using FR.This will assist in separating the initialization effects of PR from the controllability of PR.Recall that FR can only be used for initialization and not within a test sequence.The selected FFs above were transformed into scan FFs and CRIS was used to generate test vectors for these circuits with partial scan.On the average, about 44% of the FFs in each of the circuits were selected to be made resettable.The fault coverages obtained are displayed in Table Ill(c).Since no faults were injected on the scan circuitry or scan path, the Circuit number of faults is the same as for the circuit of Table III(a).Note that the FFs scanned are the same ones that were made resettable to allow a fair comparison.
The results using a single reset line is presented in Table IV.The number of faults injected has increased slightly due to the additional faults of the resetting circuitry.The column labeled "% over no DFT" shows the percentage that the fault coverage in- creases by adding PR to the original circuit.The percentage that the fault coverage increases for PR circuits over FR is displayed in the column labeled "% over FR."The last column labeled "% under p. scan" shows the percentage that PR's fault coverage is below partial scan.
Most of these circuits yield results fairly close to partial scan.Seven of the circuits with PR produced fault coverages that are within 2.1% of the ones with PR.One circuit (s386) did not seem to improve the coverage much over the circuit with no DFT tech- niques.In fact, due to the additional faults injected, the fault coverage becomes slightly lower.
Initializable circuits with PR, where the resettable FFs are a large percentage of the total FFs, produce fault coverages further below that of partial scan than other initializable circuits with PR.This is a result of the interference referred to earlier.PR may still help when compared to circuits with no DFT tech- niques.This indicates that better heuristics are needed to select resettable FFs since the present method seems to help more with partial scan than with PR.We suspect that better results can be ob- tained by cleverly selecting a subset of these FFs.One possible method would be similar to the tech- nique presented in [28] for identifying FFs that can- not be initialized due to faults that prevent initial- ization.Another possibility is to combine cyclebreaking with a testability measure, such as SCOAP [241.In circuits that are difficult to initialize, the number of FFs that are made resettable has a big impact.For example, in s510, all the cycles are broken when five of the FFs are selected.If all of the FFs are selected, the fault coverage is further increased, as evidenced by the fault coverage of FR.In general, however, FR produces lower fault coverage than PR.It ap- pears that PR and FR benefit uninitializable circuits the greatest.PR can even aid circuits that already have a FR line since the PR line can be used like a regular PI for extended controllability.Some circuits were not impacted much by the reset value selection.When the reset values were changed, the fault coverage did not vary significantly.Just the fact that the FF was made resettable increased the testability the most.On the other hand, there were some circuits where the reset value had a big influ- ence.For example, s510 yielded a fault coverage of about 10% when all of the selected FFs were reset to 0. In contrast, the fault coverage rose to over 80% when all of the reset values were changed to 1.
The fault coverage is as expected for most circuits.In general, partial scan is better thanPR, which is better than FR, which in turn is better than the circuit with no DFT.Exceptions, on the other hand, do exist.CRIS sometimes produces better results with circuits without DFT when compared to FR.Part of the reason is that CRIS is not fault-oriented.The reset line will be preferred by the STG since it usually has the greatest effect on the circuit's state when compared to other PIs.Typical STG's do not have enough knowledge to determine when the reset line usage would become detrimental to the generated test sequence.The search may be affected adversely due to this and, therefore, produce anomalous re- suits.Note that this behavior may occur in deter- ministic test generators as well.For example, a cir- cuit with FR may allow the STG to generate a test sequence that is simpler and shorter than a circuit without DFT for a fault fl.The original circuit may cause the STG to produce a longer test sequence to detect f.However, a side effect of this may be that a hard-to-detect fault, f2, might be detected with the longer sequence.Therefore, the shorter, simpler se- quence may miss the faults that are "accidentally" detected by the longer test sequence [29].

TAT Comparison
We now evaluate the TATs for PR, partial scan and full scan.The test lengths for similar coverages are tabulated in Table V.We used the fault coverage of the original circuit (no DFT) as the target fault cov- erage.(For s510, we used the fault coverage of PR (83.8%), since the original circuit is untestable by 3- value STGs.)Since CRIS is a pseudo-random test generator, the test vector lengths are typically longer than ones obtained from a deterministic faultoriented test generator.We have calculated the num- ber of clock cycles required to test the circuits.The temporal cost of testing scan design circuits is cal- culated as follows: v + vs + (s 1),s>O and t>O where is the total number of clock cycles required for testing, v is the number of test vectors and s is the number of scanned FFs.The first term v is the number of regular clocks.The second term indicates the number of times that new vectors are scanned into the circuit while scanning out the results from ckt the previous time.The last term shows the clock cycles needed to shift out the results of the last test vector.The table shows how much smaller TATs are for PR with respect to the scanned circuits in the "% ckt bel" column.Cases where the scanned circuits had lower TATs are identified with negative "% bel" values.
The results indicate that PR produce much shorter TATs than partial scan, on the average.Only two partial scan circuits produced shorter TATs.Full scan, on the other hand, performed better than par- tial scan for all except the biggest circuit as far as TATs are concerned.Despite the improved outcome, full scan did better than PR on only 5 of 15 circuits.
In some cases, PR yielded a smaller number of test vectors for the same fault coverage when com- pared to partial scan.Theoretically, this should not be the case.There are two reasons that these con- ditions occur.The first is, once again, due to the fact that CRIS is a random fault-independent test gen- erator.The second is that the different search spaces that PR and partial scan have, leads to the existence of search anomalies.A PR circuit has a smaller search space with respect to the PIs.Since it is re- stricted, it might find a shorter sequence depending on its path in the search space.An STG processing a partial scan circuit may begin to search a part of the search space which would only produce longer test sequences.
We compare our results with those of other DFT techniques used for TAT reduction.PR shortened TATs by 60.78% compared to full scan circuits where there was an improvement.Pradhan and Saxena's method had an average of 29.07%improvement over full scan in the 12 ISCAS '89 circuits for which they reported results.The scheme of Gupta et al reduced test application times of lumped ISCAS '85 combi- national circuits by an average of 12.33 %.For partial scan circuits where there was an improvement, PR reduces the TAT by 80.9%.This translates to an average of 9.36 times speedup than the partial scan versions of these circuits (not including s35932 circuit ckt which produced a highly divergent speedup of 737).
Lee and Shin's method obtained TAT speedups of 11.25 and 8 over that for partial scan for the two circuits which they evaluated (assuming a limited number of PIs and POs).Our results are encour- aging, especially since TAT reduction was only a sec- ondary goal.
Fault Coverage with Multiple Reset Lines The fault coverages obtained for two reset lines are now compared with the ones for circuits with a single reset line.Table VI contains data obtained by using the simple technique of allowing the FFs to be con- trolled to both 0 and 1.The number of faults injected, the fault coverage and the amount the fault coverage increased over the single reset technique is shown in the table.This technique did not prove beneficial for many circuits.For many of the circuits, the coverage actually appeared to drop below that obtained by using the single reset method.This may be partly due to the heuristics used within CRIS.Only the circuits which had an increase in coverage over single reset are shown.
Table VII contains results for the scheme of di- viding the selected FFs into two partitions.The re- suits were much better using the partitioning scheme.Most of the circuits had an increase in fault coverage when compared to the single reset line method.We have noticed that using multiple independent reset lines facilitates detection of faults, even on the reset lines.This is a benefit that single reset cannot guarantee.By giving independence to selected FFs as in the partitioning technique, the fault coverage in- creases.Multiple reset lines were more helpful in circuits that had lower fault coverage when single reset was used.
This research was supported by the Semiconductor Research Corporation Contract 92-DP-109.

FIGURE 2
FIGURE 2 State transition graph of example circuit.

FIGURE 4
FIGURE 4 State transition graph if reset used.

FIGURE 11
FIGURE 11 Summary of Partitioning Method.

TABLE Selectable Reset
Value This is essentially what reset FIGURE 7 Transition Graph of Example Circuit.

TABLE IV Test
Generation Results with PR

TABLE VI Coverage
Improvement Using Selectable Reset Value