TOPS : A Target-Oriented Partial Scan Design Package Based on Simulated Annealing

In this paper, we describe algorithms based on Simulated Annealing for selecting a subset of flip-flops to be connected into a scan path. The objective for selection is to maximize the coverage of faults that are aborted by a sequential fault simulator. We pose the problem as a combinatorial optimization, and present a heuristic algorithm based on Simulated Annealing. The SCOAP testability measure is employed to assess the selection of flip-flops during the course of optimization. Our algorithms form a part of an integrated design package, TOPS, which has been designed as an enhancement to the OASIS standard-cell design automation system available from MCNC. We discuss the TOPS package and its performance on a number of ISCAS’89 benchmarks. We also present a comparative evaluation of the benchmark results.


INTRODUCTION
n designing digital integrated circuits, a popular .methodfor achieving testability is full scan design, where the flip-flops in the circuit are threaded into a chain, which can perform as a shift register when the circuit is placed "in the test mode.A test vector is shifted serially into the shift register, and the re- sponse of the circuit is shifted out serially for obser- vation [1].One of the serious drawbacks of full scan design is the area overhead that results due to the extra wiring required to thread the flip-flops into a chain the extra space occupied by flip-flops when they are modified into scan cells.
In order to reduce the overhead of full scan and still maintain the advantages offered by the scan meth- odology, several authors have designed techniques for partial scan design where only a subset of flip- flops are scanned.In order to guide the selection of as small a subset as possible, the following approaches have been considered in the literature.In all these approaches, the essential idea is to exploit the underlying structure of the circuit; a graph called S-graph is derived which captures the structural in- formation.An S-graph has one node corresponding to each of the flip-flops in'the original circuit, and a directed edge from node to node j if (and only if) there exists a combinational path from the flip-flop to flipflop j in the circuit.In other words, an edge (i, j) in S-graph represents the combinational logic that separates the output of flip-flop from the input of flip-flop j.
Cheng and Agrawal observed that a circuit is poorly testable if its S-graph has long cycles [3].
When a flip-flop in the circuit is converted into a scan cell, the operation corresponds to delet- ing the corresponding node in the S-graph.In order to achieve high testability, the S-graph must be rendered acyclic by deleting as few nodes as possible.We refer to this acyclic graph as A-graph in this paper.This problem, also called the feedback vertex cover set problem, is known to be NP-complete.Cheng and Agrawal gave heuristic algorithms to obtain small feed- back vertex covers.
Gupta and Breuer introduced the concept of balance in a sequential circuit in addition to the concept of acyclicity [6].The advantage of trans- forming the circuit structure into a balanced acyclic structure is that a combinational test vec- tor generator can be employed to generate test patterns for the partially scanned circuit.Some authors believe that poor testability of a circuit may be ascribed to its large sequential 234 C.P. RAVIKUMAR and H. RASHEED depth.The sequential depth of a circuit is de- fined as the length of the longest path in the Agraph.Thus, Lin and Reddy [8] considered the following problem.Delete the fewest number of nodes from the S-graph such that the graph becomes acyclic and the length of the longest path in the A-graph is minimized.The authors described a two-step heuristic algorithm for the problem; in the first step, cycles in the S-graph are removed by deleting nodes, and in the sec- ond step, the sequential depth is reduced by deleting more nodes.Each deleted node forms part of the final partial scan chain.
An entirely different approach may be consid- ered for partial scan.If a sequential test generation algorithm is available, one could attempt to run this algorithm on the unscanned circuit to generate test vectors within a certain time limit to detect as many faults as possible.The remaining faults, also called aborted faults or target faults, are the only ones which need to be addressed by the partial scan mechanism.In a similar setup, one may use a random test vector generator and a sequential fault simulator to generate a list of target faults.
Chickermane and Patel observed empirically that hard-to-detect faults tend to lie in strongly connected components (SCCs) of the S-graph [4].As a result, the partial scan system proposed by these authors examines the SCCs in the S- graph and computes a profit function p for each node i.If a node is part of cycles i, i2,... i, the profit pi obtained by scanning the node is given by k where W(i) indicates the weight of cycle ii.In turn, the weight of a cycle is the number of hard- to-detect faults that lie on the cycle.The objec- tive in [4] is to select cells for scanning, such that the cumulative profit is maximized without exceeding the upper bound on the cost of scan- ning.The authors presented heuristic tech- niques to obtain good solutions to the above optimization problem.
In this paper, we apply the Simulated Annealing algorithm [7] to the partial scan design problem.Un- like the references cited above, our algorithm does not rely on structural properties such as cycles, weighted cycles, sequential depth, or strongly con- nected components.Instead, we regard the search space in a uniform manner when looking for a so- lution to the partial scan problem.In our approach, the structural information is used to evaluate the testability of a configuration during the course of annealing.In the following section, we describe the details of the algorithm.In Section 4, we discuss the results obtained by applying our technique to several ISCAS benchmark circuits.We also implemented a greedy algorithm to compare the results obtained through the annealing procedure.The greedy algo- rithm and its results are also discussed in Section 4.
Our algorithms are integrated into a package named TOPS, which enhances the OASIS design automa- tion system [9] available from MCNC by providing partial scan capability.We discuss the salient features of TOPS in Section 3.

PARTIAL SCAN FOR TARGET- FAULT DETECTION
The Simulated Annealing algorithm [7] has been widely applied to a number of optimization problems in Design Automation such as floorplanning, partitioning, placement, and routing (see [10], [11]).The annealing algorithm is similar to an iterative im- provement algorithm in nature, with the exception that inferior states are also accepted with a certain probability.This probability is a function of a parameter known as the temperature, which is de- creased slowly during the course of the algorithm.At higher temperatures, the annealing algorithm ac- cepts inferior states with a high probability, hence behaving like a random search procedure.As the temperature is lowered, the acceptance probability for inferior states drops, and the procedure attains greedy characteristics at temperatures close to 0. The reader may refer to [7] for a complete description of the annealing algorithm.
The partial scan design problem may be phrased in terms of a state-space search as follows.A state, or configuration, consists of a subset of cells.Let n be the total number of flip-flops in the circuit.A subset of k flip-flops can be selected in (,) ways, and hence there are 2;],=1 (,) 2   1 possible solutions to the partial scan problem.A perturbation of a state consists of deleting a flip-flop from the present con- figuration, or adding a flip-flop to the present con- figuration, or both.The cost of a configuration is the area overhead that results by scanning the flip-flops which correspond to the present configuration.Our cost measure consists of two components.the increase in functional area an estimate of the increase in wiring area due to scan path The profit of a configuration is measured by the SCOAP testability index of the configuration [5], as extended to the case of target faults.We will describe our cost and profit function in more detail later in this section.
The procedure Anneal is outlined in Figure 1.The annealing schedule is given by the initial temperature T0, the final temperature T, the cooling rate a, the number of iterations per temperature M, and the rate /3 at which M is increased progressively over tem- peratures.The initial configuration S is also an input to the procedure; it consists of a randomly selected k-sized subset of the flip-flops in the circuit.The function perturb returns a new configuration S by perturbing the subset S as explained earlier.The new configuration is accepted under two conditions.
If both the profit and cost parameters of the new configuration are better, then S is accepted.
When the new configuration is inferior in either the cost measure or the profit measure, or both, then the Metropolis criterion [7] is separately applied to both cost and profit terms.S is ac- cepted if both the Metropolis criteria succeed.

Calculating the Profit
The profit function is an implementation of the SCOAP testability analysis procedure.In the SCOAP terminology, SC[x] indicates the sequential 1-controllability of a line x.SC[x] is defined simi- larly.The sequential observability of a circuit is de- noted by SO.The conventional SCOAP testability index for a sequential circuit is given by where the summation is carried over all lines x.In our work, since we are mainly interested in target faults, we define an alternate testability index T. Let 6r(x) be a 0-1 function which evaluates so 1 if and only if there exists a target fault of the form x-stuck- where the summation is carried over all lines l.
procedure Anneal(S To, T] a, fl, M); (* S is the inital configuration, with k flip-flops.
To is the inital temperature.T] is the final temperature.c and fl are the cooling paranaeters.
M is the number of trials attempted at any temperature.*) Scanning a flip-flop F affects the T index in two ways.
the controllabilities of lines that are reachable from the output of F may improve, and the observabilities of lines which lead to the in- put of F may improve.Let y(i, j) be a 0-1 function which evaluates to 1 if and only if there exists a directed path from line to line j.Let I and O respectively indicate the input and output of flip-flop F. Let T denote the testability index for the partially scanned circuit, where S is the set of flip-flops selected for scan.The expression for TU is given below.
The reader should note that while evaluating TPs s, the line observabilities SOIl] and controllabil- ities SC[I] and SCI[I] must be recomputed for the partially scanned circuit.For simplicity, we have used the same notation to indicate the observabilities and controllabilities for both unscanned and scanned cir- cuits.
The profit function computes the difference TPs U for a given circuit and a given subset of k flip-flops selected for partial scan.This is done in two steps.
1. a forward breadth-first-search to identify the lines whose controllabilities are affected by the partial scan.If the search process encounters a line such that/-stuck-at-r is a target fault, then the procedure accumulates the value SCl-r[l] into PSC -r (sequential 1 r controllability of the partially scanned circuit).
2. a backward breadth-first-search to identify the lines whose observabilities are affected by the partial scan.If, during the search, the procedure encounters a line such that/-stuck-at-r is a target fault, then the procedure accumulates SOIl] into PSO.Here, PSO indicates the se- quential observability of the partially scanned circuit.
It is clear that TPs PSO + PSC + PSC.The unscanned testability index U is computed by the program once initially.The worst-case time com- plexity of calculating the profit function is linear in the number of nodes of the circuit.

Computing the Cost
The computation of the cost of a configuration de- pends necessarily on the implementation technology and the layout style.In our work, the target tech- nology is 2/x SCMOS, and the layout style is standard cell.The size of the cell which implements the un- scanned flip-flop is 58.0 64.0A2.The scanned cell takes an area of 58 72.0A2.The functional area overhead due to a scanning a single cell is therefore 464A units.An increase in wiring area is also in- curred due to partial scan; this area is estimated as follows.We generate a placement P of the unscanned circuit using the available standard-cell placement tool.We assume that the same placement of cells is used in the scanned circuit as well.Under this as- sumption, we have implemented an estimator for the increase in wiring area.This estimator first calculates the increase in track density for each channel due to the extra wiring required to implement the scan path.
The order in which the scan cells are connected into a scan path is crucial in the above calculation.How- ever, the problem of determining the best ordering is an instance of the Travelling Salesperson Problem, and is hence computationally difficult.We generate a good heuristic solution to the problem and use this ordering to estimate the increase in the channel track-densities.The cumulative increase in track densities, multiplied by the width of a single track, is used as an estimate of the wiring overhead.

A Greedy Algorithm
In this section, we describe a greedy approach to the partial scan design problem.We use this procedure to generate a good initial solution to the selection problem; this initial solution is passed on as input to the Anneal procedure.As a result, annealing can begin at a relatively low temperature.We found this method very effective in reducing the total computational requirements of Simulated Annealing.
The essential idea behind the procedure Greedy is to rank each of the flip-flops individually by its target testability improvement index which we define below.
Given a sequential circuit with n flip-flops f, f2, fn, the target testability improvement index of a flip-flop fi is defined as t(fi) Tf]} U (4) procedure Greedy(n, limit, C); (* n is the number of flip-flops in the circuit.
limit is the upper bound on the area, overhead that can be tolerated.
C is the circuit description.*) FOVHD is the functional area overhead contributed by a single scan cell.wire_ovhd is a procedure which estimates the wiring area overhead for a given subset P of flip-flops In other words, t(fi) measures the improvement in target testability by scanning only the flip-flop f.
Since the functional area overhead resulting from scanning any of the flip-flops is the same, a greedy strategy for scan selection is to pick those flip-flops with the highest values for t.The upper limit on the area overhead is used to guide the number of selected flip-flops.The complete procedure is shown in Figure 2. If the target faults are distributed uniformly over the circuit and not clustered in a small region, the greedy algorithm is likely to perform well.We discuss the experimental results on the greedy algorithm in the Section 4.

THE TOPS PACKAGE
The algorithms discussed in the previous section have been coded in the C programming language on a Sun SPARC workstation.In this section, we discuss the overall organization of the TOPS package.As men- tioned earlier, the TOPS package is designed to in- terface with the OASIS design automation software from MCNC [9].The input to the package is the structural description of a sequential circuit given in either the ISCAS format, HILO format, or the VPNR format.VPNR (Vanilla Place and Route) is a circuit description language developed by MCNC.The advantage of using VPNR is that it allows us to describe the circuit as various levels of detail [9].If the input is provided in ISCAS or HILO format, we internally convert it into VPNR format (see Figure 3).The VPNR description can be compiled into a layout using two programs cplrt and dglrt, which generate a standard-cell placement and routing, respec- tively.The layout is generated using unscanned flip- flops (cell dr2s).The dftaudit program is used to prepare a circuit description as required by the se- quential fault simulator silt.silt applies a specified number of random test patterns to the circuit and reports the list faults which could not be detected.
The number of random test patterns, N, plays an important role in the performance of the partial scan design system.If N is chosen large, the list of target faults may become smaller, giving less work to the partial scan selection algorithms; however, the fault simulator would then require an excessive amount of CPU-time.Of course, there are hard-to-test cir- cuits (such as the s420 benchmark from ISCAS) for which increasing N beyond a certain limit does not help in reducing the number of target faults.Pres- ently, we select N by a trial-and-error procedure where N is initially set to 1000 and doubled in every iteration.If two successive values of N do not reduce the number of target faults, we use the smaller value of N to generate the final list of target faults.If the final value of N selected by our procedure is N, it is easy to see that we need logz(N/1000) runs of sequential fault simulation.Assuming linear-time performance from the fault simulator, the total time spent on fault simulation is seen to be O(2N 000).
The TOPS package receives as inputs the original netlist, the placement information, routing infor- mation, and the list of target faults.After the selec- tion process, the TOPS package modifies the layout description file (VPNR format) to convert the se- lected flip-flops into scan cells (cell type dsr2s).The scan program is used to thread the flip-flops into a scan path.

EXPERIMENTAL RESULTS
The effectiveness of the TOPS package was tested against several standard ISCAS'89 benchmark cir- cuits.These are tabulated in Table 1.NF is the num- ber of flip-flops in the original circuit.UFC indicates the unscanned fault coverage obtainable by running a random test pattern generator as explained in the previous section.SS is the size of the scan set (number of flip-flops selected for scan).SFC(G) is the fault coverage obtained through the scan set selected by the Greedy procedure.SFC(G + A) is the fault coverage obtained by first running the Greedy procedure and then improving the solution by running the Anneal procedure.
We compared our benchmark results with other published work, namely, [4] and [8].Our results were better in three cases (s298, s386, and s510), and com- parable in the remaining cases.It is to be noted that in [4], and [8], the authors used a deterministic se- quential test pattern generator on the unscanned cir- cuit.As a result, the unscanned fault coverage re- ported by these authors is significantly higher than those in Table 1.As an example, for the circuit s526, the unscanned fault coverage is 49.4% in [8]; the random test pattern generator which we used could only generate a fault coverage of 9.9%.Similarly, the unscanned fault coverage for s386 is 67.44% in our system, whereas it is 81.8% in [4].Table 1 also throws light on the performance of the Simulated Annealing algorithm in comparison to the greedy algorithm.The greedy algorithm competes with the annealing algorithm in most cases, but the annealing algorithm performs better in three of the nine cases tested.This is to be expected, since the greedy al- Circuit NF -s208  gorithm may select a flip-flip f2 following the selec- tion of f based on the testability improvement index of f2.However, it may be the case that many of the faults covered by f2 are alreadycovered by fl.Since the greedy procedure does not reverse its decisions, it is likely to get stuck at a local optimum solution.
The annealing procedure, on the other hand, can start with the solution generated by Greedy and im- prove it further by applying local transformations.of a circuit.We have presently initiated an effort to improve TOPS through the use of similar structural properties such as acyclicity.

FIGURE 3
FIGURE 3 The Organization of TOPS package Greedy Algorithm for Partial Scan Selection.