Optimal Testing and Design of Adders

On-the-fly calculations of area and performance are a typical part of the computer-aided iterative design process in VLSI, which aims at a satisfactory tradeoff of various conflicting objectives, among which are test-generation time and test-set size. However, determining test sets on-the-fly as one circuit is transformed into another is extremely difficult. Our goal is to add a test dimension to the design optimization process that complements methods concerned with area and performance optimization. We define a set of logic transformations that result in easily computed changes to test sets. Test-set preserving (TSP) transformations preserve a combinational circuit’s test sets, while test-set altering (TSA) transformations introduce a minimum number of tests needed to maintain completeness. We illustrate our approach with a family of adders that share area-efficient tree structures and differ in the amount of carry-lookahead used to accelerate carry computation. Members include the ripple-carry adder, which has no lookahead, and the standard carry-lookahead adder, which exploits lookahead across all inputs. It is straightforward to derive area and performance measures for this class of adders. Given an n-bit adder with lookahead degree k, we determine a sequence of circuit transformations that produce the adder of degree k2 and test sets of minimum size. Optimal test sets of size k(logkn

area (measured by gate count) and performance (measured by worst-case delay), both of which should be minimized.Since it is usually straightfor- ward to assess the impact of small changes to a design on area and performance, iterative improvement has become the predominant strategy for solving multi- dimensional design objectives.However, determin- ing sets of input test patterns as a circuit is trans- formed into another is extremely complex, so generation of such test sets is normally separated from the design process.Yet there exist empirical results demonstrating close relationships among the test sets for various implementations of the same function.
For instance, Dav6 and Patel have shown that a com- plete test set for a two-level circuit almost always detects all single stuck-line (SSL) faults in other re- alizations of the same circuit [7].
Others have circumvented the problem of on-the- fly test-set computation by employing circuit trans- formations that preserve the complete test sets of the initial circuit [3, 8, 9, 12], that is, the test sets for the initial circuit are sufficient to completely test all transformed circuits.We formalized the concept of test-set preserving (TSP) transformations in [3] and showed how they can explain analytically the test- set relationships found by Dav6 and Patel in adder design [7].A drawback to these approaches is that the complete test sets for the initial circuit can be much larger than those necessary to test transformed designs.For example, the minimal n-bit two-level adder requires at least c2 tests, where c is a constant; this is equivalent to (2n) tests in complexity nota- tion.We show in [3] that the two-level adder can be transformed into the ripple-carry adder with TSP transformations only.However, the ripple-carry ad- der requires at most O(1) tests, far fewer than the two-level adder.
One might think that it is straightforward to de- termine test patterns that are rendered unnecessary by a circuit transformation and remove them.However, a test that is no longer required for a trans- formed subcircuit cannot be removed without determining if the test is needed by the overall circuit.We therefore introduce test-set altering (TSA) transfor- mations, which add a minimum number of tests to maintain complete test sets for SSL faults in trans- formed designs.TSA transformations enable test-set computation to take place in tandem with circuit transformation.The test sets for transformed designs are the union of the initial circuit's test sets with tests added by subsequent TSA transformations.TSA transformations also enlarge the design space.Se- quences of transformed designs are no longer re- stricted to those monotonically decreasing in test set size, and initial circuits need no longer be in two- level or other canonical forms.
We apply TSA transformations to adder design, extending our earlier work on TSP transformations [3].The target circuits are a family of regularly struc- tured adders {k,}, where n represents the size of the adder in bits and k the degree of carry-lookahead, that is, the number of input bits used to compute carries.{nk} includes a large number of adder designs that represent different solutions to area-and performance-based design objectives.For instance, 1 is the ripple-carry adder, which is efficient in area but not in speed.Improvements in speed can be made at the expense of area and fanout; such im- provements lead to carry-lookahead, carry-select, or carry-skip adders [1,4,5,6,10,11,15].We restrict the class {k} to area-efficient adders whose area com- plexity measured by gate count is O(kn).The carry- select and carry-skip adders do not meet this bound; they also require larger test sets.The fastest but larg- est adder in {Ck} is C, which consists of a constant number of logic levels.
It is a simple task to derive area and performance measures for the family {Cnk}.Testing requirements are far more difficult to ascertain and presently there are only limited results.For example, it is well known that the n-bit ripple-carry adder is C-testable, that is, it can be completely tested for all SSL faults with a constant number of tests.Becker [4] determined that O(log2n) is an upper bound on the number of tests for the SSL faults in the carry-lookahead adder of Brent and Kung [5], however, Becker's test sets are not of minimal size, as we will demonstrate.
Abraham and Gajski discuss a more general procedure that results in test sets that are O(m) in size for a circuit composed of m modules [1].This upper bound is also not tight because it does not account for the potential parallelism among tests.
In the following section, we present the notation necessary for transforming circuits and test sets.The structure of the family of adders {c} is then exam- ined, and the procedures for transforming the adder into (' that produce test sets of minimum size are detailed.We obtain test sets k(logkn + 1) + 2 in size, which we show is optimal for k n.Following this, we discuss the relationship of other adder types of TEST-SET ALTERING LOGIC TRANSFORMATIONS In our earlier work [3], we defined a general set of test-set preserving (TSP) transformations for com- binational logic circuits.A TSP transformation is a function ;-that takes a circuit (or a corresponding expression) C1 and returns the circuit ,'ffC1) C2.The SSL fault test sets T(C1) for the initial circuit are related to the test sets T(C2) for the transformed circuit by equality T(C1) T(C2), inclusion T(C) C_ T(C2), or covering T(C) C T(C2).Equality and inclusion relationships are straightforward; T(C1) covers T(C) if and only if for any test set T1 T(C) there exists some test set T2 T(C2) such that T2 C_ T1.In Figure la, T(C1) is included in T(C2).T(C1) also covers T(C2) by implication.Figure 1b illustrates the covering relationship that allows us to relate the smaller test sets T(C2) to T(C1).Each of these re- lationships is transitive, hence a sequence of TSP transformations is also TSP.A TSP sequence relates test sets that are mono- tonically decreasing in sizethe initial test sets in- clude all tests for the transformed circuits.As stated earlier, the initial test sets can be several orders of magnitude larger than necessary to test transformed designs.Hence our approach to this problem is to examine transformations that add a minimum num- ber of tests to maintain completeness for the test sets of the transformed circuits.For instance, we would want to add the test Our starting point is the four TSP transformations, fanout-free, De Morgan, extraction and resubstitu- tion, defined in [3], which were shown to suffice for adder design.Combinations of these transformations produce transformations such as "flattening," used elsewhere in the literature.We now characterize the test-set effects of the inverses of these TSP transfor- mations.In the case of fanout-free and De Morgan transformations, T(C) T(C2), from which it fol- lows that T(C) T(C1) and their inverses are TSP.Typical examples of fanout-free and De Morgan transformations are ,'((x + x: + x3)) ((x: + x:) + x3) and 91((Xl + 2)) (x2), respectively.The inverses of these transformations ;f-1 and ,are basically of the same type.However, in the case of extraction and resubstitution, T(C1) C_ T(C2), which does not imply T(C:) C_c T(C1); hence the inverse transformations, distribution and substitution re- spectively, are not TSP.A The distributive transformation is defined as the inverse of the extraction transformation, that is t,; -1, and corresponds to the distributive law of Bool- ean algebra.It aids in converting (flattening) a circuit to two-level form.Figure 2 illustrates the distributive transformation ((x + x)(X:l + x22)) ((x 12 lXl) "-}- (xx2) + (xx) + (xx))and the corresponding test- set transformation.Distribution has the general form (S) P, where S ((s?)(s)... (S+m)) and P ((p') + (p') +... + (p)).The expressions (E+)   and (E*) denote an arbitrary number of sum and product inputs, respectively.The number of product terms q in P is n xn2.., nm where ni is the number of inputs to the sum (s[).Inputs to (s+) are labeled X 1 x 2 i X n i , i and are subject to minor independence constraints [3].The minimum and complete test sets are related by T(S) D_c T(P), hence distribution is TSA.
Since S and P are two-level circuits, we only need Consider the to consider faults on each input xj.
of (s/+).The test stuck-at-1 fault x/1 on an input xj for this fault in S requires (sI) 0, or X lX2, x O0 0 bni.The fault is propagated to the output of S if and only all (s[) 1 for k i, or Xx:k k xk, dd .1.d r,k (d denotes don't care).Hence b2r2 0011 is the first test in Figure 2 that detects the faults x 1 and x/1.The correspond- /in P can be detected in parallel ing branch faults of xj k k 11 if allxf lin(s)forki, orxxE...x,- 1 a,.Thus for all of the sum terms in S, we add a set of m tests, denoted by TI(P) tJ=l(a a,,_,b,,,a,,,+, anm)" T(P) b2a2 {.J a2b2 0011 tO 1100 for the example in Figure 2.However, T(S) contains T,(P) due. to the patterns chosen for r2; in this instance of T(S), no tests are added.
Next consider the stuck-at-0 fault xlO on an input x,i of (s+).The test for this fault in S requires x!. here different choices for r2 are made for each test.
The corresponding branch stuck-at-0 faults in P may not be detected in parallel, hence a test must be xl added for each of the fanout branches.These tests are To(P) W,,W,:.W,.To(P) W2W2 ( 10tO 01)(10 tO 01) 1010 tO 1001 tO 0110 tO 0101 for the example in Figure 2. The shaded patterns represent tests already present in T(S).Hence only two patterns are added for this form of distribution.The general test-set transformation for distribution is therefore of the form T(P) T(S) U TI(P) U To(P) The substitution transformation is defined as the inverse of the resubstitution transformation, i.e., ,9 -.Substitution replicates circuitry and moves fanout toward the primary inputs.We identify two forms of the substitution transformation, which are illustrated in Figure 3; these correspond to the two forms of resubstitution [3].The test sets T(F) must be transformed so that the tests T(E) are applied to k copies of subcircuit E. The form of the test set transformation depends on the type of substitution.
In the case of space-disjoint substitution (Figure 3a), the outputs of F are controlled by disjoint sets of inputs X. Hence all copies of E can be tested in parallel.The change in the propagation of the tests T(E) is illustrated in Figure 3a.Let VT(Z) denote the values of Xi such that zi Ei.The corresponding test-set transformation is T(G) r(F) T(E)(VT(Zl)Vr(z2)... VT(Z)) In time-disjoint substitution, the output z Ei for disjoint sets of values Vg of the select input Vs.Faults in different copies [E]g may not be detected in parallel since each value of Vs sensitizes only a single path from E to z. Hence tests are required to test each [E] individually.This is reflected in Figure 3b by the sequential time-multiplexing of the tests T(E) by the sets of values V, V2, V.The test set transfor- mation for time-disjoint substitution is: The tests added by TSA transformations are ex- pressed in terms of the module's inputs and outputs.In general, transformed modules are embedded within a circuit and these tests must be propagated and justified to insure that they detect new faults in the transformed circuitry.For the adder, a few jus- tification and propagation functions V and Vp suffice to describe the conditions necessary to apply trans- formations to embedded modules.For arbitrary cir- cuits, conventional testing techniques can be used. x

ADDER STRUCTURE
The structure common to all adders in {3n k} is referred to by Unger [15] as the combinational iterative tree (CIT), and is applicable to any circuit that can be described iteratively.Each node in the tree computes an output function that characterizes the primary in- puts feeding that node.In the case of the adder, three types of functions are computed" the carry function c, the carry-generate function gi, and the carry-propagate function Pi.The adder's behavior is defined recursively by the carry equation ci aibi / aici-1 + bici_ and sum equation s aibici_ q--dibiCi_l -+--dibi'i-1 q-aibiei_l, or, equivalently, si ai ( b ci-.This iterative description gives rise imme- diately to the n-bit ripple-carry adder.The ripple- carry adder's tree structure is a linear chain, i.e., the n nodes in the tree have in-degree one, and each computes the carry ci and sum si functions for a single pair of input bits ai, bi. Figure 4 depicts the tree structure inherent in this circuit, which we exploit in the circuit transformation process.
The carry-generate and carry-propagate functions are defined as gi aibi and Pi ai + bi, respectively, and allow us to express the carry function as ci gi + pc_l, where go Co, the input carry.ai, b.Let g. gi and Pi.i Pi for convenience.
We can also show by induction that: Note that go,i Ci" The adder 3n k computes equations (1-3) and the sum functions si using four distinct logic stages, each consisting of a single module type GP1, GPk, Ck-1 or S. The modules GP1, GPk, Ck-1 and S compute gg and pg, equations ( 2) and (3) with j k, equation (1), and si, respectively.In the k 1 case, consists of GP, C1 and S modules only.The first stage of k contains n GP1 modules that compute &, Pi for 1 -< -< n.The second stage of the adder consists of a regular k-ary tree of GPk modules, which compute the functions gLi, PLi, where j k.A regular kary tree has 1ogkn levels, where n is an integral power of k, interior nodes of degree k + 1, and n/k leaf vogt,i (n-1)/(k-1)GPk nodes.There are --,i=0 modules in the tree, each consisting of k / 1 gates.In the first level of the tree, gj.i and pj.g are calculated fori k, 2k,...,nandj i-k + lfromthe inputs g,, p,, gn-1, Pn-1, gl, Pl computed by the first stage.At the m-th level, g,,i and Pi,i are cal- culated for km, 2km, n and j k + 1 from the outputs of the previous level.For instance, the functions gP,4, gPs.8, gP13,16 are computed in the second level of the adder 6 shown in Figure 5.At the logkn-th level, g,i and P,,i are computed for k Ign n and j 1 The third stage of the adder is a divergent regular k-ary tree that computes the carry functions c, c2, c, from the generate and propagate functions gj.i and Pj,i of the GPk tree and the input carry Co.If the inputs to the module Ck-1 are labeled gk-1, Pk-1, g, p, CO, then C-I calculates the k 1 carry functions Ck-, Ck-2, C described by equation (1).The Ck-1 tree contains (n 1)/(k 1) modules of E/k= k(k + 1)/2 1 gates each.The first level of the tree is a single module that computes the k 1 carry functions C,/k, C2n/k, C(k-1)n/k from the functions g,,, p,, computed in level 1ogkn 1 of the GP tree.For example, the module C computes the carry C,/k C8 in the adder C6 in Figure 5.The m-th level of the Ck-1 tree consists of k modules that compute the carries from g,,, P,a in level IOgkn rn of the GPk tree and the carry signals determined in previous levels of the Ck-1 tree.After level m, the k carries Co, C,/km, CZnlkrn, (km-1)n/k are avail- In the fourth stage of the adder, the sum s is computed by the module S, for 1 -< -< n.We assume a specific implementation of S consisting of two 2- input exclusive-or modules.These modules may be realized in any form, as exhaustive testing (4 tests) is required to detect faults in all possible implementations.Figure 6 depicts the adder Ct46, a quaternary structure present in the adder for the Advanced Mi- cro Devices AM29050 microprocessor described by Lynch and Swartzlander [11].
Area and performance measures for this family of adders are easy to derive, which allow us to find optimal values of k.The number of modules in Ctn k is M(n, k) n + (n 1)/(k-1) + (n 1)/(k- 1) + n + 1 ((2n + 1)k-3)/(k-1).When each term is multiplied by the number of gates per module, we have a gate count of A l(n, k) (n 1)k + (23n + 1)k-(20n + 4) (4) 2(k 1) which serves as a measure of area cost.The minimum number of gates occurs for k 3, independent of n.The gate complexity of O(kn) is superior to those for other adder types.For instance, the class of ad- ders {(Nn k} based on Abraham and Gajski's design [11] requires O(knlogkn) gates.
We can obtain a second measure of area cost by considering the layout area.If we assume that a gate with rn inputs occupies an area C proportional to m, the adder's layout area is A2(n, k) C((n-1)k3 + 15(n-1)k + (194n + 22)k-186n-30) Based on this measure, the minimum area for an adder (k occurs when k 2, even though the gate count A (n, 2) > A l(n, 3).Turning to performance measures, the longest delay in terms of gate-path length is VLSI implementation [13, 14].Numerical solutions of these objective functions yield optimal values of k in between 5.7 and 6.2 due to a slight dependence on n.Hence both the A 2D and A zD objectives favor small amounts of lookahead k relative to n.
The adders in {(,} have a well-defined structure; consequently, estimates of their area and delay are easy to establish.Even though test generation is pre- dominantly a structure-based process, characterizing the testing requirements for the adders in (X k is not straightforward.We proceed to show how this can be done by applying the theory of TSA transfor- mations described above.
The minimum delay occurs for k n.
Using the above measures for area and delay, we have examined the optimization functions A2D and A2D 2, which commonly represent the "cost" of a

CIRCUIT AND TEST-SET TRANSFORMATION FOR ADDERS
The degree k of an adder Ct k directly affects area and delay, as indicated by equations (4-6) in the previous The initial circuit d, is a version of the ripple-carry adder of Figure 4.The function ci aibi + aici_l + biq_ is computed in the form c g + pq_.
This form allows us to cast the ripple-carry adder into the structure defined in the previous section.
Figure 7 depicts the structure of dn and an initial test set, which is a minimal test set for all SSL faults.The ripple-carry adder of Figure 7 does not have a GP1 tree since the inputs required for the linear C1 tree are provided by the functions g, p in the first stage.The final transformed circuit ] results from re- peatedly applying the procedure below that trans- forms n into d, k.The final circuit consists of two single-node trees GPn and Cn-1, illustrated in Figure 8. Incidentally, both 1, and ] can be transformed into the minimal two-level adder by applying the specific TSA transformations that are the inverses of the TSP sequences for adders [3].There are several potential sequences that transform ., into n", de- pending on the increment of k. Figure 9 depicts sev- eral of these, where :ff denotes a transformation of dn k into d, .(When k 1, :::), denotes the transfor- mation of n k into ', for some integer rn > 1.) The procedure for transforming , into d, k is marked by a transformation of the modules GPk and Ckinto the modules GPk and Ck-, respectively.
The straightforward process of grouping the modules GPk and C_1 that compose GP and Cz_ is illus- trated in Figure 5 for 126, which is to be transformed into 46.We now describe the general procedures for transforming C_1 into C-1 and GPg into GPk.
These are applied to modules of the circuit from right to left, that is, from primary outputs to primary in- puts.Tests are specified in algebraic terms using two functions V and Vp we call value-justify and value- propagate, respectively.Let Vp(c) be defined as the values of the primary inputs that propagate the re- sponses to the tests T(Ci) for module Ci to the signal c.For example, Vp(C3) a3b3 01 or 10 {0} in Figure 5.Let V(T(Ci)) denote the values of the pri- mary inputs that justify the tests T(C) applied to module Ci.In the following tables, we simplify these expressions as much as possible to describe the form of the tests but avoid lengthy descriptions of easily computed test sets.
The goal of the circuit transformations in Table I is to move all fanout internal to Ck2_ to its periphery, which is accomplished by steps 1 and 2, and subsequently apply distribution to produce Ck2_ in two-level form.Table I also defines the TSA trans- formations that accompany each of the preceding circuit transformations.These steps are illustrated in Figure 10.In step 1, the space-disjoint substitution transformation S,1 removes fanout on the carry sig- nals c, C2k, Ck-) by replicating Ck-1 k 1 times.The expression for the transformed test sets can be simplified; several of the added tests are im- plied by the simplified expression.In step 2, a second substitution transformation s.2 produces k(k 1) GP modules, one for each carry function Ck2_ through Ck.For example, in Figure 5 two GP2 mod- ules are produced for Ca and c2.Substitution re- quires the addition of O(k2) tests for all copies of the repeated subcircuit GPk.These tests are of the form Vp(Ck2_l)Vj(T(GPk))Vp(Ck(k_l)) {10} {10} After some fanout-free transformations are applied, which do not affect test sets, the distribution transformation reduces the four-level circuit to the two-level form Ck-. The 1 transformation is applied k 1 times; each application introduces O(k) tests.These tests are specified in terms of the inputs to Ck2_1.After all Ck2_ modules have been produced by this procedure, O(kElogk2n) tests have been introduced.Most of these new tests can be merged with the tests for fin k.
Table II describes the transformation of the mod- ules GPk to GPk2 and the test sets T(GPk) to T(GPk:), which proceeds from primary outputs to- ward primary inputs.Figure 11 illustrates the procedure.In step 1 the substitution transformation eT, moves the fanout from the k 1 gates of the form Pmk+l,(m/l)k in GPk to the inputs of GPk: so that the subcircuits gl,k and P l,k may be constructed inde- pendently.T(pk+l,Ek) consists of k + 1 tests which are propagated separately by both Vp(g.kO and Vp(P,kO.A fanout-free transformation produces Pa,k from ((Pl,k)(Pk+l,2k) (P(k-1)k+l,k2)) The mod- ule GPk is completed by applying tJ3 k 1 times in step 2. Substep 2.i results in k additional tests, hence step 2 contributes (k 1)k tests to T(GPk0.After Step Circuit Translk)rmation Test-set Trmsformation T(Ck2_l := T(Ck2_l q.) Vp(CkE_l)Vj(T(Ck_l)) __{ol ,ol I 1 v(r(C_lll producing all GPk2 modules, O(k21Ogk2n) tests have been added.Again, most of these new tests can be merged with the tests for Ct k, resulting in O(kElogm)   tests for n k:.After transformation to the adder n k2 is complete, the added tests must be combined and merged.
Rather than describing the complex procedure for doing so, we illustrate the test sets that result from transforming an adder along the path Ctln :=> &, 4, :ff .We use the notation T to denote the test-by-test concatenation of m copies of a test set T. For the test set T {tl, t2, tk}, T {t', Step Sr. (Pt+.2,) [P.+.2,I. [P,+1.2,12....
T((l) (010 100 t_J 011 t_J 101 tA 110 001)" IT(cf')l 6 Table III recursively expresses the test sets T(.fk) that result from applying the procedures of Tables I and II with various values of k.
The above analysis shows that the test-set size for (k is Ir(c )l k(logkn + 1) + 2. Becker [4] has shown that Brent and Kung's adder [5], which is a simplified version of 2 n, can be tested for SSL faults gP(k-1 )k+ ,k '"Pk    by 81og2n 6 tests.However, our analysis demon- strates that IT(C2n)l 21og2n / 4, roughly a quarter of the number of tests determined by Becker.We now show that the final test set T(a) in Table III is optimal.
Theorem 1: IT()I 2(n + 1) Proof: The test set T(() in Table III is guaranteed to be complete by our TSA analysis because we have added tests to maintain completeness for each TSA transformation.Hence IT((f)l-< 2(n + 1).We pro- ceed to show that 2(n + 1) is also a lower bound for IT((f)[.Consider the subcircuit that computes the carry c g + Pg-+ + PP- pco in (", (modules GP and C in Figure 8), which consists of n + 1 terms labeled in a right-to-left ordering by that is Cn, Cn P'nPn-1 Pigi-1, where 1 -< -< n.
Any complete test set must detect the faults gi-1/O, g-l/1, and p}/1, <-j <-n, for each of these product terms.The tests for the faults &_l/O, gi_/1, and p}/ 1 are presented in Table IV in the form of a fault table .A complete set of tests for the subcircuit com- puting c is the union of the tests obtained by varying and ] over the ranges specified in the table.
Now that we have a well-defined measure IT(ngl for the testing dimension of a circuit, it is possible to perform tradeoff analysis using test-set size as a parameter in the objective function.For example, we might choose the objective function A2(n, k)/ T(a.)l, which is analogous to the area-delay objec- tive used in [14].It is easily shown that the value of k that minimizes A2/T occurs between 7.4 and 9.2 for values of n ranging from 16 to 1024.A counter- intuitive result of this analysis is that the larger values for k occur for the smaller values of n, meaning that as the number of input bits increases, the optimal amount of carry-lookahead decreases.
O(knlogkn) gates, which is greater than the bound of O(kn) for {,}.We show briefly how {} relates to the class {a,}.Figure 12a illustrates , redrawn in a form that resembles .acontains the first two stages of and part of the third stage.
eJ28 is transformed into using the TSP transfor- mations , 6 and s, hence the test sets for 82 must be no smaller than the test sets f0r 82.The fanout- free and extraction transformations 3: and t; transform a connected pair of GP2-C1 modules into a pair of C1-C1 modules.The first of these Ca modules is pres- ent in the partial C tree of ; hence the application of the resubstitution transformation .gts that combines these replicated subcircuits.The second C module becomes part of the C tree.This sequence is re- peated level by level for other GP2-C1 pairs, pro- ducing the adder of Figure 12b.Similar sequences exist for other forms of Abraham and Gajski's adder; their test sets can be determined by generalizing this example.

CONCLUSIONS EXTENSION TO OTHER ADDER TYPES
Other adders that do not have the structure described in section III require more area and, in turn, larger test sets.These include the carry-select and condi- tional sum adders, among others [6,10].As men- tioned previously, the class of adders {n} based on Abraham and Gajski's design [1] requires We have shown for the first time that it is possible to generate optimal test sequences on-the-fly while exploring the design space for adders.We have done this by defining test-set-altering transformations that complement the circuit transformation rules typically used in CAD-based design.This makes it possible to treat testing on an equal footing with area and delay in making VLSI design tradeoffs.Currently, we are investigating the applicability of our approach to a broader class of designs that can be described iteratively.It appears possible to extend our work to these circuit types, making it feasible to explore the rich design space of VLSI circuits and obtain optimal test sets at the same time.
FIGUREExamples of inclusion relationships among sets of test sets.

FIGURE 4
FIGURE4 Tree structure of a ripple-carry adder.

FIGURE 8
FIGURE 8 Final transformed circuit

FIGURE 9
FIGURE 9 Values of k for some typical adder transformation sequences.

FIGURE 12
FIGURE 12 TSP transformation for the Abraham-Gajski adder However, the impact of k on the test sets of the adder is not as easily determined.We now show how to transform the adder n into t and produce test sets of minimum size.The procedure may be generalized to transform d, into d, k for rn_> 2.

TABLE Circuit and
Test-SetTransformations for the Ck2_ Tree

TABLE II Circuit
and Test-Set Transformations for the GPk2 Tree

TABLE III Test
Sets for the Adders 2,, g4, and c3

TABLE IV Fault
Table for the Subcircuit of et, Computing c, , hence it too is essential.The tests for pjl, where is constant, may be combined into {::,) {::) {::,) 00 {i,i}