A Quadratic Programming Approach to Estimating the Testability and Random or Deterministic Coverage of a VLSl Circuit

The testability distribution of a VLSI circuit is modeled as a series of step functions over the interval [0, 1]. The model generalizes previous related work on testability. Unlike previous work, however, we include estimates of testability by random vectors. Quadratic programming methods are used to estimate the parameters of the testability distribution from fault coverage data (random and deterministic) on a sample of faults. The estimated testability is then used to predict the random and deterministic fault coverage distributions without the need to employ test generation or fault simulations. The prediction of fault coverage distribution can answer important questions about the “goodness” of a design from a testing point of view. Experimental results are given on the large ISCAS-85 and ISCAS-89 circuits.


INTRODUCTION
he problem of test generation for a VLSI circuit is to find a set of inputs that detect the presence of a desired fraction of modeled faults.The process of finding such a set can be summarized as follows: Create a fault list from the circuit descriptions; initialize the test set to empty.While coverage of test set is less than desired coverage do 1.Select a target fault, f, and generate a test, t, for f using random or deterministic test generation procedures [10]; add to the test set if needed.
2. Simulate the generated test on the re- maining faults [2] and update the fault list by removing faults detected by the gen- erated test Steps (1) and (2) above dominate the overall costs of the test generation process.Here, the costs are measured in terms of the CPU time and memory space requirements.The simulation costs are non- linear in the size of the fault list [11].In a previous paper [1], the above test generation process was re- stricted to a sample of faults.By employing a rela- tionship between testability and fault coverage, tests generated on a sample of faults were used to estimate the population coverage without the need to use full fault simulation.Thus, major savings in the overall costs of fault simulation were obtained.Figure 1 shows a flow chart of the process of test generation by fault sampling.The model used in estimating the testability profile is of great importance since the estimated testability is used to predict the population fault coverage and the sample size for pass two (if needed).In previous work the testability profile was modeled as a beta distribution [7].The advantage of such a distribution is in the flexibility of the beta model (from a statistics point of view the beta model represents the most flexible and tractable two parameter model).The testability distribution of real circuits, however, is a mixture of step functions over the interval [0, 1] (this is due to the finiteness of fault populations).In ad- dition in previous work, deterministic input vectors were used to estimate the parameters of testability.The testability profile is a function of the detection probabilities of faults in the circuit.probability of a fault, however, is a function of the input distribution used.For example, when deter- ministic test generators are used to generate the input tests, the input vectors can be considered "random" from some unknown distribution.For this type of input distribution target faults have a detection probability equal to one (assuming no fault is redundant and no time limits are imposed on the deterministic test generator).As a result the testability profile dis- tribution of deterministic vectors is usually more skewed to the right than that of random vectors taken from a uniform distribution.
The main contribution of this paper is: 1) adopting a general model and estimating its parameters (this results in a new procedure of estimating the testa- bility profile of a circuit that is different from existing procedures [3, 13, 14]), and 2) estimating the random and deterministic coverage distributions of aset of vectors without the need to employ expensive means of full fault simulation.
The testability profile is modeled as a series of step functions over the interval [0, 1].In addition, in order to account for redundant faults, the model includes an impulse function located at zero.
In estimating the testability distribution we use deterministic and random vectors.For both cases, the test generation process is carried over a random sample of faults.Deterministic and random tests are generated and simulated on the sample of faults (without fault dropping).The testability parameters are estimated from the detection counts collected on the sampled faults.From the estimated parameters, the random and deterministic coverage distributions are estimated without the need to employ the ran- dom or deterministic test generation process.
The paper is organized as follows.In Section 2 the needed definitions and the testability model are given.Section 3 contains a quadratic programming approach to estimating the testability parameters.Section 4 includes experimental results on three of the large ISCAS-85 circuits for the random coverage case and three of the large ISCAS-89 circuits for the deterministic coverage case.The conclusions are given in section 5.

BACKGROUND AND THE TESTABILITY MODEL
Definitions and Background.The detection probability of a fault, a, is the probability of detecting a by a random vector.Note that the detection probability of a fault is affected by the distribution from which the random inputs are selected.For example, when deterministic test generators are used to generate the tests, the input vectors can be considered "random" from some unknown distribution.For this type of input distribution, target faults have a de- tection probability equal to one (assuming no fault is redundant and no time limits are imposed on the deterministic test generator).
The detection probability distribution (testability profile), p(t), is the probability density function of the detection probabilities of faults.The term p(t)dt corresponds to the fraction of faults with detection probability in [t, + dt].
The fault coverage by n vectors, y,, is the fraction of faults detected by the n vectors.The set of vectors can be generated randomly or deterministically.
For random test generation, the method of ob- taining the test vectors is a function of the probability of choosing a zero or a one at each input.We choose a uniform distribution.That is, the probability of applying a zero at any input is the same as the probability of applying a one.From [15], the random coverage by n vectors is y, 1 f(1 x)"p(x)dx 1 I(n).We call the term I(n) the undetectability profile.
Deterministic test generation is accomplished by employing deterministic test generation procedures.For a given (target) fault, the test procedure selects a test for the fault by searching the input space.Thus, deterministic test vectors are assumed to detect at least one new fault not detected by other previously generated tests.In addition, the deterministic test (generated) is assumed to act as a random vector on the non-target faults.The distribution of the input space is unknown, however.From [15], the deter- ministic coverage by n vectors can be found as y, 1 where Y is the fault population size.For large n with n < < Y, this coverage can be estimated by Yn 1 I(n) + n/Y.The approximation has an intuitive interpretation.The n/Y term is the contri- bution of the n deterministic vectors to coverage.
The remaining term (1 I(n)) is the random cov- erage contribution of deterministic vectors on non- targeted faults.The Testability Model.The testability profile dis- tribution of actual VLSI circuits is a mixture of dis- crete step functions.Figure 2 shows the actual test- ability distribution of the ISCAS-85 C432 circuit.
In accordance with actual distributions of the test- ability profile, we choose the following general test- ability model.
where 8(t) is the Dirac delta function, a + a2(t2 h) + + a(t t_l) 1, and ai >-O, 1, 2, k.The model includes an impulse function at zero to account for the contribution of redundant faults (redundant faults have detection probability equal to zero).A knowledge of the a parameters, 1, 2,... k, can be used to estimate the coverage distribution by n vectors.For deterministic coverage, the esti- mated coverage using the above model is evaluated to y, 1 1 + "al n 4-1 Z ((1 ti) "+1 i=l wherex 0, ...,N, andj 1, ...,n,.From (4), the probability that fault fj is detected 1 times is given as PIXj i-11 f: (/ -NI) ti-l(1 t)N-i+lp(t)dt k-1 t,+, ( N ) ti_l(l t)u_i+ldt, al + .,ai-1 /=2 (1 ti+l)n+l) ai+,] Similarly, for random vectors we obtain (2 In the next section we present a method of estimating these parameters by applying the test generation pro- cess to a random sample of faults. where -> 1. Equation ( 5) was obtained from the testability model of p(t) as given in (1) and can be written as where 3

PARAMETER ESTIMATION
The statistical frame work.Assume that a random sample of ns faults is drawn from the fault population of a given circuit.Let Y denote the fault population size.Let denote the actual detection probability of the ith sampled fault, 1, ns.Note that t equals the fraction of the input space that will detect the ith fault and that such a t/. is not known.
For ns << Y, one may assume that tl, tn constitutes a random sample of faults from a popu- lation of faults with detection probability distribution p(t), 0 -< -< 1. Assume N random input vectors are applied to each of the ns faults.Let Xl, Xns denote the number of times (out of N) faults 1,... ns are detected, respectively.The conditional distri- bution of X; given ti is binomial with N trials and success parameter ti.That is (x The unconditional distribution of Xi is a mixture of binomials with probability distribution function given by P[Xi x] tx(1 t)N-xp(t)dt, (4)   eit 1) ti-1(1 t)N-i+ldt, /=2,...,k. ( This can be written as 1,...,N, where and eil 0 for all >-2 Computing the parameters of testability.Let W equal the number of X/s which are equal to i, 0, 1, N. That is Wi is the number of faults in the sample that are detected out of N times.Then P[Xj 1] is approximated by Wi-1/ns, 1, N. Based on the unconditional distribution of each Xi (i O, n), the testability parameters can be estimated using the method of least squares.
To do this we need to minimize D /1: /:1 eitat-Pi where Wi-Pi--1 N, ns subject to the constraints fp(t)dt 1 and ai >--0 for 1, 2, k.It is well-known that least squares problems can be solved by quadratic pro- gramming methods.Here, we show how this method apply to the problem of estimating the testability parameters.Let E,p and A be N x k, N x 1 and k x 1 matrices with entries eii,'pi and ai, respectively.Multiplying the above matrix equation for D and simplifying we get, D ArHA + 2GA (7) where H is the k x k matrix ErE and G is the k x i matrix with G Erp. From this and the previous constraints, we obtain minimize Subject to The above is a quadratic programming problem with H a positive definite symmetric matrix.A solution to this problem will yield the proper ag values in A.
These values can then be used to estimate the cov- erage distribution from the testability and coverage relationship.In order to solve this problem, how- ever, we need to determine the values of the constant matrices G and H.In addition, the t ti+ terms needed to be known.For these, we choose equally k-l' Matrix H can be computed from knowledge of E.
Each of the ei in (8), and hence E and H, can be computed by employing the IMSL routines DBINPR and DBETDF.Similarly, Matrix G is computed from knowledge P and E.

EXPERIMENTAL RESULTS
We carried the proposed method of computing the testability profile and estimating coverage data using random and deterministic test generation.
Random test generation.For random test genera- tion the proposed method was applied to three of the large ISCAS-85 circuits, C2670, C6288, and C7552 [3]; C2670 was chosen due to its resistance to random testing.For each of the circuits a random sample of 1000 faults was selected.On the sample of faults random patterns were generated and sim- ulated using a deductive fault simulator [2].Unlike test generation procedures, however, each fault was simulated for each of the generated patterns and a count was recorded of the number of times each fault was detected.On each sample, patterns were gen- erated while noticeable changes in sample coverage were observed.For both, C2670 and C7552, minor changes in the sample coverage occurred on random patterns exceeding 200 vectors.For these circuits we chose 300 random patterns.Similarly, for the C6288 circuit minor changes in sample coverage occurred for random patterns exceeding 50 vectors.For this circuit, we chose 100 patterns.The Xi and Wi counts obtained from the sample of faults were then used to estimate the random testability profile using the IMSL routine "DQPROG."The number of parameters used in the testability model was 50 for each of the circuits.
The estimated testability profile was then used to estimate the random coverage distribution of the three circuits without generating actual random tests.
To do this we used the equation for random cover- age, y, 1 f01(1 x)"p(x)dx.The expected ran- dom coverage was computed for each circuit for 5000 random vectors.In a separate run, we computed the actual random coverage for each circuit for the same number of vectors.Figure 3, shows the expected and actual coverage curves for the C2670 and C7552 cir- cuits, respectively.Table 1, includes the initial cov- erage data (estimated and actual) for the three cir- cuits.As can be seen from the table, initial estimates of coverage do not agree with actual ones.This is due to the fact that coverage by the first random vector can vary by up to 20% in some of the circuits  studied.This variance, however, is removed as the number of vectors generated increases.Initial esti- mates of coverage can be improved if "fault drop- ping" is used [9].When fault dropping is used, Xi is the value of the vector number for which fault fi is first detected.
Deterministic test generation.For the determinis- tic test generation case the proposed method was used on three of the largest ISCAS-89 circuits, $35932, $38417, and $38584 [5].Although these are known to be sequential circuits, we have regarded them as combinational by considering all the flip- flops fully controllable and observable, as if they were connected in a full-scan chain.
Here unlike the random test generation case, how- ever, two samples of faults were used; one sample to generate the deterministic vectors, and another sample to collect the X; and Wi counts by simulating these vectors on the new sample.To generate the deterministic vectors we used the PODEM test gen- erator on a sample of 500 faults [10].The number of tests generated were 27 for the $35932 circuit, 103 for the $38417 circuit, and 80 for the $38584 circuit.All remaining undetected faults were identified as redundant or aborted (an aborted fault is a fault for which a test cannot be found within a time limit set on a test generator search time; this time limit is a result of the NP-complete nature of test generation [12]).
The generated tests were then simulated without fault dropping on a different sample of 1000 faults.For this the deductive fault simulator was used.
(Here, it is important to mention that a sample size of 1000, and not 500, faults was chosen in order to get a better estimate of the detection probabilities; this sample size, however, is still very small relative to the size of the actual fault population, well under 5 % for any of the three circuits).The testability pro- file parameters were then estimated from the Xi and W counts using the IMSL routine "DQ PROG."The number of parameters chosen for estimating the test- ability profile were approximately half the number of vectors generated.The number of parameters for the $38417 circuit was 50.The numbers of parameters chosen for the $35932 and $38584 were 20 and 40, respectively.Note that 20 parameters were cho- sen for the $35932; this was done because the number of vectors generated was small (27 vectors).Table 2 shows the non-zero computed parameters for the three circuits.
The predicted distribution of the deterministic fault coverage was obtained from y, 1 I(n) + n/Y.To compare the distributions of the predicted and actual population coverage the standard test generation process was performed on the entire fault population.In a separate run, tests were generated for the three circuits.For the $35932 circuit 78 vec- tors were generated.The tests covered 89.809% of the faults.For the $38417 ($38584) circuit, a test set of 1318 (900) vectors was generated.The test set covered 99.410% (95.502%) of modeled faults.Fig- ure 4 shows the curves of actual and estimated fault coverages of the three circuits.

CONCLUSION
This paper considered a testability model similar to that of actual testability distributions.As a result the model generalizes a previous beta testability model.
A relationship between testability and fault coverage were used to predict random and deterministic cov- erage distribution without the need to generate test vectors or to employ fault simulation.Applications of the presented work include: 1) prediction of test set length needed to cover a certain fraction of modeled faults, 2) test generation by fault sampling, and 3) estimation of the testability profile of a circuit.
Define the matrix, C, asC EA P [cij].Note that the matrix, C, is an N x 1 matrix where EA P)T(EA P).

TABLE Initial
FIGURE 3Estimated and actual random coverage distribution.

TABLE II Computed
Parameters for the Three Circuits