An Approach for Self-Checking Realization of Interacting Finite State Machines

This paper presents a technique for designing interacting finite state machines which will be totally self-checking for any single stuck-at fault. In the proposed technique m-out-of-n codes are used for both primary output and state assignments. In addition, the next state logic (NSL) for each submachine and the output logic (OL) are realized such that any single stuck-at fault results in either single bit error or unidirectional multibit error at the output. The proposed technique does not have any restriction on the way the NSL and the OL are implemented.

[1] e.g.LSSD, Scan-path have been proposed to overcome the problem.Despite their advantages scan-based circuits cannot be tested at normal speed and also require long test times.
An approach for designing fully testable state ma- chines without using scannable memory elements is discussed in [2].This method adds edges to the initial STG (State Transition Graph) specification to raise the number of states to 2 n where n is the number of the latches in the machine.In addition, the synthesis procedures are hard to apply and may increase the area without any significant improvement in testa- bility.This is because the state machine under test must be placed in a valid state so that with appro- priate inputs it can excite the fault and propagate its effect to the external outputs.These steps are slow because for every possible fault the appropriate state and input have to be found, and it might take 2 cycles to place the circuit in the desired state.Also, the above mentioned approaches for testing state machines are unable to cope with transient faults.Transient faults are emerging as the dominant failure mode in VLSI circuits [3].Current testing strategies are incapable of detecting this type of fault since these testing techniques, whether applied ex- ternally or implemented as BIST scheme, have been designed to detect only permanent faults.The char- acteristics of a transient fault require a test strategy which continuously monitors the operation of a cir- cuit so that whenever an invalid output is present, the fault will be automatically detected.Such a test strategy is known as self-checking or on-line testing.
The problem of designing totally self-checking syn- chronous state machines has been examined by Diaz   [4] and by Ozguner [5].If a Moore machine has rn different inputs, p different outputs and n states, Diaz proposed using m-out-of-2m code for input en- coding, n/2-out-of-n code for state encoding and p-out-of-2p code for output encoding.Ozguner pre- sented a method for designing totally self-checking Mealy synchronous state machines.In principle, this method is similar to that of Diaz; it uses 1-out-of-n code for state codes and 1-out-of-m code for the input encoding.
The decomposition of large Finite State Machine (FSM), or a lumped FSM, into smaller interacting FSMs increases performance and reduces area over- head.This is because currently available schemes for state assignment and for logic optimization are ex- 336 FADI BUSABA and PARAG K. LALA ponentially related to the size of the input, and there- fore inefficient for large FSMs.In general, these schemes guarantee better results for small FSMs than for large ones.In addition, if smaller interacting FSMs are used instead of a lumped machine, there will be less logic between latches, thus significantly increasing the speed of operation.As in [6], three types of state machine decomposition are considered in this paper: parallel decomposition (Figure la), cascade decomposition (Figure lb) and arbitrary de- composition (Figure lc).In Figure 1, 'I' is the pri- mary input, 'O' is the primary output, M1 and M2 are the two submachines, INT1 is the intermediate lines from M1 to M2, INT2 is the intermediate lines from M2 to M1, and OL is the combinational logic for generating the primary outputs.Parallel decomposition does not allow any inter- action between the component submachines.The submachines M1 and M2 are supplied with the same input sequence, but operates independently.The next state lines of the submachines as well as the external inputs are supplied to the combinational cir- cuit OL to generate the output.Cascade decomposition allows unidirectional interaction between the component submachines.Both submachines are dri- ven.by the same input sequence, but they do not operate independently; the next state lines of M1 are direct inputs to M2.The information flow from M1 to M2 enables M2 to generate the appropriate out- put.In this case, it is necessary to guarantee that a fault in M1 will be propagated to M2 and to the primary output.Submachine M1 is usually called the driving machine, and submachine M2 is called the driven machine.Finally, arbitrary decomposition al- lows bidirectional interaction between the component submachines.We also assume here that the sub- machines interconnect through their next state lines, and there is no logic in the interconnection paths.The state lines of both submachines and the primary input lines drive the OL.
Decomposition of state machines was first de- scribed in [7], where preserved partitions were used to find cascade decomposition.An approach for find- ing general decomposition using factoring algorithm has been proposed in Ref. [6].A recent approach for decomposition ensures that the sum of the num- ber of product terms in the one-hot encoded sub- machines is minimum [8].
As mentioned previously, currently available schemes for self-checking state machines consider only lumped machines [4] [5].Even if these schemes are used to make all interacting submachines self- checking, it cannot be guaranteed that the composite machine itself will be self-checking.This is due to the limited controllability/observability of the inter- connection lines between the different submachines.Therefore, different schemes have to be applied for designing interacting finite state machines such that they are self-checking.In this paper, we propose a novel technique for designing interacting finite state machines from the state transition graphs of the con- stituent submachines so that the composite machine will be fault-secure and self-testing for all single stuck-at faults i.e., totally self-checking.

PRELIMINARIES
Def. 1" A vector X covers vector Y if X has a 1 in every bit position where Y has a 1. Vector Y is then covered by X.
Def. 2: Two vectors O and 02 are partially bidirec- tional if there exist at least two output bits which are 10 in O and 01 in 02 or vice versa.For example, O 1100 and 02 0101 are partially bidirectional whereas O 1000 and 02 1111 are not.Def. 3: Two input cubes are called m-directional if they only differ in position m and their corresponding outputs are partially bidirectional.(c) Arbitrary Def. 4: A fault f creates a unidirectional error if the correct and the faulty outputs are not partially bi- directional.
Def. 5: A circuit is fault-secure for a given set of faults, if for any fault in the set the circuit never produces an incorrect code word at the output for the input code space.
Def. 6: A circuit is self-testing, if for every fault from a given set of faults, the circuit produces a non-code word at the output for at least one input code word.
Def. 7: A circuit is totally self-checking, if it is both fault-secure and self-testing.The following def- inition is taken from [10].
Def. 8: A primitive gate in a network is prime if none of its inputs can be removed without causing the resulting circuit to be functionally different.A gate is irredundant if its removal causes the resulting cir- cuit to be functionally different.A gate level circuit is said to be prime if all the gates are prime and irredundant if all the gates are irredundant.
Def. 9: A state machine is represented by its state transition graph (STG) G(V, E, W(E)) where V is the set of vertices corresponding to the set of states, E is the set of edges that join the vertices corre- sponding to the transition from one state to another, and W(E) is the set of labels attached to each edge corresponding to the inputs that lead to the transition and the associated outputs.A state machine has an Output Logic (OL) block which generates the pri- mary outputs, the Next State Logic (NSL) block which drives the next state lines, and memory ele- ments.In Mealy machines, the primary inputs as well as the present state lines feed the OL and the NSL.
When n latches are used, each state in V is represented by an n-bit vector.An n-bit vector at the output of the latches represents a valid state if that state belongs to V. All other n-bit vectors that rep- resent states outside V are invalid states.A single stuck-at fault can occur at OL, NSL, memory ele- ments or at the primary outputs.We assume that the primary inputs are fault free.The output of the latches are referred to state lines throughout this paper.
[9] that these kind of redundancies could be eliminated by logic syn- thesis restriction.CRFs are due to the presence of lines/wires in the logic circuit that do not contribute to the primary output or the next state functions.
SRFs in a state machine can be classified into three categories [9]" 1) 3) Equivalent-SRF: The fault causes the inter- change/creation of equivalent states in the STG.
Invalid-SRF: the fault does not corrupt any fan- out edge of a valid state in the STG.Isomorph-SRF: the fault results in a faulty ma- chine that is isomorphic; i.e., the faulty ma- chine is equivalent to the fault-freemachine but with a different encoding.
If parallel decomposition is used, the redundant faults in the resulting interacting submachines will be the same as that in the composite machine since the submachines work independently.
On the other hand, if a cascade decomposition is used, redundant faults in the composite machine can be classified into four categories [10]: 2) A fault in M1 that propagates to INT1 but not to primary output O.
3) A fault in M2 that does not propagate to O, but will have if INT1 were completely control- lable.
4) A fault in M2 that does not propagate to O even if INT1 were completely controllable.
Clearly, if none of the submachines has redundant faults, then type 1 and 4 of redundant faults will not appear in a cascade decomposition.
Sequential redundant faults in an arbitrary decom- position can be classified into six categories: 1) A fault in M2 that cannot propagate to the intermediate lines INT2.
2) A fault in M1 that does not propagate to O, but will have if INT2 is completely controllable.
3) A fault in M1 that does not propagate to O even if INT2 were completely controllable.4) A fault in M1 that cannot propagate to the intermediate lines INTl.5) A fault in M2 that does not propagate to O, but will have if INT1 is completely controllable.6) A fault in M2 that does not propagate to O even if INT1 were completely controllable.FADI BUSABA arid PARAG K. LALA Redundant faults of type 1, 3, 4 and 6 would not appear if none of the submachine has redundant faults in itself.Redundancies similar to type 2 in cascade decomposition are not present in the arbi- trary decomposition described in this paper.Be- cause, if a fault in M1 (M2) propagates to INT1 (INT2), the first erroneous output will be an invalid output (Lemmas 5 and 6 in Section 3).Therefore, if the fault propagates to the INT1 (INT2), the fault will propagate to O provided the OL is prime and irredundant.

IMPLEMENTATION OF NSL AND OL
We use m-out-of-n codes for state assignments for all submachines.The NSL of all submachines and the OL will be driven by arbitrarily encoded primary inputs and m-out-of-n encoded state lines.The NSL and OL have to be implemented such that any single stuck-at fault can only result in either single bit error or unidirectional multibit errors at the output.The implementation of the NSL of each submachine and the OL does not impose any restrictions on the type of gates used or on the minimization procedures (boolean or algebraic).The primary inputs are as- sumed fault-free.
We will first present lemmas that identify the ex- istence of bidirectional errors [11].Lemma 1" Ifthere exist two x-bidirectional (Def.3) input cubes, then a fault at input x may create a bidirectional error at the output.Lemma 2: If no two input cubes are x-bidirectional, then a single stuck-at fault at an input line can only produce a unidirectional error.Lemma 3: A fault f creates unidirectional error at the outputs for any input pattern if and only if the number of inversions from the fault site to each of the affected outputs is either even or odd but not both.
The following lemma suggests how bidirectional errors can be eliminated [11].
Lemma 4: If a combinational circuit is designed such that all faults at the inputs which create bidirectional error at the output are removed, then any fault in the circuit, internal or at the inputs, can only result in either single bit error or unidirectional multibit error at the output irrespective of the way the circuit is implemented.
If the inputs to a circuit are m-out-of-n code, then the minimum distance between two codewords is 2.
Thus, there does not exist any x-bidirectional input cubes.Consequently, no single stuck-at fault at an input line can produce bidirectional error (Lemma 2); therefore, any single stuck-at fault in the circuit can only cause unidirectional error (Lemma 4).It should be noted that for m-out-of-n input encoding, a single stuck-at-0 (stuck-at-l) at an input line can only cause a transition from 1 to 0 (0 to 1) at the outputs if only the true values of the variables are considered.
Lemma 5: If the inputs to a circuit are m-out-of-n code, then any unidirectional multiple stuck-at faults at the input lines can cause either single bit error or unidirectional multibit error at the output.
Proof: Suppose that the fault free input codeword is C. Since m-out-of-n codes are used for input en- coding, a unidirectional multiple stuck-at fault at the input will result in an invalid input codeword, C, C covers C in case of unidirectional multiple stuck-at- 0 faults, and C is covered by C in case of unidirec- tional multiple stuck-at-1 faults.If C covers C, then C cannot cover any of the input codewords.The output in this case will be all O's; thus, this multiple stuck-at fault will create unidirectional error.On the other hand, if C covers C, C might cover other input codewords.Thus, the output will be the bitwise Boolean OR of the outputs corresponding to the input codewords covered by C. In this case, only 0 to 1 error can occur at the output lines.Therefore, the error caused by the multiple stuck-at fault is unidi- rectional.O.E.D. Lemma 6: Any arbitrary logic circuit with two sets of inputs, one set (I1, I:, In) being m-out-of-n encoded and the other set (J, J_,  Jy) being arbitrarily encoded, can be implemented such that all single stuck-at fault except those at input lines J, J, Jy result in single bit or unidirectional mul- tibit errors at the output irrespective of the mini- mization scheme or the type of gates used.Proof: The circuit can be represented as in Figure 2 where O2, 02, O m are the outputs and I1, I2, In, J1, J2, Jy are the inputs (the dashed box represents the original circuit).The output expressions can be also written as functions of inputs Jla, Jib, Jya, Jyb, I1, I2, In (the solid box represents the new circuit).For two input cubes, if the distance between their arbitrarily input encoded set is 0, the minimum distance between these cubes is 2 because m-out-of-n codes are used for the second input set.Therefore, if two inputs cubes in the orig- inal circuit are x-bidirectional (Def. 3),input x has to be from the arbitrarily input encoded set.Without any loss of generality, suppose that two input cubes are Jx-bidirectional in the original circuit (Jx will be arbitrary circuit FIGURE 2 Logic circuit realization. 0in one of the cubes and 1 in the other).In the new circuit, the distance between the same two cubes will be 2 because JxaJxb will 01 in one cube and 10 in the other.In this case, bidirectional input cubes are elim- inated, and consequently any single stuck-at fault either internally or at input lines (I1, I,,... In, Jla, Jib, Jya and Jyb) produces either single bit error or unidirectional multibit error at the outputs (Lemma 4).Q.E.D. Thus, if the input lines are assumed fault-free, then the above strategy for implementing logic circuits will guarantee that any possible stuck-at fault in the cir- cuit will result in either single bit error or unidirec- tional multibit error at the output without having any restrictions on the type of gates used or on the min- imization procedures.Lemma 7: A circuit that is both fault-secure and irredundant is also self-testing, and therefore totally self-checking.
Proof: For an input pattern t, let C(t) be the fault- free output of the circuit, and let Ci(t) be the output of the circuit with fault f present.Because the circuit is irredundant, there exists input pattern such that C(t) does not equal to C,(t) for every f in the fault set.The circuit is fault secure, so for any such test t, the fact that C(t) does not equal to Cf(t) implies that Cr(t) is not a codeword.Therefore, the circuit is self-testing, and thus totally self-checking.Q.E.D.

TOTALLY SELF-CHECKING FSM
Theorem 1: Consider a state machine with I inputs, S states and N different symbolic outputs.
1.If m-out-of-n code is used for state assignment such that (,) >_ S, and 2. m-out-of-n-code for output encoding such that (,) -> N, and 3. Next State Logic (NSL) and Output Logic (OL) are implemented as suggested in Lemma 6, then this state machine will be totally self-checking.
Before we prove the theorem, we show that if the machine is in an invalid state, the first erroneous output is an invalid codeword.
Lemma 8: If a state machine is realized as described in Theorem 1, the OL will be fault-secure for any unidirectional multiple stuck-at faults at the state lines.In other words, in case of an invalid state, the first erroneous output is invalid.
Proof: an invalid state can result from either a fault in the NSL, or a stuck-at fault at the input or output of a memory element.In both cases, the faulty state and correct state are not partially bidirectional since any stuck-at fault in the NSL will result in either single bit error or unidirectional multibit error (Lemma 6).Therefore, an invalid state can be viewed as multiple unidirectional stuck-at faults at the inputs or outputs of the state flip flops (D type flip flop is assumed), which will take the machine from a correct state to an invalid state.By Lemma 5, this multiple stuck-at fault can only result in uni- directional error at the output i.e., either an invalid output codeword or the correct valid codeword will be produced.Therefore, the first erroneous output is an invalid codeword.Q.E.D.
Proof of Theorem 1: We have to prove that ma- chine is fault secure for all single stuck-at fault.For a single fault f, some input patterns may mask the fault while others may propagate its effect to the output.In the proofs of the fault-secure property in this paper, we will only consider the situation when the fault is not masked.We consider three cases: Case 1: A single stuck at fault in the OL will cause either single bit error or unidirectional multibit error at the output lines (Lemma 6).Since m-out-of-n code is used for output encoding, the output is an invalid codeword.
Case 2: A single stuck-at fault in the NSL will result in only single bit error or unidirectional multibit error at the state lines (Lemma 6).Since m-out-of-n code is used for state assignm6nt, this fault will produce an invalid state.By Lemma 8, the resulting output codeword is invalid.Case 3: A single stuck at fault at either an input or an output of a memory element will force the circuit into an invalid state, and thus produce an invalid output (Lemma 8).
Therefore, the machine will never produce a faulty but valid code word in case of a single stuck-at fault; i.e., the circuit is fault secure for any single stuck-at fault.
In order to prove that a fault-secure machine is totally self-checking we have to prove that the circuit is irredundant for all types of faults (Lemma 7).Com- binationally redundant faults (CRFs) can be elimi- nated by designing prime and irredundant (Def.9) networks for OL and NSL by using techniques proposed in Ref. [12].Sequential redundant faults (SRFs), however, require restricted logic synthesis methods.For a combinationally irredundant fault to be sequentially redundant, the faulty circuit has to be isomorphic to the fault-free circuit [9].It was proven in Ref. [9] that if NSL and OL were imple- mented such that there is even or odd number of inversions between a node (other than the primary inputs) and the primary outputs, then no fault can convert the state machine into a faulty one which is isomorphic with the fault-free state machine.Since Lemma 6 guarantees that only unidirectional errors are present in case of a single fault, then by Lemma 3, the number of inversions from any node to the outputs has to be odd or even, but not both.Thus, the proposed implementation of state machines will eliminate SRFs.Therefore, the circuit is irredundant and hence totally self-checking.Q.E.D.

TOTALLY SELF-CHECKING INTERACTING FSMs
In order to design totally self-checking interacting FSMs, the interacting machines have to be fault-se- cure and self-testing for any single stuck-at fault.The following theorem outlines the steps for designing self-checking interacting machines" Theorem 2: Given any type of decomposition with I inputs and O outputs; S1 and $2 are the number of states for submachine M1 and M2 respectively, if  1. m-out-of-n code is used for state assignments such that (m) >--S1, and (,) >-$2, and 2. m-out-of-n code for output encoding such that () -> N, and 3. Next State Logic (NSL) for each submachine and the Output Logic (OL) are implemented as suggested in Lemma 6, and 4. the schemes discussed in [10] are used to elim- inate redundant faults in the interacting ma- chines then this composite state machine will be totally self-checking for all single stuck-at faults.We will consider subcircuits resulting from each type of decomposition separately.

Parallel Decomposition
In parallel decomposition, Fig. la, each submachine operates independently.Since each submachine is realized as in Theorem 1, the composite machine is totally self-checking.Note that the OL is common for both submachines, and if at any time either of the states in M1 and M2 is invalid, the output will be an invalid codeword (Lemma 8).
Cascade Decomposition We will prove here that if the interacting subma- chines are designed as proposed in Theorem 2, they will be fault-secure and irredundant for all single stuck-at faults.We will first prove the fault-secure property for the following cases: Case 1: A single stuck-at fault in the NSL of sub- machine M1 will create a single bit error or unidi- rectional multibit error at the state lines (Lemma 6).
Since m-out-of-n code is used for state assignments, this fault will place M1 in an invalid state.The state lines of M1 are inputs to M2. Invalid input lines for M2 will place the machine in an invalid state and/or will produce invalid output since the state lines of M1 are m-out-of-n codes (Lemma 8).If the fault produce invalid output, then the circuit is fault-se- cure.However, if the fault place M2 in an invalid state, the output will be also invalid (Lemma 8).
Case 2: A fault at the input or output of a memory element in M1 will force M1 to an invalid state, and as in case 1, M2 will generate invalid output.Case 3: A fault in the OL will generate either single bit error or unidirectional multibit error at the output lines (Lemma 6).Therefore, the output is a non codeword.
Case 4: A single stuck-at fault in the NSL of sub- machine M2 will also create unidirectional errors at the state lines (Lemma 6) which will place M2 in an invalid state, thus creating invalid output (Lemma 7).
Case 5: A fault at the input or output of a memory element in M2 will force M2 to an invalid state, thus creating an invalid output (Lemma 8).
We have proved above that the circuit (submachines implemented using cascade decomposition) is fault-secure; therefore, to guarantee that the circuit is self-checking, we have to prove that none of the redundancies possible in a cascade decomposition is present (Lemma 7).Four categories of redundancies are present in cascade decomposition which were discussed in Section 2. Type 1 and type 4 which are associated with single submachines M1 and M2 are eliminated because each submachine is self-checking by itself (Theorem 1).Type 2 will not be present in this case because INT1 corresponds to the state lines; therefore, if a fault in M1 propagates to INT1 (state lines), the state lines will generate an invalid code- word (Lemma 8).Type 3 can be eliminated by meth- ods discussed in [10].CRFs can be eliminated by methods presented in [12].Therefore, a state ma- chine using cascade decomposition is fault-secure and irredundant, hence totally self-checking.Q.E.D.

Arbitrary Decomposition
In arbitrary decomposition, each submachine has in- formation about the other submachine through its state lines.The state lines of both submachines and the primary inputs feed the OL.By Lemma 8, an invalid state at either of the submachines will cause invalid output.Similar to the proofs of Theorems 1 and 2, a fault in the NSL of either submachine will cause either single bit error or unidirectional multibit error.Therefore, this fault will place the corresponding submachine in an invalid state.By Lemma 8, an invalid state will produce an invalid output.A fault at the input or out- put of a memory element will result in an invalid state thus resulting in an invalid output.Finally, a fault in the OL will also result in either a single bit error or unidirectional multibit error at the output.Thus, the decomposed circuit is fault-secure.
To prove that the circuit is irredundant, all redun- dant faults associated with arbitrary decomposition have to be eliminated.CRFs can be eliminated from NSL of each submachine and from OL, by schemes presented in [12].Six categories of redundancies are present in arbitrary decomposition as described in Section 2. Type 1, type 3, type 4 and type 6 which are associated with submachines M1 and M2 are elimi- nated since each submachine by itself has no redundant faults (Theorem 1).Type 2 and type 5 can be elimi- nated by methods discussed in [10].Therefore, the resulting cascade decomposition is fault-secure and ir- redundant, hence totally self-checking.Q.E.D.

RESULTS
We applied the proposed synthesis techniques to a set of interacting state machines formed by connecting dif- ferent MCNC benchmark state machines in cascade and in arbitrary decomposition.The NSL and OL of the decomposed submachines are implemented using multi-level logic (factored form).The number of lit- erals obtained from such realization has been com- pared to the results obtained by applying techniques that target two-level (NOVA [14]) and multi-level (MUSTANG [13]) implementations; as far as we are aware, no other state assignment and output encoding schemes are available that can be directly applied to interacting FSMs.The number of literals in multi-level realization is approximately twice the number of tran- sistors used in CMOS implementation because each literal will be an input to two transistors (one n-type and one p-type).Therefore, the results reported here (the number of literals in factored form) give a fair estimate of the area requirement for VLSI implemen- tation.
Table I shows the statistics of 10 interacting state machines which are constructed by connecting differ- ent MCNC benchmark circuits.Six of these machines are connected in cascade decomposition and the re- Cascade(M1,M2) means that the two machines, M1 and M2, are connected in cascade decomposition where M1 is the driving machine and M2 is the driven machine.The state lines of M1 are now part of the inputs to M2, and the outputs of M2 are considered as primary outputs.For example, seql is an interacting FSM constructed by cascading bbtas and bbara, where bbtas is the driving machine and bbara is the driven machine.Arbitrary(M1,M2) means that the two ma- chines are connected in arbitrary decomposition.The outputs of the interacting machine is the concatenation of the primary outputs of the two submachines.For example, seq7 has been obtained by connecting bbara and dkl4, and the outputs of seq7 are the concaten- ation of the bbara outputs and dkl4 outputs.
Table II gives the number of literals in factored form for each submachine, and for the composite machine obtained by applying our technique, MUSTANG [13] and NOVA [14], where the sum rep- resents the number of literals for the composite ma- chine.The TSC column is produced by applying Theo- rem 2 and by performing unconstrained boolean minimization using MIS [15].The results in Table II do not include the area of the latches.Table III gives the number of literals when the latches are included as well; each latch is considered to have 3 literals [16].

CONCLUSION
This paper presented a technique for making inter- acting FSMs totally self-checking for single stuck-at faults.These techniques use m-out-of-n code for state assignments and for output encoding.The NSL of each submachine and the OL are designed such that a fault can only cause unidirectional errors at the output.The overhead of these techniques when  applied to benchmarks circuits are considerably low, less than 8%.MUSTANG and NOVA try to mini- mize the 'cost' of a state machine without considering the testability problem.If scan-based techniques were used, there will be an area overhead because of scan-in circuitry, scan-out circuitry and scan flip flops.

TABLE
Statistics of the benchmark examples #inp is the number of primary inputs to the interacting machine #out is the number of primary outputs #diff_o is the number of different output patterns #state is the number of states FADI BUSABA and PARAG K. LALA maining four are connected in arbitrary decomposition.