Input / Output Pad Placement Problem

VLSI chip is a rectangular area with input/ utput (I/O) pads (we will refer to these simply as pads) arranged along the perimeter of the chip in which cells are laid out surrounded by routing channels. Cells (modules or blocks) are logic models of a rectilinear shape with a predefined internal layout. Nets are physical wires that provide interconnections between cells. They provide the physical means for logical signals to travel through. Nets are laid out on a reserved chip space known as a routing channel. I/O pad placement is the problem of placing I/O pads around a VLSI chip boundary such that it leads to a reduction in the cost of cells placement. Pad placement is typically done as the last stage in a VLSI layout design. However, some cell placement packages are sensitive to the pad placement and require such placement to be done first [1]. To solve this problem Tsay et al. [6] proposed a similar approach of Hall’s [4] by solving for the eigenvectors of the modified connectivity matrix given by the following equation.

INTRODUCTION VLSI chip is a rectangular area with input/ utput (I/O) pads (we will refer to these simply as pads) arranged along the perimeter of the chip in which cells are laid out surrounded by routing chan- nels.Cells (modules or blocks) are logic models of a rectilinear shape with a predefined internal layout.
Nets are physical wires that provide interconnec- tions between cells.They provide the physical means for logical signals to travel through.Nets are laid out on a reserved chip space known as a routing channel.
I/O pad placement is the problem of placing I/O pads around a VLSI chip boundary such that it leads to a reduction in the cost of cells placement.Pad placement is typically done as the last stage in a VLSI layout design.However, some cell placement packages are sensitive to the pad placement and require such placement to be done first [1].
To solve this problem Tsay et al. [6] proposed a similar approach of Hall's [4] by solving for the eigenvectors of the modified connectivity matrix given by the following equation.
B* B22 B21BllB12 (1) In practice, pad pair exchange produces a better and a more efficient placement.In this paper we present heuristics for pad placement.We also give some results obtained by running these heuristics over known industrial circuits.

CELL PLACEMENT
Cheng and Kuh [1] have devised a novel technique for cell placement.They have transformed the cell placement problem into the problem of minimizing the power dissipation in a resistive network.The objective function (square Let C be the connection matrix.Let c be the sum of all elements in the ith row of C. Define a diagonal matrix D such that The matrix B is defined as B=D-C (4) Further, let X r= [Xl,.X2,...,Xn] and yT= Yl, Y2,..., Yn] be the row vectors representing the x-and y-coordinates of the desired solution.Then the objective function can be rewritten as d XrBX + yrBy This representation is similar to the one for resistive networks.The placement problem is solved by ma- nipulating the corresponding network to minimize power dissipation using sparse matrix techniques.The equation for the power dissipation in a resistive network is P VTYn V (6) We find that B is of the same form as the indefinite admittance matrix Yn of an n-terminal linear resis- tive network.The coordinate x of cell is analogous to the voltage at node i.The connectivity c ij between cells and j is analogous to the mutual conductance Yij between nodes and j, and dii is analogous to the self-admittance at node i.If the given netlist contains some fixed modules, such as pads, then that will be equivalent to having voltage sources in the resistive network.In a resistive net- work, currents always distribute so as to minimize the power dissipation.The current distribution can be computed using the two Kirchhoff laws, where /31 and /3 2 represent movable and fixed modules, respectively.
Tsay et al. [6] proposed a placement technique, Proud, based on the resistive network analogy.The slot constraints are bypassed, i.e. modules are con- sidered as zero-area points and are not confined to the grid points.The method proceeds in two phases: First, slot-free placement is done by solving the linear system of equations represented by Eq. 7.Then, module shape and area are taken into consid- eration, and the chip is partitioned alternately in the vertical and horizontal directions along the cut axis.This process is repeated until each subregion con- sists of only one module.
The I/O pad placement is used as the seed for the cell placement.The final cell placement is usu- ally very sensitive to the pad placement.

PAD PLACEMENT
In practice, the chip boundary is rectilinear in shape, but to simplify circuit analysis we assume that the boundary is circular.Pads are to be placed at the boundary forming a circular ring, with neighbors equally apart from each other.In our approach, pad placement is done in two phases.First we try to find a circular ordering based on the connection graph of the circuit.Second, we try to compute the optimal rotation of that ordering.

Circular Ordering
Let the distance dij between pads and j be the shortest path length between and j in the circuit connection graph G(C, P, N), where C, P and N represent cells, pads and nets, respectively.A circu- lar ordering is a sequence for pads around a circular boundary with their relative positions preserved.
Our intuition is that distance dictates the ordering of the pads around the boundary.Pads that are graphically close to each other are more likely to occupy neighboring positions than pads that are graphically further apart.
Let the pad distance graph be a complete weighted graph, where vertices represent pads and edge weights, do., represent the length of the shortest path between pads and j in the connection graph G.Note that this graph maintains the triangu.larinequality, i.e., dij <_ dik + dkj for all i, j and k.To construct such a graph we can use a modified ver- sion of Dijkstra's algorithm [3], to compute the single-source shortest-path for each pad in the con- nection graph.Dijkstra's algorithm runs in O(N log P + C), therefore the' construction of the pad distance graph runs in O(PN log P + C).
Given a circular ordering we define the ordering length as the sum of the distances between adjacent pads in the ordering.The problem of finding a circular ordering with the minimum length is equiva- lent to finding the shortest traveling salesman tour (i.e., a closed tour that visits each vertex once and only once) in the distance graph.This problem is known to be NP-complete [5], but there exist fast approximation algorithms that find cycles with at most one and a half the optimal tour cost [2].We present an algorithm to compute a circular ordering of the pads.

Algorithm: Circular Ordering
Input: G(C, P, N) Output: circular ordering Order(P) begin 1.Construct pad distance graph D(P), dij length of shortest path between and j in G. 2. Order(P) traveling-salesman-tour(D(P))   tour-length 14 Slot-free cell placement.
Fig. 1 shows a pad distance graph for a circuit with pads a, b, c and d.Using Eq. 7 we.computed the slot-free cell placement for pads ordering (abcd) and (bacd), and we get the placement shown in Fig. 2. We note that the pads ordering correspond- ing to the shorter tour gave a better placement.

Rotation of Pad Ordering
Empirically, we have observed that a good pads ordering is not sufficient to guarantee a good cell placement.For a cell placement algorithm like Proud, the alignment of the cut-axis is also crucial to obtain a good cell placement.Given a pads ordering the angle at which the cut-axis is aligned has a major effect on the final placement.Fig. 3 shows a pads ordering with the slot-free cell placement (computed using Eq.7) and one possible, cut-axis alignment.
To show the sensitivity of Proud to the cut-axis angle, we started with a pad placement and com- puted the cell placement using Proud, then we the cell placement for successive rotations by a small angle while preserving the pads ordering (similar in effect to changing the angle of the cut-axis).Table I shows the effect of pads ordering rotation for sev- eral circuits.In each circuit we used the procedure described above.Table I shows the worst and best cell placement obtained from pads ordering rota- tion.It also shows the percentage improvement of the best over the worst case.Clearly, we can obtain an improvement of as much as 17% on the cell placement if we can tune the cut axis to the best angle of rotation.
The simplest way to find the best alignment angle for the cut-axis, can be done by incrementally rotat- ing the pads ordering around the chip boundary and taking the alignment with the minimal cell place- ment cost.Unfortunately this procedure is com- putationally expensive because it requires a small rotational increment which in turn leads to many executions of the cell placement algorithm.
To approximate the alignment angle of the cut- axis, we compute the slot-free cell placement for the pads ordering using Eq.7 (we assume that the chip boundary is circular).Note this does not involve computing the final cell placement.This gives us the optimal slot-free cell placement, where cells are t__ cut axis  Placement quality vs. tour cost.i50 allowed to move freely without being confined to the slot constraints.Usually cells would cluster near the center of the layout.We think it is best to align the cut axis with the orientation of the main cluster [Fig.3].Aligning the cut axis with the orientation of the main cell cluster attempts to align the cluster with the chip boundary [Fig.4].Therefore as the cluster expands in later partitioning steps, it fills the chip area.To compute cluster orientation we used the second moment of the cluster distribution.
Algorithm: Circular Ordering Orientation Input: G(C, P, N) & Order(P) Output: best rotation angle of Order(P) 0 begin 1.Compute the slot-free placement using the linear system of eq.
B11x -B12x2 2. 0 orientation of the main cluster.end 4. RESULTS In Section 3.1 we assumed that the quality of the final placement in Proud is dependent on the length of the circular ordering.Minimizing ordering length should lead to a better placement.To show such a relationship empirically, we randomly constructed several circular orderings for a given circuit and computed the final placement using Proud.We then constructed several circular orderings with minimum TSP tours.The placement quality versus the order- ing length was then plotted.The relationship be- tween the ordering length and the final placement is shown in Fig. 5. Clearly, Fig. 5 shows a direct relationship between the ordering length and the final placement.We can obtain as much as 17% improvement over the random pad placement.
In Section 3.2 we asserted that aligning the cut axis with the orientation of the main cell cluster in the slot-free placement would lead to a better place- ment quality.Given a circular ordering, we com- puted placements obtained by incrementally rotat- ing the ordering by a few degrees covering a full cycle.Fig. 6 shows a plot of the placement of several circuits against the angle of the cut axis.Each curve was normalized by its mean value.The curves show a periodic relationship between the placement qual- ity and the angle rotation.Table II shows statistics obtained from the pads rotation of several circuits.The standard deviation is about 5% of the mean.
Fig. 6 also shows that the filaal placement is sensitive to the angle of rotation.So we expect that alignment of the cut-axis to the orientation of the main cluster would be a crude approximation and we might test few other angles in the neighborhood of the approx- imation.

CONCLUSION
In this paper we present an I/O pad placement heuristics.These heuristics could be used as a pre- processing step for cell placement algorithms that are sensitive to the pad placement.Two heuristics were proposed for pad placement; namely, pads circular ordering and ordering angle of rotation.The combined heuristics may result in more than 20% improvement over using random pad place- ment.
Our heuristics are iterative in the sense that sev- eral pads ordering candidates (by using different TSP tours) can be used to generate good pad and cell placements. end

3 FIGURE
FIGURE Pads distance graph.

FIGURE 3
FIGURE 3 Global cell placement for a VLSI circuit.

FIGURE 4
FIGURE 4 Aligning cluster orientation with cut axis.

FIGURE 6
FIGURE 6 Final placement vs. angle of rotation.
of Euclidean wire length)