A New Theory for Testability-Preserving Optimization of Combinational Circuits

Testability should be considered as early as possible in VLSI synthesis and optimization. In most CAD tools, testability preservation is achieved as a by-product of finding a less redundant implementation. Unfortunately, this approach is not supported by theory. It is essential to have an optimization scheme that systematically preserves testability. A complete theory covering testability-preserving optimization of combinational circuits is yet to be developed.


INTRODUCTION
With increasing complexity of VLSI (Very Large Scale Integrated) circuits, the design of chips is in- creasingly dependent on CAD tools for automatic synthesis, layout, and testing.These tools reduce the time required to design needed circuits.
Synthesis tools should produce minimal or nearly minimal logic (or transistor) circuits in order to re- duce manufacturing costs 1].At the same time, it is important that the resultant circuits be testable in or- der to reliably and efficiently detect manufacturing faults [2,3].Unfortunately, as will be shown in Sec- tion 3.2 of this paper, optimization of a circuit may cause faults which were testable in the unoptimized circuit to be no longer testable in the optimized cir- cuit.
In order to support the twin goals of optimization and testability, it is useful to develop optimization techniques which preserve testability.
Usually, factorization and substitution approaches are used in gate level circuit synthesis.These techniques are presented and their features are discussed in the following subsections.The main disadvantage of factorization is that ex- traction of factors is constrained to be among vari- ables at the same level.If paths from the terms that can be extracted to the output of the circuit are drawn, it can be found that these paths must merge at the gate in the next logic level or the second logic level thereafter (in Figure l(a), the paths from two input terms "ac" to the output f merge at the OR gate in the second logic level).In general, circuits cannot be further optimized due to this limitation.This lim- itation is further illustrated in the following example.a(bcd + e) + g(bch + i)

Factorization Methods
The factorization approach [5,6,7,8,9, 10] is a circuit optimization method which uses Boolean al- gebra operations/transformations to reduce the num- ber of literals in Boolean expressions.Factorization results in a (near) minimum factored expression for a given function.Consider, for example, the function f= abc + ace + bd + de The corresponding gate-level realization of the func- tion f is shown in Figure l(a).The Boolean expres- sion of the function can be factorized into The multilevel circuit realization of this expression is shown in Figure 2.Although the two terms "bc" are in the same level in the circuit, they cannot be ex- FIGURE 2 Limitation of factorization tracted for optimization because the paths from these two terms to f merge at the next fourth level thereaf- ter.

Substitution Methods
Substitution is another method for optimizing cir- cuits.The basic idea is to find common parts (containing two or more literals) which occur two or more times in an expression, and substitute these parts with a single temporal signal line (variable).After the sub- stitution, a fan-out from the single, sub-circuit which generates a Boolean function for the common parts in the original circuit is created.By replacing the dupli- cated parts with the shared sub-circuit, gates in the circuit can be saved.A simple example is shown in Figure 3. Here, the substitution rn abc is made.
In the substitution methods, extractions are al- lowed among the signal lines (variables) in different levels, and extracted signal lines can merge in any manner.In most cases, the substituted circuits have fewer connections as well as fewer and/or smaller gates.Substitution reduces the duplication in both gates and connections.Therefore, in addition to using fewer and smaller gates, the substituted circuit uses less area for routing wires.
The main disadvantages of substitution methods is that the computing cost is higher than that of simple factorization methods.In the substitution method, there are more possible extractions available and more possible plans for substitution have to be eval- uated.
(a) The original circuit FIGURE 3 Substitution method

TESTABILITY-PRESERVING OPTIMIZATION
There are numerous possible definitions for testabil- ity.For this paper we require a specific meaning for the this term.Our definition of testability depends upon a specific fault model.We assume that all faults can be modeled as stuck-at-zero (s-a-0) or stuck-at- one (s-a-l) faults; further we assume that only one such fault exists in the circuit-under-test.Now we define testability to be the number of possible faults which cannot be detected at the primary outputs of a circuit with any vector applied to the primary inputs of the circuit.Our objective is to reduce this number, a testability measure of zero is ideal.
It is significant that circuit testability be preserved, or even improved during synthesis.In this section, the basic concepts, background, and recent research in the area of testability-preserving optimization are introduced.

Redundant Circuits and Undetectable Faults
The single stuck-at-fault model [11] is suitable for gate level circuit model of combinational circuits.This model is used in this paper.
If there exists no test vector (i.e., a given assignment to the set of inputs) which can detect some given fault + in a circuit, then the circuit is said to be redundant with respect to +.Consider the circuit shown in Figure 4.This circuit is redundant with re- spect to the s-a-0 fault on line 3, denoted as +1, since the occurrence of this fault does not change the func- tion realized at f. Thus it is tempting to just ignore such faults.However, the presence of undetectable faults can cause some detectable faults to become un- (b) The circuit after substitution X2 FIGURE 4 A redundant circuit detectable.For example, undetectable fault 1)1 can cause s-a-1 fault on line 1 to be undetectable [12].It should be noted that line 1 was detectable in the ab- sence of fault Another problem that arises in dealing with redun- dant circuits is that part of the computational effort is wasted in trying to find a test vector for an undetect- able fault.
Therefore it is advisable to remove any redundant part(s) of a circuit in the design phase itself.Unfor- tunately, for larger circuits identifying the redundant lines and gates can be a very time-consuming pro- cess.Therefore extra care needs to be taken while designing a circuit to avoid redundancy [12]. 3.2 The Relationship between Optimization and Testability X3 X abcd abce (a) gedundant in terms of optimization (b) Irredundant in terms of optimization but irredundant in terms of testing but redundant in terms of testing FIGURE 5 Two different redundancy definitions antee testability preservation.In some cases, optimi- zation may make some detectable faults in the origi- nal circuit undetectable.An example can be found in [13], as shown in Figure 6.The original circuit in Figure 6(a) is fully testable, but gate h in the opti- mized circuit in Figure 6(b) is not testable.
Generally speaking, the less redundant a circuit is, the better its testability.In other words, redundancy can be a reason that a given circuit is less testable.A circuit is optimized by reducing its redundancy.In most existing automatic synthesis systems, testability is considered only as a side effect of a less redundant implementation [10].However, this approach is supported by neither a theory nor experimental results.The redundancy con- cept in the context of circuit optimization and the redundancy definition in the context of circuit testing should not be confused.In circuit optimization, the components (gates, transistors, and lines) are said to be redundant if they can be removed, for example, through optimization, without changing the logic function realized by the circuit.Some circuits are re- dundant in terms of circuit optimization but are irre- dundant in terms of testing, see, for example, the cir- cuit shown in Figure 5(a).Some other circuits, see, for example, the circuit shown in Figure 5(b), are irredundant in the context of circuit optimization but are redundant in the context of testing.
In practice, the traditional approach, which tries to reduce the redundancy in terms of testing by reducing the redundancy in terms of optimization, cannot guar-  [4] that if a network (two-level or multilevel) is completely testable, then the net- work obtained by any of the Boolean algebraic trans- formations along with De Morgan's law is also com- pletely testable.Rajski and Vasudevamurthy gave the following definition for testability preservation.DEFINITION 1 Let N be a network and F be a trans- formation which transforms N to a network N 2. Let T be a complete test set for single stuck-at faults for N 1.We say that transformation F preserves testabil- ity, if T is also a complete test set for single stuck-at faults in network N2.The results given by Rajski and Vasudevamurthy in [4] could be summarized in the following theorem where part corresponds to Theorems 3-5 in [4], and part 2 corresponds to Theorem 6 in [4].rithm were reported in [4].However, no data re- garding the testability preservation of these results was given.THEOREM 1 (1) In factorization, the transformations along with De Morgan's law preserve testability, if the orig- inal circuit is irredundant.
(2) Resubstitution of common sub-expressions in a multi-output irredundant circuit, as shown in Figure 7, preserves testability if no two sub- expressions control the same output, i.e., X can- not reach Pi via yj, and cannot reach Pj via Yi.
Rajski and Vasudevamurthy opened a new research area.Their theory provides a systematic solution to the testability preservation problem in combinational circuit optimization.However, we have the following observations to make: 1. Applicability: Theorem 1 is only proved to be applicable to irredundant circuits.In fact, nearly half of the circuits used in the experiments in [4] were redundant, and therefore were not covered by the above theorem. 2. Comprehensiveness: Theorem 1 includes four cases used in factorization of irredundant circuits.
Other operations, for example, the sub-expression substitution shown in Figure 3, was not consid- ered.As will be shown in Theorem 3 of this paper, there is room for improvement over the above the- orem for irredundant circuits.
3. Reported experimental results: Some experi- mental results which demonstrated the efficiency in terms of optimization of the factorization algo-4.E/O APPROACH TO TESTABILITY-PRESERVING OPTIMIZATION In this section, a more general new theory for testability-preserving optimizationmE/O approachm is proposed.In the following discussion, "E" means even, and "O" means odd.

Definitions and Concepts
The denotation D from the D-algorithm [14] is used in this work.The symbol D is used to denote the situation in which a line has a value 1 in the absence of the fault and 0 in its presence.The complementary situation is denoted by D. For example, a s-a-0 fault on line x is represented as fault x D; a s-a-1 fault on line xl is represented as fault x =/).
We define the concept of testability-preserving op- timization such that it is applicable to both irredun- dam and redundant circuits.
DEFINITION 2 Let N be a network and F a transfor- mation (or extraction) which transforms N to a net- work N2, as shown in Figure 8. Suppose that trans- formation F removes the copy of fl which produces  13 (or C I3) is detectable in N 1, then single faults B' I3 (or C' 13) and M 13 will also be detectable in N2.
In order to derive the theory of testability preser- vation for optimization of redundant circuits as well as irredundant circuits, Lemma 7 in [4], which is only applicable to irredundant circuits, should be generalized to be applicable to redundant circuits as well.
Suppose that a network N is transformed to N2 in a step of an optimization sequence, where N can be redundant or irredundant.Only a part of the network N 1, namely K 1, is transformed to K2 in N2, and K1 and K2 perform the same function.We have the following lemma.
LEMMA 1 A test set T detects a fault set Sf of single stuck-at faults in N 1, outside of K 1, (Nlrl), if and only if T detects all corresponding stuck-at faults of Sf in N 2, outside of K 2, (N2Vf2), as shown in Figure 9.
The proof is similar to the proof of Lemma 7 in [4].
With this lemma, in proving the testability preservation of a transformation, it is sufficient to demonstrate that any line in K2 is testable if the correspond- ing line in K is testable.

E/O Theory
To simplify the discussion, we will assume that a given circuit is decomposed in terms of AND, OR and NOT gates unless otherwise indicated.For exam- ple, a NAND gate is decomposed to an AND gate followed by a NOT gate.The effect of a fault in a circuit may propagate to the primary output of the circuit through one or more paths.DEFINITION 3 The E/O value of a path is defined as even (or odd) if the number of inversions (i.e., in- verter gates) on the path is even (or odd).DEFINITION 4 Suppose that there exist more than one path from node n to node n 2 in a circuit.If the E/O values of these paths are not the same, i.e., some are even, while the others are odd, then it is said that there is a conflict; otherwise, we define the E/O value of the paths from n to n 2 as the common E/O value of these paths.If the E/O value from n to n2 is even, this relationship is denoted as: If the E/O value from n to n 2 is odd, this relationship is denoted as: According to Definition 4, if the E/O value of the primary output is fixed, for example, as E, then the E/O value of each node in the circuit can also be calculated unless the node is involved in conflict.The process is from the primary output towards the pri- mary inputs.During this backward scan, an E/O value is maintained until an inverting gate (NOT, NOR, or NAND) is encountered.The E/O value is updated from E to O or from O to E at the input line(s) of the inverting gate.This backward scan con- tinues until the primary input is encountered.
Example 2 Consider the circuit shown in Figure 10.To mark the E/O value of each node in the circuit, we mark the primary output line 11 as E and proceed from the primary output towards the primary inputs.
Input lines 9 and 10 of gate G5 are marked as E because G5 is a non-inverter gate.However, input lines 7 and 8 of G 4 are marked as O because G 4 is an inverting gate.The E/O value is updated again at G2 2/0 3/0 FIGURE 10 E/O values of the nodes in a circuit from O at its output line 8 to E at its input line 4.In a similar way, the rest of the nodes can be marked as shown in Figure 10.
where p is any point in the circuit.
Proof Because the functions OR and AND are monotonically increasing (or called as unate in [12,  15]), the circuit composed of OR and AND gates only is also monotonically increasing, i.e., LEMMA 3 Suppose that there is a single-path from A to x in the circuits shown in Figure 11(a)-(c).Then we have: DEFINITION 5 The arithmetic difference of a func- tion f with respect to an input x is defined as: Of JXi 1) jx 0), Ox where "-" is the arithmetic subtraction operator.

0A
0A" The meaning of Of OX 0 is that f remains un- changed due to a change in x i.Of OX 1 means that f changes in the same direction as the change in x i, i.e., when xi changes from 1 to 0 (or 0 to 1), f changes fromlto0(or0tol);0f/0x lmeansthatf changes in the opposite direction to a change in xi, i.e., when xi changes from to 0 (or 0 to 1), f changes from 0 to 1 (or 1 to 0).In terms of testing, Of OX 0 means that the effect of a stuck-at fault b on line x cannot propagate to f.If f is the only output of the circuit and Of Ox 0 for all the inputs, then + is considered undetectable.On the other hand, Of/Ox 4:0 means stuck-at fault + on line x is de- tectable.
LEMMA 2 Suppose that a circuit f consists of AND and OR gates, i.e., there are no NOT, NAND, NOR, or XOR gates in the circuit, then where "" is the multiplication operator.
Proof (1) If at least one of the inputs {x2, x 3 X of the OR gate is 1, then the effect of a fault on line A cannot propagate from A to fOR through x 1.Hence, the left hand side of Equation 1 is OfoR OA 0. On the other hand, the right hand side of Equation 1 is: x----= x 0 O. (2) The proof for Equation 2 is similar to that for Equation 1.
(3) If x is independent of A, then the effect of a fault on A cannot propagate to x and hence to fNOT, there- fore both Xx and fNOT remain unchanged, i.e.,  Proof According to the assumption, the sub-circuit K which is changed into K 2 during the substitution has only one output p. From Lemmas 1 and 4, we know that the substitution preserves testability.Q.E.D. OfNOT X OA OA Hence, Equation 3 is correct.Q.E.D In using substitution in single output redundant cir- cuits, testability can be preserved if the condition in the following lemma is satisfied.LEMMA 4 In the circuit shown in Figure 12, suppose that the E/O values of nodes B and C are the same.Then the extraction from  Proof For the proof of Lemma 4, please refer to Appendix A.
Q.E.D LEMMA 5 Consider the substitution in Figure 13.
Suppose that all paths from B and C to primary out- N1 (the entire circuit) The original circuit N.(the entire circuit) A' P f' The extracted circuit (an AND or an OR gate), as shown in Figure 14, preserves testability no matter whether the original circuit is redundant or irredundant.
Proof Each fault in K e corresponds to one fault in K except that the type of the fault is inverted.For example, a stuck-at-1 fault on line l' in K e corre- sponds to a stuck-at-0 fault on the corresponding line in K 1.Therefore, if the stuck-at-0 fault on 11 in K is detectable, then the stuck-at-1 fault on line l' in K e is also detectable.(1) First, let us consider the testability of line j in Figure 15(b).
Suppose that s-a-0 fault on line Js (or js D) in the original circuit is detectable, i.e., there exists a test pattern T such that when the input of the circuit is T1, Jt 0, R 0, and Js 1 under fault-free condi- tion.This is the condition that fault j D can prop- agate to f and be detected.Notice that Js 1 requires S= andA 1.Now, let us apply T to the optimized circuit in Figure 15(b).Because S 1 and A 1, then j 1 in the optimized circuit under fault-free condition.Furthermore, because R 0, Js D can propagate to f.Therefore, j D in the optimized circuit is detect- able.
Similarly, it can be shown that if Jt D in the original circuit is detectable, then j D in the opti- mized circuit is also detectable.
In the same way, it can be shown that if either js /) or Jt =/) in the original circuit is detectable, then j D in the optimized circuit is also detectable.
Therefore, testability of line j is preserved after optimization.gl (a) The original circuit In a similar way as above, it can be shown that if either j D or Jt D is detectable in the original circuit, then D in the optimized circuit is also detectable.
However, to detect fault /) in the optimized circuit requires that A 1, S 0, T 0 and R 0. In fact, this condition is also necessary to detect fault S =/) (or sk =/) where 1 <-k <-ns) and fault T /) (or tk =/5 where 1 <-k <-nt) in the original circuit.
In other words, if either S =/9 (or s k if)) or T =/5 (or k =/9) in the original circuit is detectable, then D in the optimized circuit is also detectable.Therefore, testability of line is preserved after optimization.
(3) Let us consider the testability of line S in Figure 5().
In a similar way as (1), it can be shown that S in Figure 15(b) is testable if S in Figure 15(a) is testable.
(4) Let us consider the testability of line A in Figure 15(b).
In a similar way as (1), it can be shown that if either line ls or in Figure 15(a) is testable, then A in (5) Let us consider lines au, Sv, and tw in Figure 15(b)   where u 1, 2 n a, v 1, 2 ns, and w 1, 2 n r Suppose that line s in Figure 15(a) is testable with test pattern T 2, i.e., the fault on Sv can propagate to f via S.In the same way, the fault on Sv in Figure 15(b) should also propagate to f via S because S is testable with T 2. Therefore, Sv in Figure 15(b) is testable.
In a similar way, it can be shown that line a in (6) Line R is unchanged in the transformation.
From ( 1) to (6), it can be concluded that double cube factorization preserves testability for redundant circuits.
Q.E.D. From Lemmas 1, 4, 6, and 7 we have Theorem 2. Theorem 6 in [4] can also be generalized for redun- dant circuits as shown in the following theorem.THEOREM 2 The following redundant circuits optimi- zations preserve testability: 1.The substitution of nodes B and C which represent the same Boolean function, as shown in Figure 13.Suppose that p is a line that all paths from B and C to all primary outputs must pass.Then the sub- stitution preserves testability if one of the follow- ing conditions is (a) B and C have the same E/O values counted from p (Lemma 4).
(b) B and C do not control the same primary out- put.
2. The extraction of NOT gates as shown in Figure 14 (Lemma 6).
If the original circuit is irredundant, i.e., fully test- able, then substitutions of nodes with opposite E/O values also preserve testability, as stated in Lemma 9 below.Before showing Lemma 9, we need to intro- duce Lemma 8.
LEMMA 8 Consider the substitution in Figure 12.Suppose that all paths from B and C to f meet only at E 0 f, and B --> f, and C -f.The substitution preserves testability, if at least one of the following conditions is satisfied: 1. Gate f is an AND gate, and single faults B D and C D in the original circuit are detectable.
2. Gate f is an OR gate, and single faults B ) and C D in the original circuit are detectable.
Proof Please refer to Appendix B.

Q.E.D.
LEMMA 9 Consider the substitution nodes B and C in an irredundant circuit.Suppose that p is a line that all paths from B and C to the primary output f must pass.Then the substitution preserves testability if there is no conflict in the E/O values on paths B --> p and C --> p, i.e., one of the following conditions is satisfied: 1. B and C have the same E/O values counted from p.
2. B and C have the opposite E/O values counted from p.
Proof Case 1 is the direct result from Lemmas 4 and 1. Case 2 is the direct result from Lemmas 8 and 1.
Q.E.D. Lemma 9 can be generalized for multi-output cir- cuits, as stated in Part 1 of Theorem 3. THEOREM 3 The following optimizations of irredun- dant circuits (single-output or multi-output) preserve testability: 1.The substitution of nodes B and C which represent the same Boolean function, as shown in Figure 13.Suppose that p is a line that all paths from B and C to all primary outputs must pass.Then the sub- stitution preserves testability if one of the following conditions is satisfied: (a) All paths from B to p have the same E/O value; and all paths from C to p have the same E/O value (Lemma 4).(b) B and C do not control the same primary out- put.
2. The extraction of NOT gates shown in Figure 14 (Lemma 6).
It should be noted that all the cases in the theorem due to Rajski and Vasudevamurthy (Theorem 1 in Section 3.3 of this paper) represent special cases of Theorem 3. In addition, Theorem 3 covers more cases for both single-and multi-output circuits.

Application of E/O Theory
First, let us show the algorithm that verifies the con- ditions in Theorem 2(1) and Theorem 3 (1).Any com- binational circuit can be represented as a DAG (Directed-Acyclic Graph) in which nodes correspond to AND, OR, or NOT gates.The directed edges in a DAG correspond to connections among gates.The in-coming edges to a node represent the connections with the inputs of the gate, and the out-going edge represents the output from the gate.More than one out-going edges from a node represent a fan-out.OUTPUT: True, if at least one of the conditions is satisfied; False, otherwise.

METHOD:
1. Extract the subgraph Go from the DAG of C SO that G O contains only all the paths from B and C to all the primary outputs {f/}.
2. Mark each node in Go as PB and/or Pc if it is on a path from B and/or C to a primary output.
3. Denote node set NBc {nln is marked as both Pn and Pc}. 4. IF Nnc is empty, THEN RETURN True. 5. Denote node set Np {nln N,c, no node directly connected with the input of node n be- longs to Nnc}.Based on Theorems 2 and 3, the following algorithm is proposed.This algorithm can perform gen- eral optimizations that are testability-preserving even if the circuits to be optimized are not fully testable.The basic idea of the algorithm is that in addition to the extraction of factorization, as that in [4], sub- functions in different levels are also substituted.
Algorithm 2: Factorization and substitution on re- dundant and irredundant circuits INPUT: An initial circuit C having a cost cl.
OUTPUT: An optimized circuit C2 having a cost c 2 such that c 2 C1, and C 2 preserves the testability of C1.
Algorithm 1: Checking testability-preserving con- ditions for substitution INPUT: The original circuit C and candidate nodes B and C for substitution.

METHOD:
Perform the testability-preserving optimization on the circuit until no further optimization can be made as follows.
1. Find factorization Planfact with the maximum saving in the number of literals in the expression (or transistors in the circuit) using single-cube, double-cube, or dual expression extraction.
2. For each node pair x and y which represent the same Boolean function, check whether one of the testability-preserving conditions is satisfied by using Algorithm 1. Find substitution Plansubs with the maximum saving in the num- ber of literals in the Boolean expression (or transistors in the circuit).
3. Compare the saving in the number of literals in the expression (or transistors in the circuit) of Planfact, and Plansubsr If the savings are all 0, then exit; otherwise denote the plan with the maximum saving in the number of literals in the expression (or transistors in the circuit) as Plan.

EXPERIMENTAL RESULTS
TPOS can optimize circuits using both factoriza- tion and substitution as described above.It can also check the E/O values of the nodes to be optimized.If the option in TPOS which indicates optimization of redundant circuits is set, then only nodes with the same E/O values are eligible for optimization.
FAN [16] is a fast test generation system for VLSI circuits.In this paper, the fault-simulation part of FAN is used to measure the testability of circuits.It should be pointed out that the fault collapsing tech- nique 12, 3] is used in FAN.This technique reduces the number of faults that need to be considered in order to completely test a given circuit.However, with fault collapsing, the fault simulator in FAN gives the number of faults after collapsing instead of the real number of existing faults.Therefore, in the experimental part of this paper, the fault collapsing part of FAN is disabled so that we can observe the actual number of undetectable faults in the circuits simulated.A program, named TPOS (Testability-Preserving Optimization System), which implements both Algorithm 1 and Algorithm 2 is coded in about 5000 lines of C and run under Unix on a Sun Sparc 2 workstation.The purpose of developing TPOS is mainly to verify the validity of the theory proposed in the paper.
The program TPOS has been used to test twenty-five examples including the circuits used in [9] and the benchmarks distributed by the Microelectronics Center of North Carolina (including the ISCAS'85 set) [17, 18].The number of signal lines in a circuit is roughly equal to the number of transistors in the circuit.Min- imizing the number of transistors in the circuit is used as an optimization criterion in TPOS.In the results listed in this paper, the number of the gates in some circuit may increase after optimization because the number of the gates is not selected as the optimization goal in TPOS.
Table I lists data for irredundant circuits optimized by TPOS.By comparing the last two columns of the table, it is clear that the optimized circuits are also irredundant.In other words, optimization preserves the testability for the irredundant circuits.
Table II lists data for redundant circuits optimized by TPOS.By comparing the number of undetectable faults of the original circuits and that of the optimized circuits, it is clear that the optimized circuits have the same or better testability than the original circuits.The types (stuck-at-0 or stuck-at-I) and the locations of undetectable faults in the original and the optimized circuits were compared (not listed in the table due to space limitation).It was found that the type and location of undetectable faults are the same ex- cept that some undetectable faults in the original cir- cuit were removed because the lines on which these undetectable faults occur were removed.
Circuit optimization may affect the test generation so that the test generation program needs more CPU time for the optimized circuits, or it may need more test vectors to test the optimized circuits.These problems are not considered in the proposed theory.However, by comparing the data for test generation listed in Table III, the average CPU time cost for FAN to generate test patterns and the average number of test patterns needed drop after the circuits were optimized with testability preservation.In other words, because the scales of circuits (i.e., the number of components and the number of signal lines) are optimized, CPU time for test pattern generation can be saved, and it generally needs fewer test patterns to test smaller or simpler circuits.

CONCLUSIONS AND OPEN RESEARCH TOPICS
In this paper, a new theory for testability-preserving optimization of combinational circuits is established.According to this theory, in a redundant or irredun- dant circuit, substitutions which satisfy one of the conditions described in part 1 of Theorems 2 and 3, double-cube factorization, and extraction of NOT gates preserve testability, no matter whether the cir- cuits have single-or multiple-output.
The theory proposed allows us to design a more generalized optimization algorithm which preserves testability for both redundant and irredundant cir- cuits.This algorithm uses both factorization and sub- stitution methods.The experimental results reported show that both irredundant and redundant circuits preserve testability after being optimized using the proposed algorithm.
There are some improvements to be done on the theory and the algorithm proposed in this paper.For example, the theory may be generalized to be appli- cable to a functional block level model.
The fact that circuit optimization may affect the test generation is not considered in the proposed the- ory.The theory only guarantees that no new undetect- able faults in the optimized circuit are created, but it cannot guarantee that the cost of testing and test generation does not increase.In the context of DFT (De- sign For Testing) [3] [19], testability is defined as the ease of testing or as the ability to test easily or cost- effectively 19].To preserve the testability in the con- text of DFT during optimizing is another open re- search topic to be studied.
x 2 0 will conclude that B D cannot propagate to f, i.e., is not detectable.The conflict proves that x 2 1.) Now, let C change from to 0 such that the situa- tion of the circuit is equivalent to the effect of fault M o o D. Because Cf, i.e., C --> x 2, from Lemma 13, 3x 2 we know that {0, 1}.Therefore, x 2 will not OC change from 1 to 0, but will remain at 1. Hence, f(M=D)lt,=f(B =DC=D)I,,=D Therefore, any fault which can be represented as M D is detectable.
Similarly, from C =/), it can be shown that M /) is detectable.

Example 1
Consider the following Boolean expression.

FIGURE 6
FIGURE6 Optimization may make some faults undetectable

FIGURE 9
FIGURE 9 Transformation of redundant/irredundant networks FIGURE 11 Illustration for the properties of gates The extracted circuit (c) Merging point is AND gate (d) Merging point is OR gate

FIGURE 12
FIGURE 12 Substitution procedure

FIGURE 13
FIGURE 13 Substitution procedure

Q
ano 81$ 8no alas aria tlt tm (a) The original circuit (b) The circuit after factorizafion FIGURE 15 Double cube factorization LEMMA 7 tion, i.e., Double cube extraction using factoriza-f=AS+AT+R A(S + T) + Ras shown in Figure15, preserves testability for re- dundant circuits, where A a a2...ana, S S S 2 Sns and T 1, 2 tn,.Proof We will prove that every line in the optimized circuit in Figure15(b) is testable if the corresponding line in the original circuit in Figure15(a) is testable.During the transformation, lines Js AS and Jt AT in Figure15(a) are removed, while new lines S + T and j A in Figure15(b) are created.

Figure 15 (
Figure 15(b) is testable if any au in Figure 15(a) is testable, and line in Figure 15(b) is testable if tw in Figure 15(a) is testable.

6 .
FOR each n Np DO (a) Calculate the E/O values of B and C, re- spectively.(b) IF conflict occurs THEN RETURN False.
(c) IF C1 is redundant, and B and C have oppo- site E/O values THEN RETURN False. 7. RETURN TRUE.

5. 1
Design of the Experiment 5.2 Explanation of the Experimental Results If fault B D (or C D) is detectable in N 1, then single faults B' D (or C' D) and M D will also be detectable in N 2, and 2. If fault B C, and creates fan-out point M connected with B' and C'.It is said that transformation (or extraction) F pre- serves testability, if the following conditions are The test data and the experimental results are listed in Table I ar/d TableII.

TABLE II The
Redundant Circuits Optimized by TPOS

TABLE III Test
Generation for the Circuits Optimized