A Novel Path Delay Fault Simulator Using Binary Logic

A novel path delay fault simulator for combinational logic circuits which is capable of detecting both robust and nonrobust paths is presented. Particular emphasis has been given for the use of binary logic rather than the multiple-valued logic as used in the existing simulators which contributes to the reduction of the overall complexity of the algorithm. A rule based approach has been developed which identifies all robust and nonrobust paths tested by a two-pattern test , while backtracing from the POs to PIs in a depth-first manner. Rules are also given to find probable glitches and to determine how they propagate through the circuit, which enables the identification of nonrobust paths. Experimental results on several ISCAS’85 benchmark circuits demonstrate the efficiency of the algorithm.


INTRODUCTION
There has always been an increasing demand for faster digital systems.The maximum allowable clock frequency in a synchronous system is determined by the propagation delay of a signal in the combinational network between the latches.Due to some physical defects, statistical process variations or stray capaci- tances, if the delay of the manufactured network ex- ceeds specifications, there is a chance of unstabilized and possibly incorrect logie values being latched at the outputs.Delay fault testing can be used to ascer- tain that manufactured digital circuits meet their tim- ing specifications and operate correctly at desired clock rates.Thus, delay fault testing has achieved great theoretical and practical importance for the de- sign of high-speed logic circuits.In this paper, we have presented a novel path delay fault simulator for combinational circuits which detects the faulty paths under the application of two-pattern test pairs.A delay fault only causes logic values to respond slower than the normal which leads to the malfunctioning of the logic network.Unlike a stuck-at fault, a delay fault does not affect the steady state logical operation of a system, but it affects the timing behav- ior of the system and degrades the overall system performance.From the operational point of view, a combinational logic system is said to be free of delay faults if the transition (rising or falling) initiated at the primary inputs (PIs) arrives at the primary outputs 168 A.K. MAJHI, J. JACOB and L. M. PATNAIK (POs) in less time than the system clock timing spec- ifications.
In the recent past, two different fault models have been proposed in literature, viz, the gate delay fault model and the path delay fault model.The gate delay fault model as described in [4,7,12,16] was also re- ferred as transition fault model.In this model, the lumped gate delay fault is localized to a particular gate input or output.This is also analogous to dc stuck-at fault model, i.e., the slow-to-rise and slow- to-fall transitions correspond to the dc stuck-at zero and stuck-at one respectively, since it behaves a stuck-at zero or stuck-at one temporarily [16].However, it does not model the cumulative effect of the gate delays along a path from the PIs to POs.On the other hand, the path delay fault model [3,6,14,15]  alleviates this deficiency.In this model, the delay fault is associated with a physical path in the circuit and the path is declared to be free of delay faults if the transition provoked at the input propagates to the outputs through the specified path in less time than the operational system clock interval.Thus, the path delay fault model provides the advantageous capabil- ity of modeling the distributed failures which are mainly caused by statistical process variations and physical defects during the manufacturing process.
There is a major bottleneck in selecting the paths for which the test generation and fault simulation are to be carried out, since as the circuit size grows the number of paths grow exponentially with circuit depth and the number of fanouts.Hence, prior to test generation and fault simulation process it may be necessary to focus on a subset of all possible paths in the logic network.There are several methods avail- able in literature like worst-case path selection and threshold-based path selection [9], and a polynomial time algorithm to find a minimum cardinality path set has been described in [5].
During the last few years, a considerable number of test generation methods for path delay faults have been developed [3,6,8,9,13], whereas the problem of fault simulation has only been addressed in a few [2,11,14,15].Smith [15] has proposed a six-valued logic, which identifies the paths tested for delay faults independent of the delays of any individual gate in the network.Schulz et al [14] have presented a four- valued logic for an accelerated fault simulation approach for the delay faults, which applies parallel processing of patterns at all stages of the calculation procedure.Bose et al [2] have used Smith's six- valued algebra for delay fault simulation of synchro- nous sequential circuits.Pomeranz et al [11] have used a non-enumerative method to estimate path de- lay fault coverage.Similarly, multiple-valued logic has been used for the test generation process of the delay faults; e.g., eleven-valued logic in [7], ten- valued logic in [3,8], and five-valued logic in [6,9].The number of logic states used is a factor that deter- mines the time and memory complexity of the algo- rithms based on them; fewer logic symbols lead to less complex implementations [6].Hence, we have employed the simple two-valued logic for path delay fault simulation.
During event-driven logic simulation with respect to the first vector (initialization vector) of the two- pattern test < V 1, V 2 >, we evaluate the gate sensitiv- ity, and classify the gate inputs as controlling (CO) and noncontrolling (NC) based on the logic values on them.After evaluating the true logic values with re- spect to the second vector (propagation vector) using the same event-driven approach, the possibility of a glitch event at the output of a gate is determined tak- ing both the initialization and propagation vectors into account.An event-queue is also maintained for the propagation of the glitch events from PIs to POs in order to determine the robustness/nonrobustness of a path.Finally, we backtrace from the POs to PIs in a depth-first manner based on some specified rules to trace the faulty paths.Thus, our algorithm detects both robust and nonrobust paths during the simula- tion procedure.Additionally, the program can also count the total number of all possible paths in the network.We have not used any of the path selection algorithms mentioned earlier to create a target path list from the enormous number of possible paths.Once a path is detected as faulty by a vector pair, it is added to the global path list to keep track of the fault coverage.

THEORETICAL BACKGROUND AND BASIC DEFINITIONS
Hardware Model and Clock Timings Unlike a single pattern test as used in case of dc stuck-at fault testing, delay fault testing requires a two-pattern test <V, V2>.Considering the well ac- cepted hardware model as described in literature [3,6,8,13,15] illustrated in Fig. 1, we assume that the initialization vector V is loaded into the input latches at time o After the signals of the network get stabi- lized under V, the propagation vector V 2 is applied at time t by activating the clock C. Finally, the logic values are sampled from the output latches at time 2 t + by pulsing clock C2, where represents the desired system clock interval.The main objective of delay fault testing is to ensure that the maximum propagation delay of a path in the circuit is less than the system clock interval c.

Robust and Nonrobust Paths
Robust path: A structural path P in the logic net- work can be termed as a robust path with respect to a two-pattern test <V, V2>, iff, a transition provoked at the input to the path prop- agates to output through the structural path P.
it is guaranteed that all signals on the structural path P cannot attain their final values with respect to the propagation vector V 2 of the two-pattern test <V, V2>, unless the provoked transition at the in- put has arrived at them.
A delay fault in the robust path will cause a faulty logic value at the output of the path independent of other path delays in the network.The corresponding vector pair which detects the faulty robust path is defined as a robust test.
Nonrobust Path" A structural path P in the logic network can be termed as a nonrobust path with re- spect to a two-pattern test <Vl, V2>, iff, a transition is provoked at the input of path P by the test <V l, V2>. the excessive delay on path P can be detected by the two-pattern test <V, V2> under the assumption that there does not exist any other faulty paths in the network.In other words, the propagation vector V 2 causes all off-path sensitizing inputs [9,14] along the structural path P to assume their noncon- trolling values to propagate the provoked transition at the input.
The corresponding vector pair which detects the faulty nonrobust path is termed as nonrobust test.
Fig. 2 illustrates the two-pattern test <V, V2> con- sisting of the initialization vector V (11110) and the propagation vector V2 (11010).The structural path P1 (C-E-I-J-L-N-Q) is referred as a robust path with respect to the test <V1, V2>, since all lines in the path P1 cannot attain their final values unless the transition provoked at input C arrives at them.The structural path P2 (C-E-I-J-L-M-P) is referred as a nonrobust path with respect to the test <V1,V2>, because an excessive delay in the rising transition on line H may cause the PO (line P) to have its expected true final logic value at the sampling time t as shown in Fig. 2(b), regardless the delay on path P2.
Thus., it leads to the conclusion that the circuit is fault-free, although there are delays on both lines H and L, M. But if there is no delay on line H as shown  in Fig. 2(c), we will get the faulty logic value 0 at the PO (line P) at the sampling time 2. Thus, path P2 can be detected as a nonrobust path with respect to the test pair <V 1, V2>, iff there is no delay on line H.

Sensitivity and Gate Evaluation
During event-driven logic simulation with respect to the initialization vector of the two-pattern test <V1, V2>, we classify each gate into the following classes: Globally Sensitive (GS): A logic gate with all in- puts at noncontrolling (NC) value is classified as a GS gate.Noncontrolling values are 1(0) for AND/ NAND(OR/NOR) gates.
Potentially Sensitive (PS): A logic gate with at least one input at controlling (CO) value is classi- fied as a PS gate.Controlling values are 0(1) for AND/NAND(OR/NOR) gates.
Odd-Parity Sensitive (OPS): A logic gate whose output is complemented when an odd number of inputs have events is classified as an OPS gate, e.g.XOR/XNOR gates. (We have restricted the OPS gates to two input gates only throughout our dis- cussion.) Input Sensitive (IS): A logic gate with single input is classified as IS gate, since output is comple- mented by complementing the input.Inverters/ Buffers are IS gates.

PATH DELAY FAULT SIMULATION USING BINARY LOGIC
In order to perform the path delay fault simulation with respect to the given two-pattern test vector, we follow the procedures given below: While doing event-driven logic simulation with re- spect to the initialization vector V1 of the two-pat- tern test <V1, V2>, the gate sensitivity (i.e.GS, PS, OPS, IS) as well as the controlling (CO) and non- controlling (NC) inputs of the gates are determined based on the rules specified in the previous section.
An example of the same has been given in Fig. 3, where we have taken the test pair <V1, V2> as (11110,11010).The gate inputs having a star (*) represent the CO inputs with respect to the initial- ization vector V 1.
Secondly, event-driven logic simulation is per- formed with respect to the propagation vector V2 and the true final logic values are evaluated.Along with the logic simulation we additionally check for the possibility of a glitch event at the gate output.
An example showing the generation of a glitch at the gate output is shown in Fig. 4.There are both rising and falling transitions at the inputs of the AND gate.According to the rules of event-driven logic simulation, we do not have a logic event on the output of the AND gate.However, this condi-

Glitch Generation
Rule 1: If the gate is PS, all CO inputs have events and exactly one NC input has event, then output will have a glitch as shown in Fig. 5(a).Rule 2: If the gate is OPS and both inputs have events, then output will have a glitch as shown in Fig. 5(b),(c).
tion can cause a glitch event at the gate output, if the falling transition at the NC input is delayed with respect to the rising transition on the CO in- put.Hence, we put the fanouts of this gate into the event-queue in order to propagate the glitch event towards the POs.The existence of a glitch helps us to determine the robustness/nonrobustness of the path.We have developed a set of rules to accu- rately model the generation and propagation of a glitch and these are explained in the next section.After evaluating the true logic values with respect to V2, we perform glitch propagation (for those glitch events which were scheduled in the previous step) in an event-driven manner towards the pri- mary outputs.Finally, we backtrace from the POs to PIs in a depth-first manner to determine the faulty paths (both robust as well as nonrobust) based on some specified rules which are explained in a following section.

GLITCH GENERATION AND PROPAGATION
In order to determine the robustness/nonrobustness of a path, we need to check for the possibility of a glitch event at the gate output.It is also required to deter- mine whether the glitch can propagate to the primary outputs or not.Only gates whose output does not have a logic event need be considered for glitch generation and propagation.We have developed a set of simple rules that govern the generation and propagation of the glitch event as stated below: Glitch Propagation Rule 3: If the gate is GS or OPS, a glitch on any input will propagate to the output as shown in Fig. 6(a),(b).Rule 4: If the gate is PS, exactly one CO input has a glitch, all other CO inputs (if more than one CO input present) have events and no NC input has event, then the glitch on the CO input will propa- gate to the gate output as shown in Fig. 6(c).We do not restrict the presence of glitches on the NC in- puts.
Rule 5: If the gate is IS, the glitch on the single input will propagate to the output as shown in Fig.

6(d),(e).
Illustration: Fig. 7 shows the generation of glitch events at lines I and J according to Rules and 2 respectively.The glitch events are then propagated towards primary output based on the Rules 3, 4 and 5 mentioned above.Finally, the path (E-G-M-P) can be detected as a nonrobust path (based on the Rules de- scribed in the next section) under the test (011100, 101010). [b] [c] Our strategy in identifying robust and nonrobust paths detected by a vector pair is to backtrace from POs to PIs in a depth first manner and mark each input of gates along the path as robust or nonrobust based on a set of simple rules.Once we reach a PI, we have identified a path and it is classified as a robust or nonrobust path depending on the status of the lines along the path.Backtrace employs a recur- sive procedure and to start with, a PO having an event is marked as robust and a PO with glitch is marked as nonrobust.A gate is declared robust (non- robust) if its output is robust (nonrobust).Now the following rules are applied to compute the robust/ nonrobust status of the inputs of a gate.
Rules for Evaluating the Inputs of a Robust Gate Rule 1: If the gate is PS, all CO inputs are marked as robust and all NC inputs with glitches are marked as nonrobust.
Rule 2: If the gate is GS, exactly one input, say input j, has event and no other input has a glitch, then input j is marked as robust.If at least one input (except j) has a glitch then input j will be marked as nonrobust.
Rule 3: If the gate is OPS, the input with event is marked as robust if there is no glitch on the other input; else both inputs are marked as nonrobust.
Example 1: Fig. 8 illustrates the logic underlying Rules 1-3 for determining the robust and nonrobust inputs of a robust gate.In Fig. 8(a), the output D of AND gate (of type PS) has an event and has been marked as robust.The controlling inputs A and B with rising transition (0 ---> 1) will be marked as ro- bust, since the path delay fault on these inputs can robustly propagate to output D. The delay fault on input C (i.e., glitch ---> 0 ---> 1) can be propagated to output D, if there is no delay on inputs A and B. Thus, input C is marked as nonrobust and Rule is justi- fied.
Example 2: In Fig. 8(b), the output D of the OR gate (of type GS) has an event and has been marked as robust.The input B having a rising transition (0 ---> 1) will be marked as robust, since the delay fault on this input can be robustly propagated to output D. But the same input B will be marked as nonrobust as shown in Fig. 8(c), since there is a glitch (0 --> ---> 0) on input A. The glitch on A may cause the true final logic value on output D at the sampling time and the delay fault on B may go undetected.The delay fault on B can propagate to output provided there is no delay on input A and thus B is marked as nonrobust satisfying Rule 2. Again, if there are more than one input of the GS gate having events, then none of the inputs will be marked as robust, because the delay fault on one input will be masked by the transition on the other input causing the gate output to have its true final logic value at the sampling time.
Example 3: In Fig. 8(d), the delay fault on input A of the XOR gate (of type OPS) can robustly propa- gate to output C and thus it is marked as robust.In Fig. 8(e), the delay fault on A can be masked by the delay fault on B (i.e.glitch --> 0 ---> 1) and vice versa.As a result the output can have its true final logic value at the sampling time though there are de- lay faults on both inputs.The delay fault on one input will propagate to the output provided there is no de- lay on the other input and thus both inputs A and B are marked as nonrobust satisfying Rule 3.   Rules for Evaluating the Inputs of a Nonrobust Gate Rule 4: If the gate is PS and output has a glitch, then the single NC input having event is marked as nonrobust provided all CO inputs have events.
Again, the single CO input with a glitch is marked as nonrobust if there is no event on other NC in- puts.If the gate is PS and output has event, all CO inputs having events as well as all NC inputs with glitches are marked as nonrobust.Rule 5: If the gate is GS and output has a glitch, all inputs with glitches are marked as nonrobust.If the gate is GS and output has event and exactly one input, say input j, has event, then input j is marked as nonrobust (independent of the presence of glitches on other inputs).
Rule 6: If the gate is OPS and output has event or glitch, then input with event or glitch is marked as nonrobust.
Example 1: Fig. 9 illustrates the logic behind Rules 4-6 for determining the nonrobust inputs of a nonro- bust gate.It is to be noted that the inputs of a robust gate can be marked as robust as well as nonrobust l whereas the inputs of a nonrobust gate will be only nonrobust.In Fig. 9(a), the output D of the AND gate (of type PS) has a glitch and has been marked as nonrobust.The delay fault on the single NC input C can propagate to the output if all CO inputs have events and there is no delay fault on any one of the CO inputs.Thus, input C is marked as nonrobust.In Fig. 9(b), the glitch (0 ---> ---> 0) on the CO input A can propagate to output D, if there is no event on other NC inputs and thus input A is marked as non- robust.In Fig. 9(c), the output D has been marked as nonrobust though it has an event. (This possibility has been explained in the previous example used for illustrating Rules 1-3).Referring to Fig. 9(c), the de- lay fault on inputs A and B can robustly propagate to output D, but these inputs will be marked as nonro- bust since output D is nonrobust.Again, input C hav- ing a glitch (1 ---> 0---> 1) will be marked as nonrobust as explained earlier and thus Rule 4 is justified.
Example 2: Consider the case when the output of the GS gate has a glitch and has been marked as nonrobust.The delay fault (i.e., glitch) on any input will propagate to the output.An example is given in Fig. 9(d) in which input A has a glitch and thus marked as nonrobust.In Fig. 9(e), the output C of the GS gate has an event and has been marked as nonro- bust.The delay fault on input A having event will robustly propagate to output C independent of the presence of glitch on other input B and thus A will be marked as nonrobust since the output C is nonrobust satisfying Rule 5.
Example 3: Consider the case when the output of an OPS gate has a glitch and has been marked as nonrobust.The delay fault on any input having a logic event or a glitch event can propagate to the output.Thus, inputs A and B having logic events will be marked as nonrobust as shown in Fig. 9(f) and input B having a glitch event will be marked as non- robust as shown in Fig. 9(g).If the output of the OPS gate has an event and has been marked as nonrobust, then the delay fault on the input having a logic event will propagate to the output.In Fig. 9(h), the input A having a logic event will be marked as nonrobust and hence Rule 6 is justified.
Rules for Evaluating the Input of an IS Gate Rule 7: If the gate is IS, its input is marked as robust (nonrobust) provided the output is robust (non- robust).
Illustration: Fig. 10 shows an example circuit where we have applied Rules to 7 while backtrac- ing from POs to PIs and determined the status of each line.We have applied the two pattern test (110, 101) at the inputs of the logic circuit and propagated the logic events as well as the glitch events through the circuit.Finally, the output P will have a logic event (0 1) whereas the output Q will have a glitch event (1 0 1).Hence, the output P will be marked as robust and Q as nonrobust.First, we backtrace from FIGURE 10 Example of Robust & Nonrobust Path Detection the robust output P towards primary inputs in a depth first manner.The inputs G and M of the AND gate (of type PS) will be marked as robust based on Rule 1. Backtracing along the line G, the stem line F will be marked as robust since its fanout branch G is robust.The input C of the XOR gate (of type OPS) will be marked robust based on Rule 3 and thus primary in- put B which is a stem line for C, will also be marked as robust.After reaching the primary input B, we found a path (B-C-F-G-P) which is robust since all the lines along the path have been marked as robust.Next, backtracing along line M, the stem line L will be marked as robust.The inputs H and J of the XOR gate (of type OPS) will be marked as nonrobust based on Rule 3. Backtracing along the line H, the stem line F (which has already been marked as robust) will be marked as nonrobust.The input C of the XOR gate will be marked as nonrobust based on Rule 6 and thus the primary input B will also be marked as non- robust.Hence, we found another path (B-C-F-H-L- M-P) which is nonrobust since some of the lines along this path have been marked as nonrobust.Next, backtracing along the line J, the stem line I will be marked as nonrobust.The input D of the AND gate (of type PS) will be marked as nonrobust based on Rule 4 and thus the primary input B will also be marked as nonrobust.Hence, we found another path (B-D-I-J-L-M-P) as nonrobust.After enumerating all the paths whose output converge on P, we then back- trace from the nonrobust output Q.The input K of the NAND gate (of type PS) will be marked as nonrobust based on Rule 4 and thus the stem line I will also be marked as nonrobust.Backtracing again, the input D will be marked as nonrobust according to Rule 4 and the stem line B will also be marked as nonrobust.Thus, we found another path (B-D-I-K-Q) as nonro- bust, and now all robust and nonrobust paths detected by the vector pair (110, 101) have been enumerated.As shown in Fig. 10, we have used the following notation to mark the status of a line, e.g., a line is denoted as r which is only robust, nr which is only nonrobust and rnr which is both robust as well as nonrobust.Thus, we conclude that 1. a line can be robust as well as nonrobust with respect to different paths.
2. a functional path will be robust iff all lines of the path are marked as r or rnr. 3. a functional path will be nonrobust iff at least one of the lines on the path is marked as nr.

SIMULATION RESULTS AND CONCLUSIONS
We have implemented the proposed path delay fault simulation algorithm in the C language (about 1500 lines of code) on an IBM RS-6000/580 computer sys- tem running UNIX.Table I shows the number of pri- mary inputs, primary outputs, number of levels in the circuit and total number of physical paths for the IS- CAS'85 combinational benchmark circuits.The CPU times for counting the number of paths have been included in Table I.We have not enumerated the path lists.Path counting was carried out as described in [11 ].The number of logical path delay faults modeled is equal to twice the number of physical paths present in a circuit since both the rising and falling transitions are considered at the input of each path.The number of logical path faults varies from 17284 for circuit c880 to 197.88 1018 for circuit c6288.
In order to derive a set of deterministic delay fault test vectors for use in simulation we have employed S. Patil's test generator [9] on the ISCAS'85 bench- mark circuits.In Table II, the total number of paths generated by worst-case path selection procedure [9]   is given in column Examined.The number of two- pattern test vector pairs generated are given in the column Vectors.Table III shows the delay fault simulation results generated by our fault simulator implementation on the same circuits.We have simulated three sets of vector pairs to detect both the robust and nonrobust paths for all circuits.The first row of each circuit shows the simulation results of the deterministic test pattern pairs for path delay faults (denoted as dpd) obtained from Table II.In our simulation procedure, we use the second pattern (propagation vector) of the present simulation as the first pattern (initialization vector) for the next simulation.Hence, we get 2n-1 vector pairs where n is the number of deterministic vectors generated, which are given in Table II.The second row in Table III for each circuit shows the simulation results of the deterministic test patterns obtained for stuck-at faults and these are denoted as dsa.The deterministic test patterns for single stuck faults were obtained using COMPACTEST[10] and these had complete coverage of all non-redundant stuck faults.The third row for each circuit shows the simulation results for random test patterns.
In our implementation, once a faulty path is de- tected by a test vector pair, it is added to the global path list of detected paths provided the path does not already exist in the global list of detected paths.The circuit c6288 was not simulated for nonrobust paths since the number of nonrobust paths detected were extremely large and it did not complete within rea- sonable CPU time.Hence, the CPU time mentioned for this circuit is the time taken only for detecting the robust paths.We have not imposed any restriction on the path lengths.All faulty paths detected by the test patterns are added to the global path list.
Table IV shows the overall statistics.The simula- tion results of circuit c6288 has not been considered for the statistics in Table IV since we have not con- sidered the nonrobust paths for this circuit.It is to be noted that the number of robust paths detected per vector pair by dpd patterns are greater than that of random patterns.For example, 291 dpd test patterns detect 318 robust paths whereas 5000 random pat- terns detect only 71 robust paths for circuit c499 and 1011 dpd test patterns detect 2002 robust paths whereas 5000 random patterns detect only 1069 ro- bust paths for circuit c880 as given in Table III.On an average the number of nonrobust paths detected per vector pair by dsa patterns is greater than that of dpd patterns since dpd patterns were obtained using the deterministic test generator generating only ro- bust tests.As shown in Table IV, the per vector cov- erage of nonrobust paths by dsa patterns is 102.72 whereas that of dpd patterns is 15.32.For example, 45 dsa patterns detect 819 nonrobust paths whereas 65 dpd patterns detect only 278 for circuit c432 and 94 dsa patterns detect 13625 nonrobust paths whereas 127 dpd patterns detect only 1476 nonrobust paths for circuit c1355 as shown in Table III.On the whole the per vector coverage by dsa patterns is better than that of dpd and random patterns for both robust and nonrobust paths as shown in Table IV.We believe that our novel path delay fault simula- tor which uses the simple two-valued algebra will be faster and require less memory than the existing sim- ulators, since the computational complexity is drasti- cally reduced in our approach.Further, it is not nec- essary to have a look-up table as required in the mul- tiple-valued logic evaluation. FIGURE2

FIGURE 5
FIGURE 5 Rules for Glitch Generation

TABLE III
tic test patterns for stuck-at faults.(r)-random test patterns.