HYSIM : Hybrid Fault Simulation for Synchronous Sequential Circuits

The paper identifies the inefficiencies of the critical processes in concurrent fault simulation and proposes methods to remove such inefficiencies in a systematic manner. Also, proposed are dynamic memory usage reduction strategies for concurrent fault simulators. Through extensive step-by-step experimentation, we verified the effectiveness of the proposed methods for performance improvement and identified best memory management strategy for dynamic memory usage reduction. A simulator, HySim, based on the proposed methods is implemented and shown to outperform the existing fault simulators and achieve dramatic memory usage reduction. The HySim maintains fault lists which are subsets of that of a conventional concurrent fault simulator, which yields shorter fault list processing time and reduced dynamic memory usage. It also employs Release-and-Reconstruct method for fault list construction, where any fault list identified to be useless is released immediately. The experimental results show that Release-and-Reconstruct method is very effective in dynamic memory usage reduction.


INTRODUCTION
Fault simulation algorithms for synchronous sequen- tial circuits which have appeared in the literature can be categorized as follows: 1) serial fault simulation, 2) deductive fault simulation, 3) concurrent fault sim- ulation.Serial fault simulator simulates a good ma- chine and faulty machines one by one.Even though it is a straightforward way of simulation, it is impracti- cal for simulating a large number of faults because it would consume an excessive amount of CPU time [1].Deductive fault simulator [4] simulates a good circuit explicitly and determines detected faults by deduction.It processes all faults at the same time.Although deductive fault simulation is capable of 2-value and 3-value fault simulation, its use for 3-value simulation is complex and inefficient.Thus, deductive fault simulation method is a poor choice for circuits where some of the inputs may be unspecified.Such is the case for sequential circuits, where the values of some of the storage elements may re- main unspecified for a long duration of a test se- quence.Concurrent fault simulator [22] simulates a good circuit and all faulty circuits concurrently.How-ever, only gates of a faulty circuit whose status (values on inputs and output of a gate) is different from that of the good circuit are explicitly simulated.Thus, it can perform 2-value as well as 3-value fault simu- lation equally efficiently.Concurrent fault simulation is often used as a reference fault simulator for performance comparison.
In recent literature some very efficient fault simu- lators have been reported.Three such simulators are 1) Differential fault simulator, 2) PROOFS,and 3) PARIS.Differential fault simulation [12] is a varia- tion of serial fault simulation technique.Like serial fault simulation, after simulating the good machine, it simulates faulty machines, one by one, for each time frame.When it finishes simulation for each time frame, it stores only the state differences between the previously simulated and the the current simulated machines.This increases the simulation efficiency in terms of storage and processing time.PROOFS [11] is an extension of parallel fault simulation method [21].In each time frame it simulates a set of faults determined by the word size of the host computer.The techniques used by a Differential fault simulator are also incorporated to further improve the performance.Another efficient fault simulator HOPE [20], also based on parallel fault simulation, was reported in the literature.PARIS (PARallel Iterative Simula- tor) [16] is an extension of parallel pattern single fault propagation simulation (PPSFP) method [3].A number of test patterns are grouped based on the word size of the computer and a good machine is simulated for all these patterns.Following this, each faulty machine, one at a time, is also simulated for the group of patterns.A detected fault can not be dropped until the group of patterns is simulated.
Even though concurrent fault simulator is often used as a reference fault simulator for measuring the performance of a new fault simulator, the performance of the concurrent fault simulator itself is heavily dependent on the implementation.In this pa- per we propose an efficient fault simulation method for synchronous sequential circuits, which is a hybrid of concurrent and deductive fault simulation techniques.The basic concept is to identify inefficiencies in a conventional concurrent fault simulator and re- move them systematically.In a concurrent fault sim- ulator, fault lists are implemented using linear linked lists and traversal operation on these lists is an inef- ficient and costly operation.A concurrent fault simu- lator also tends to use much memory since it must simulate good and all faulty machines simulta- neously.Even though the differential representation of the good machine and a faulty machine is a salient feature of a concurrent fault simulator, its memory usage is often very high compared to other fault sim- ulators.Thus, in order to improve the performance of a concurrent fault simulator, methods should be de- veloped to process the fault lists efficiently and re- duce the memory usage to minimum possible.HySim successfully fulfills these two goals.HySim also uses efficient representation of primitives using BDD-like representation and simplifies the fault deletion of fault descriptors associated with detected and con- verged faults.
In section 2, critical operations which cause ineffi- ciencies in concurrent fault simulation are identified.Methods to overcome these inefficiencies and new approaches to improve the performance of fault sim- ulation are described in section 3. Methods of mem- ory usage reduction to be investigated are described in section 4. Section 5 contains the experimental re- sults and the discussion.The conclusion follows in section 6.

CRITICAL OPERATIONS IN CONCURRENT FAULT SIMULATION
The performance of a fault simulator is measured by elapsed CPU time and its memory usage.Thus, the research efforts in fault simulation have been directed towards reducing the CPU time and the memory us- age.In this section, we identify several critical oper- ations which are related to fault list processing and cause inefficiencies in a concurrent fault simulator.

Fault Deletion of Detected Faults
Fault dropping is the deletion of detected faults from the fault list.Even in diagnostic applications, where simulation is used to build a fault dictionary, detected faults can be deleted from the fault list [5, 9].Thus, for deletion of faults the fault descriptors associated with the detected faults should be deleted from the data structure of the fault simulator.Here, the fault descriptor is an element of fault list associated with each gate.It represents the faulty gate, and holds the faulty gate specific informations such as fault index, input and output values and a pointer to the next fault descriptor.By deleting fault descriptors of the de- tected faults, the number of fault descriptors that are to be simulated is reduced.When and how to delete fault descriptors of detected faults is critical to the performance of a concurrent fault simulator.This problem was also identified by Gai et.al. [15]

Removal of Converged Fault Descriptors
This process is a little more complex than fault dropping.A fault descriptor is said to be converged if its status (input values and output value) becomes iden- tical to that of the corresponding good gate.Note that the gates of a faulty circuit whose status is identical to the corresponding gates in the good circuit need not be simulated by a concurrent fault .simulator.On the other hand a converged fault descriptor should be deleted because its non deletion can lead to erroneous results as explained below through two different ex- amples identifying two possible scenarios.
Let us consider the circuit in Figure 1.Suppose this is a subcircuit embedded in a larger circuit.With a pattern T1 in which xdefg 11000, the fault x/0, which represents line x stuck-at 0, is excited and propagated to the input to the gate p, but it is not observed at p.With a pattern T2, in which signals x and e change, the fault is converged, i.e., the good value is same as the stuck-at value.Notice that even though the logic event dies at m, fault descriptors of x/0 must be deleted from all the gates marked in Figure (b) including gates m and n.If this fault descriptor is not deleted, it may later get propagated to the primary output and the fault may falsely be declared as detected.Thus, all occurrences of fault descriptor must be removed when the fault descriptor at the fault site is converged.If the fault was propagated through multiple fanouts, the concurrent fault simu- lator must find all occurrences of a converged fault descriptor along the fanout branches.This selective deletion operation requires searching of the con- verged fault descriptor inside the fault lists associated with many gates in all possible paths from the con- verged fault site.We now examine another situation which demon- strates that not all fault descriptors must be removed and in certain instances a more careful examination of the situation is required.Consider the situation shown in Figure 2. In this circuit the fault g/0 is prop- agated to a gate through more than one path.Sensi- tized paths are shown by bold lines.If the fault is converged at the fault site, all fault descriptors asso- ciated with the fault on the sensitized paths should be removed as in the first example.However, when a sensitized path is broken in the middle due to a con- trolling value on an input of a gate in a sensitized path, the fault propagated through multiple paths may or may not converge.In the circuit of Figure 2, a change in the value of c does not cause convergence g/0 of g/0 at gate k, but will require deletion of g/0 from all gates on the path from gate h to gate k.Thus, deletion operation must determine whether the fault descriptor propagated through multiple paths should be deleted or not.This can only be determined by the actual simulation of the fault descriptor.Our experi- ence with most test sets indicates that such an occur- rence is rare, nonetheless it should be handled cor- rectly by the fault simulator in order to get the correct result.

Memory Usage
In concurrent fault simulation, only the gates of the faulty circuit whose status is different from the corre- sponding gates in the good circuit are explicitly sim- ulated.Even though differential representation of faulty circuits in concurrent fault simulation appears very efficient, it cannot handle very large circuits be- cause of limited memory and large number of faults in such circuits.Figure 3 (a) and (b), taken from [13], illustrate methods of representing faulty circuits us- ing linear linked lists in concurrent and deductive fault simulators respectively.Concurrent fault simu- lator keeps a fault descriptor in the fault list associ- ated with a gate whenever its status different from the good gate status.Thus, even if the output of the good and the faulty gate are identical the corresponding fault descriptor is entered in the list.In a deductive  fault simulator, on the other hand, only the fault de- scriptor whose output value is different from the good is entered.We call a fault descriptor whose output value is identical to the output value of a corresponding gate in the good circuit an invisible fault descrip- tor (invisible fault in short) and fault descriptor whose output value is different from the output value off the corresponding gate of the good circuit a visi- ble fault descriptor (visible fault in short).Thus, con- current fault simulator has visible and invisible faults at each gate output while deductive fault simulator has only visible faults at each gate output.It follows that in this representation a deductive fault list is a subset of the concurrent fault list, and concurrent fault simulation requires more memory than deduc- tive fault simulation.Furthermore, each fault descriptor in concurrent fault simulator requires more mem- ory than deductive fault simulator because it has to store gate status information.

List Traversal
In a concurrent fault simulator, fault list for a gate is implemented as a linked list and is attached to the associated good gate.Individual fault descriptor in the fault list can be accessed by traversing the fault list.In order to increase the efficiency of the search process, the list is usually sorted in increasing (or decreasing) fault index order.This facilitates fault de- scriptor insertion due to fault divergence, fault de- scriptor deletion due to fault convergence, and fault descriptor evaluation.Detected fault identification also requires fault list traversal at primary outputs.Since the list traversal is an expensive operation, we must avoid redundant or unnecessary list traversals.Furthermore, since the list traversal time is directly proportional to the length of the list, it is beneficial to have shorter fault lists if possible.Typically a concur- rent fault simulator maintains longer fault lists than deductive fault simulation, which in turn requires longer fault list traversal time.

METHODS OF REMOVING INEFFICIENCIES
In the previous section, we identified inefficiencies associated with critical operations in concurrent fault simulation.Below we describe a number of methods which can be used to improve the efficiency of a con- current fault simulation for synchronous sequential circuits.

Release-and-Reconstruct Method for Fault List Update
Causes of inefficiency related to the removal of faults were identified in section 2.1 and 2.2.An efficient way of handling these problems is required to im- prove the performance of a concurrent fault simula- tor.We also indicated in the previous section that the problem of deletion of detected faults was noticed by Gai et.al. [15] as well.They experimented with var- ious methods of fault dropping and proposed an asyn- chronous fault dropping method.Asynchronous fault dropping method deletes fault descriptors of a de- tected fault only when the associated fault lists are accessed and can be used for synchronous as well as asynchronous design.Their method marginally but demonstrably improved the performance of the sim- ulator.However it suffers from two drawbacks.First, it requires more memory than necessary and second the performance is dependent on the test order which determines the activation of fault lists.
No efforts seem to have been made to remove the inefficiencies associated with deletion of converged fault descriptors.Our method concentrates on the de- letion of converged fault descriptors.It reinitializes the data structure of the concurrent fault simulator before each test vector simulation.Fault list must be updated according to the fault divergence and fault convergence whenever a new test vector is simulated.Updating can be done in two ways.The first method is to insert a new fault de- scriptor in the fault list whenever the associated fault diverges; and to delete an existing fault descriptor from the fault list whenever the associated fault con- verges.This method involves linear search operation in fault lists for the insertion and deletion of fault descriptors.This search operation is a rather ineffi- cient operation.The second method is to delete the complete fault list associated with the gate before processing it and reconstruct the fault list.Reconstruction can be done mainly by append operation which is efficient.Thus, this method avoids expensive linear search operation and substitutes it by a list de- letion and append operation.We call the first method a Modification method and the second method a Release-and-Reconstruct method.
Release-and-Reconstruct method has been found to be more effi- cient than Modification method [18].Further, Release-and-Reconstruct method can be implemented with very little overhead with multi-list traversal (MLT) [14].MLT traverses the fault lists at inputs and output of a gate at the same time, thus, it can avoid unnecessary fault list traversals.All fault sim- ulators developed for experiments and described in this paper use Release-and-Reconstruct method.
Time of deletion of fault lists that use Release-and- Reconstruct method is critical from the memory us- age point of view because memory allocated to all fault descriptors associated with the deleted fault lists are returned to the memory pool for recycling.Memory management strategies for concurrent fault simu- lators described in section 5 of this paper are related to this aspect.

Rank Order Simulation 3.3. Delayed Fault Descriptor Construction
Event driven method is a well established and com- monly used method in simulation and fault simula- tion.However, the overhead of queue manipulation in event driven fault simulation often offsets the effi- ciency of it when the number of events becomes large.It is reported that an event driven simulation performs relatively poorly when the circuit activity becomes over 1% [23].In event driven fault simula- tion for sequential circuits, an event is initiated by a primary input change, fault insertion, fault deletion due to fault divergence or convergence and state vari- able change.When multiple faults are to be processed simultaneously as in concurrent fault simulation, the sources of events increase tremendously since each fault can cause fault insertion, fault deletion and state change independently.Table I shows the percentage of list events in ISCAS 89 circuits during concurrent fault simulation.The activity is obtained by the for- mula # fault lists processed activity 100.# vectors # gates This table gives a measure of high activity in concur- rent fault simulation.Thus, rank order simulation, where the circuit is levelized and the gates are processed in the level order, is a suitable choice for the concurrent fault simulation if the combined activity of the good and faulty circuits becomes high.
Fault descriptor can be constructed at the time when the first input difference is identified.This method requires updating of the fault descriptor if difference for other input occurs later, thus requiring unneces- sary list traversals.Figure 4 shows an example which requires more than one list traversal.In Figure 4 (i) the fault list at the input a is processed, and fault descriptor x is propagated to the output of the gate and a new fault descriptor x is formed in the fault list at the output c.In Figure 4 (ii) the fault descriptor at the input b is also to be propagated to the output of the gate, the fault list at the output is traversed again to access the fault descriptor x and update its status.If we delay fault descriptor construction at output un- til all input fault lists are processed as shown in Fig- ure 5, we can avoid unnecessary list traversals.This can be achieved using MLT [14] by traversing all fault lists at inputs and output at the same time and construct a fault list at the output of a gate and eval- uate each fault descriptor when it is constructed.Thus, one MLT is sufficient for construction and eval- uation off a fault list at each gate output as opposed to two separate MLTs, i.e., evaluation MLT and propa- gation MLT [14].When combined with rank order simulation, this method does not need fanout infor- mation for fault effect propagation, which in turn simplifies the data structure.During fault simulation, the gates can be evaluated in various ways.method in use.Table lookup method requires packing operation and separate tables for different gate types.Further, the number of inputs that can be handled is restricted by the table size, and for the gates which have more inputs, multiple table lookups may be nec- essary.Another method is an iterative bit operation using bitwise AND, OR, and NOT instructions.It is the most efficient method when bit-level parallelism is utilized as in PPSFP/PARIS or parallel fault simulation/PROOFS.BDDs (Binary Decision Diagram) are known to be very efficient for circuit simulation [2,8].We can use BDD-like structure for gate value evaluation in con- current fault simulation.Figure 6 shows the BDD for an n-input gate with controlling value c and inversion parity i.If an input has a controlling value c left branch is taken, otherwise right branch is taken.At each node a flag is set if the input has X (unknown) value.At controlling leaf C, the gate value is c i.For AND, OR gates is 0 and for NAND, NOR and NOT gate is 1.At the non-controlling leaf NC, we must check the flag if any of the input traversed was X.If so, the gate value becomes X, otherwise it be- comes e i.The experimental results given in sec- tion 5 justify the use off this method in our simulator.

Visible Fault Only Fault List
Concurrent fault simulation explicitly simulates a faulty gate whenever its input status (input values) and/or output status (output value) are different from good gate.Thus, typical concurrent fault simulators keep the fault descriptor in the fault list whenever its input and/or output values are different from good gate irrespective of its visibility.Note that invisible faults never propagate forward.Thus, deletion of in- visible faults does not affect the correctness of the fault simulation.By deleting such faults from each fault list, we can shorten the fault list size, and thus reduce list traversal time and memory requirement.Better yet is not to construct the fault descriptors for the invisible faults at all, since visibility of the fault descriptors can be determined before construction.
Notice that this is similar to deductive simulation which maintains only the visible faults in its fault list at each gate.However, the method is different from deductive fault simulation in the sense that fault list processing does not rely on set operations.All faulty machines and good machine are processed concur- rently as in concurrent fault simulation even though fault lists look like that of deductive fault simulation.

METHODS FOR MEMORY USAGE REDUCTION
Concurrent fault simulator is known to use more dy- namic memory than other fault simulators.Usual techniques to cope with memory usage problem of concurrent fault simulation is to use memory pool for internal memory allocation for fault descriptors and fault set partitioning to reduce the number of faults that can be handled in each run.In this section, we will present the methods for reduction of dynamic memory usage.The methods are classified into two categories, i.e., memory management strategies and data representation strategies.

Memory Management Strategies
In this section, we investigate three memory manage- ment methods for Release-and-Reconstruction of fault lists.These are i) Lazy Method ii) Synchronous Method and iii) Eager Method.We explain these methods by introducing the concept of population map.As explained earlier, simulator essentially de- letes, modifies and/or creates fault lists for different gates in the circuits.The population map is a pictorial representation of the circuit state during simulation.In the population map representation the circuit is divided into shaded and white areas.Gates in the shaded area of the population map may have associ- ated fault lists, and gates in the white area have no fault lists associated with them.Note that white areas can occur because fault lists associated with gates in this area may have been released. 4.1.1.Lazy Method Lazy method releases a fault list whenever the fault list is activated for update, and then constructs a new fault list.This process is repeated for each fault list to be updated.Lazy method does not release fault lists unless it has to, i.e., it tries to hold fault lists as long as it can.In this strategy, fault lists have a maximum life span.Conventional concurrent fault simulators use minor variations of this strategy.Figure 7 shows the population maps during the fault simulation that employs the Lazy method.Two sequences of maps shown in the figure correspond to the population maps for the consecutive test vectors.For the first test vector, the simulation starts with all white area in the population map since there is no fault lists built in the beginning.As the fault simulation proceeds, fault lists are created.Thus, shaded area grows and fills up the population map as shown in the three population maps shown in Figure 7 (a).For the second test vec- tor, nearly all the population maps are shaded throughout the fault simulation because the fault lists built for the first test vector are retained by this method.This is shown in Figure 7 (b).The small white box in each picture represents a gate for which the associated fault list is deleted and reconstructed after the evaluation of the gate.As the fault simula- tion continues, the white box moves through all the gates in the first level and then all gates in the second level, and so on until all gates and their associated fault lists are processed.The population maps for the third and the subsequent test vectors change in the pattern similar to that for the second test vector. 4.1.2.Synchronous Method Synchronous method was used to solve the problem of fault dropping and invalidated fault deletion [18].In [18] this method is referred to as a Total Synchro- nism method and it was shown that this method not only handles the fault deletion problem "nicely", but also reduced the dynamic memory usage to a small degree.Gai et.al. [15] also noticed the fault deletion problem associated with fault dropping, but they did not focus on the memory usage issue.Synchronous method holds fault lists until fault lists associated with all gates and flip-flops are processed for a test vector.After the fault simulation is completed for a test vector, fault lists at all flip-flops are updated first, and then all fault lists except those at flip-flops are deleted.The deletion of fault lists can be done very efficiently.The lifespan of fault lists in Synchronous method is shorter than the Lazy method.Figure 8 shows the population maps during the fault simula- tion that employs the Synchronous method for the two consecutive test vectors.As before, the simula- tion starts with all white area in the population map and proceeds to construct fault lists for each gate as shown in Figure 8 (a).Thus, the population map is all white in the beginning, partially filled with shaded area in the middle and is all shaded in the end.For the second test vector, the simulation starts with a strip of shaded area in the beginning.This shaded area represents the flip-flops in the circuit, for which the associated fault lists are updated.As simulation proceeds, the shaded area grows and fills up the population map just like for the first test vector.This is shown in Figure 8 (b).For the third and the subse- quent test vectors, the population map changes like that for the second test vector.

Eager Method
This method releases fault lists as soon as it is deter- mined that the fault list is no longer needed.Each fault list maintains a reference counter.Whenever the fault list is accessed, the reference counter is incre- mented.If the number in the reference counter is same as the number of fanouts of the associated gate or flip-flop, the fault list is released immediately.Thus, in this method fault lists exist only as long as they are useful for simulation.Therefore, the fault lists in this method have the shortest life span among the three methods described.Figure 9 shows the population maps during fault simulation that employs the Eager method for two consecutive test vectors.For the first test vector, the fault simulation starts with all white area like the other two methods.However, as the simulation proceeds, it releases the fault lists as soon as they are found to be eligible for release.Thus, shaded area is generated as the new fault lists are created and the white area is generated as the used fault lists are released.So, the white area on the left side of the shaded area represents the gates whose fault lists are constructed and released.And the white area on the right side of the shaded area represents the gates that are not processed yet.In the end, fault lists are only at the gates that feed flip-flops.This progression is shown in Figure 9 (a).For the second test vector, the fault simulation starts with the fault lists at the gates that feed the flip-flops as shown in the picture marked "beginning" in Figure 9 (b).As beginning Gates middle (a) maps for the first test vector end beginning middle end (a) maps for the first test vector beginning middle end i i !!i i i i l i !! !!i i i i .i i i i ii i i i i i .i l the fault simulation proceeds, all fault lists in the shaded area are processed and then released.This in turn causes shaded area as shown in the picture marked "middle" in Figure 9 (b).As explained ear- lier, white area on the left of shaded area implies that all gates in that part have been processed whereas the gates in the white area on the right of shaded area remain to be processed.Finally the shaded area moves to the right as shown in the picture marked "end" in Figure 9 (b).The above process repeats for the third and the subsequent test vectors.
Clearly the fault lists in the Eager method have the shortest lifespan among the three methods.Also the size of the shaded area in the population map does not grow bigger than the other two methods throughout all three stages for each test vectors.On the other hand, the population map for the Lazy method is al- ways filled up with shaded area for the second and the subsequent test vectors.And the shaded area in the population map of the Synchronous method grows and fills up the population map for every test vector.This implies that the Eager method holds smallest fault lists at any moment.Based on these arguments, we expect the Eager method to achieve the lowest memory usage.

Data Representation Strategies
In the previous section we proposed three memory management strategies.These strategies deal with the release of old fault lists.In this section we describe an efficient method of representing fault descriptors and a method to minimize the information in each fault list.Together these methods help reduce the dynamic memory usage in concurrent fault simulation for synchronous sequential circuits even further.

Simplified Fault Descriptor Representation
While forming the fault descriptors in the fault list associated with each gate, input values can be packed into a word (Input Status Word) and stored in each fault descriptor [19].However, the packing of input values into status is a computationally expensive operation.Further, this is a redundant information since all these values can be obtained from the fault lists associated with the driving gates.If we do not use table lookup method for gate evaluation, we need not store input values for each fault descriptor in the fault list.Thus, by not storing input values in fault descrip- tors, we can reduce the size of individual fault de- scriptor in the fault list.Also, we can eliminate writ- ing redundant information.Reduced fault descriptor size reduces the dynamic memory usage accordingly.
Figure 10 shows the structures of a conventional and a simplified fault descriptor.A conventional fault de- scriptor must contain fault index, input status, output value and pointer fields in its structure whereas a sim- plified descriptor need only contain the fault index, the output value and the pointer fields.Assuming fault index, input status and pointer take 4 bytes and output value takes byte, a conventional fault de- scriptor requires 13 bytes of memory while a simpli- fied fault descriptor requires only 9 bytes of memory.Thus a simplified fault descriptor is 31% more effi- cient in memory usage.In a typical concurrent simu- lator a major part of memory is indeed associated with fault descriptors, hence simplified representation of fault descriptors is likely to reduce the memory requirement substantially.

Visible Faults Only Fault List
In section 3.4, Visible Faults Only Fault List method was proposed for performance improvement of a current fault simulator.It was also mentioned that the length of the fault list is the same as that of deductive fault simulation.By not storing invisible faults in a fault list, the fault list length can be kept to its mini- mum and the memory usage is also reduced.

IMPLEMENTATION OF THE PROPOSED METHODS AND EXPERIMENTAL RESULTS
A series of different experiments were conducted step by step to determine the effectiveness of the methods proposed in the previous sections.First set of exper- iments was conducted to prove the effectiveness of Release-and-Reconstruct method used to solve the fault deletion problem mentioned in section 2. The other proposed methods were verified in the succes- sive experiments.All fault simulators for these experiments were written in the C language and were run on SPARCstation 2 under Unix environment.

Verification of Release-and-Reconstruct Method
We implemented three concurrent fault simulators which solve the fault deletion problem in three differ- ent ways to compare their relative performances.
These are 1) FSim_l" Conventional concurrent fault simulator 2) FSim_2: Concurrent fault simulator with asyn- chronous fault dropping [15] 3) FSim_3: Concurrent fault simulator with Release- and-Reconstruct method (Section 3.1) For comparing the performance of the simulators the ISCAS combinational benchmark circuits [6] and a subset of ISCAS sequential benchmark circuits [7] were used.The characteristics of the circuits are sum- marized in Table II.
The performance of the concurrent fault simulators for ISCAS combinational and sequential benchmark circuits is summarized in Table III.The table also contains the number of test patterns in the each test set used for simulation and the corresponding fault coverages of these test sets.Relative performances of FSim_2 and FSim_3 with respect to FSim_l are also given in the table.The relative performance of FSim_2 is included here to verify and prove the claims made by Gai et.al. [15].It is evident that the Asynchronous Fault Deletion method implemented in FSim_2 improves the performance of a concurrent fault simulator (between 1% to 31% ), but such an improvement is only marginal compared to the im-  provement obtained by FSim_3.From Tables III it is evident that FSim_3 achieves 45% to 169% performance improvement over FSim_l for combinational circuits and its improvement for sequential circuits is 20% to 102%.FSim_3 improvement in performance over FSim_2 is between 16% and 136% for all the benchmark circuits.On the average FSim_3 is faster than FSim_l and FSim_2 by 69% and 59% respec- tively.This experiment proves that the Release-and- Reconstruct method implemented in FSim_3 is very effective for solving fault dropping and converged fault deletion problem.

Verification of Rank Order Simulation and Delayed Fault Descriptor Construction
A second set of experiments was conducted to deter- mine the efficiency of the methods proposed in the section 3.2 and section 3.3.We built another fault simulator called FSim_4.Features included in the simulator are listed below.
Table IV shows the elapsed CPU times of FSim_4 for selected ISCAS 89 sequential circuits.The perfor- mance of FSim_4 is consistently better than that of FSim_3 for all ISCAS sequential circuits tested.From the table, it is evident that the two methods incorporated in FSim_4 are very effective in improv- ing the performance.
5.3 Verification of BDD-Like Gate Evaluation and Memory Management Strategy Experiment Based on the results obtained in the section 5.1, we devised memory usage experiments as explained in the section 4.1.The three memory management strat- egies, Lazy, Synchronous and Eager methods will be investigated in the following experiment.The experiment is to establish the best memory management strategy among the three strategies described in sec- tion 4.1.Note that the memory management strategy used in FSim_4 in section 5.2 is Synchronous method.We implemented three concurrent fault sim- ulators.These are.
Since it is clear that Simplified Fault Descriptor takes less memory space than conventional fault de- scriptor, all fault simulators implemented for the ex- periments employ Simplified Fault Descriptor pro- posed in section 4.2.1.To verify the effectiveness of BDD-Like Gate Evaluation, we incorporated the method into GSim_l, GSim-2 and GSim_3.For com- paring the memory usage of the simulators a subset of ISCAS sequential benchmark circuits [7] were used.The characteristics of the circuits are summa- rized in Table II.
Table V contains the dynamic memory usage of the simulators on the subset of ISCAS sequential circuits for test vectors obtained from STG-3 [10].It showed that GSim_2 uses almost same amount of dynamic memory as GSim_l in most cases.The improvement of GSim_3 over GSim_l or GSim_2 is dramatic.The memory requirement of GSim_3 for the large circuits is as little as 14% of the memory requirement of GSim_l.Considering all the circuits memory re- quirement of GSim_3 was between 14% and 47% of the memory requirement of GSim_l.This proves the superiority of the Eager method over the Lazy and the Synchronous methods.We also obtained elapsed CPU times of GSim_l, GSim_2 and GSim_3, and included the measured CPU times in Table V.By comparing the performances of GSim's to that of the FSim' s, it is obvious that BDD_Like Gate Evaluation achieved big performance improvement.However, it is observed that there is no significant performance differences between GSim_l, GSim_2 and GSim_3.

Verification of Visible Fault Only Fault List Method
We claimed in the previous sections 3.5 and 4.2.2 that Visible Faults Only Fault List would achieve both performance improvement and memory reduction.In order to prove this claim we built three fault simula- tors, called HySim_l, HySim_2 and HySim_3.Fea- tures included in each of these simulators are listed below.
HySim_l" GSim_l + Visible Fault Only Fault List HySim_2:GSim_2 + Visible Fault Only Fault List HySim_3" GSim_3 + Visible Fault Only Fault List Visible Fault Only Fault List method evaluates a fault descriptor before creating it.If the calculated value is different from that of the corresponding good gate, a fault descriptor is actually created and appended to the fault list associated with the gate.Oth- erwise, the fault descriptor is not created at all.In other words, it stores only visible faults in a fault list like deductive fault simulation.Thus, we call the fault simulator HySim (Hybrid Fault Simulator).We tested the fault simulator for the same set of sequential cir- cuits and test vectors.Table VI shows the memory usages of HySim' s.Comparing Table V and Table VI, it is clear that the Visible Faults Only Fault List method achieved substantial improvement in memory usage reduction.For example, the memory require- ments of HySim is 47% to 81% of the memory re- quirements of GSim_3.This implies that consider- able number of fault descriptors in a fault list are invisible faults which need not be stored in a fault list.
We obtained test vectors generated by FASTEST  17] for a larger subset of ISCAS sequential circuits.We ran HySim_l, HySim_2 and HySim_3 for those test vectors.Table  VII shows the characteristics of the circuits tested,the number of test vectors, fault cover- age obtained and memory usages for the fault simu- lators.The results are consistent with the results for the test vectors from STG-3.That is, HySim_l uses about same amount of dynamic memory as HySim_2.Whereas HySim_3 uses the least dynamic memory among the three fault simulators.
We measured elapsed CPU times of HySim_l, HySim-2 and HySim_3 to compare the performance.For comparison we obtained the results of PROOFS, a well-publicized state-of-the-art fault simulator.The Table VIII shows the results of HySim_l, HySim_2, HySim_3 and PROOFS for ISCAS sequential circuits for the test vectors generated by STG-3 [10].Perfor- mance of HySim_l, HySim_2 and HySim_3 was found to be nearly identical for all the circuits used in our study.In all three cases the system memory was very large.We believe that for extremely large cir- cuits that may require even larger memory space HySim_3 is likely to perform better than HySim_2 and HySim_3.However, HySim_l, HySim_2 and HySim_3 performed substantially better than GSim_l, GSim_2 and GSim_3 for all circuits tested, and all HySim's achieved better performance than PROOFS.We also ran HySim_3 and PROOFS for the test vectors obtained from FASTEST [17].Table IX shows the ISCAS sequential circuits run for the test vectors from FASTEST and the results of these runs.We could not run PROOFS for s641, hence the entry is left blank for PROOFS in the Table IX.Note also that HySim_3 and PROOFS have different fault coverages for some circuits such as s208.It is be- cause PROOFS enumerates and collapses faults inter- nally while HySim does not.HySim accepts the fault list provided by a user.From the Table IX, it is evi- dent that HySim_3 outperforms PROOFS for the test vectors obtained from FASTEST for all circuits tested.Further, from the performance data given in circuit   IX we can conclude that with the exception of three small circuits, HySim_3 runs between two to three times faster Than PROOFS.HOPE [20] claimed to be more efficient than PROOFS though it was based on parallel fault simu- lation not on concurrent fault simulation.HOPE achieved similar speedup to HySim over PROOFS.We could not directly compare the performance of HySim with that of PARIS [16], for PARIS is not available to us for running on our machines under similar conditions.

CONCLUSION
We have identified critical operations which cause in- efficiencie in conventional concurrent fault simula- tors and proposed several methods for performance improvement and dynamic memory usage reduction.A number of fault simulators based on concurrent fault simulation were implemented which incorporate one or more proposed methods.Through step-by-step experiment, we proved the effectiveness of the proposed methods.A fault simulator, HySim_3 which  Fault coverage for s208, s386, s420, s838, s1488, s1494 and s9234 are different for PROOFS and HySim_3.(See text) incorporates all the proposed methods achieved sub- stantial improvement in both performance and dy- namic memory usage.Indeed, our experimental re- suits show that HySim_3 is very efficient and outper- forms all the known and available fault simulators.
FIGUREExample of Converged Fault Descriptor.

FIGURE 2
FIGURE 2 Selective Deletion of a Fault Descriptor.

FIGURE 3 Fault
FIGURE 3 Fault Lists in a Concurrent and a Deductive Fault Simulators.

FIGURE 6
FIGURE 6 BDD-Like Evaluation of n-input gate.FIGURE 5 Delayed Fault Descriptor Construction.

TABLE tot List
Events in Event Driven Concurrent Fault Simula- Table lookup method is a popular

TABLE III Performance
Comparison for ISCAS Circuits

TABLE V Dynamic
Memory Usage and Performance of FSim for Vectors from STG-3

TABLE VII Memory
Usage of HySim for Vectors fromFASTEST Table VIII and Table

TABLE VIII
Performance of HySim's and PROOFS for Vectors from STG-3 K. KIM and K. K.SALUJA

TABLE IX
Performance of HySim_3 and PROOFS for Deterministic Test Vectors