Fault Modeling of ECL for High Fault Coverage of Physical Defects

Bipolar Emitter Coupled Logic (ECL) devices can now be fabricated at higher densities and consumes much lower power. Behaviour of simple and complex ECL gates are examined in the presence of physical faults. The effectiveness of the classical stuck-at model in representing physical failures in ECL gates is examined. It is shown that the conventional stuck-at fault model cannot represent a majority of circuit level faults. A new augmented stuck-at fault model is presented which provides a significantly higher coverage of physical failures. The model may be applicable to other logic families that use logic gates with both true and complementary outputs. A design for testability approach is suggested for on-line detection of certain error conditions occurring in gates with true and complementary outputs which is a normal implementation for ECL devices.


INTRODUCTION
Emitter Coupled Logic (ECL) using bipolar technology is a non-saturated form of digital logic which eliminates transistor storage time as a speed limiting characteristic, permitting very high speeds of operation [q ].Conventional bipolar ECL technology repre- sents the state of the art in silicon speed, providing system propagation delays of the order of 300 to 500 pico seconds but the price paid for such speeds is very high power dissipation (1.5 mW or more per gatemway too much for VLSI densities) [2].Transis- tor size and circuit density are two factors causing high power dissipation.Some recent developments in technology such as BIT1 [2] have made it possible to create smaller bipolar transistors and ECL devices are 231 being fabricated at higher densities and much lower power.A BIT1 transistor takes about 1/20th the area of conventional ECL devices and the speed is com- parable to the fastest ECL transistors which is achieved at 1/10th the power [2].
With the attainment of low power, high speed, as well as high density, ECL technology is expected to be used widely in various high performance digital circuits.Using the B5000 ECL Sparc series of com- ponents, for example, small ECL systems that perform have been designed that perform at a level equal to large mainframe computers and approach that of present day supercomputers [3].Even more highly integrated bipolar and bipolar/MOS chips are ex- pected in future, further narrowing the gap between low cost workstations and high performance servers.
Transistor level shorts and opens model a majority of the physical failures and defects in ICs [4,5].Defects and failures in present day integrated circuits can be abstracted to shorts and opens in the intercon- nects and degradation of devices [6].Therefore, fault models at the transistor level, can characterize fail- ures quite accurately [5,7-12].For MOS devices it has been shown that gate level models may not cor- rectly represent some major failure modes [13][14][15].Analysis of faults in simple logic circuits suggest that transistor level testing provides a higher coverage of faults compared to that at gate level  16].It is neces- sary to study the effects of failures at the transistor level and develop accurate fault models at this level [4].The major fault models at transistor level are stuck-at faults, stuck-shorts and opens of transistor and interconnects, and bridging faults [17].Fault models for one-level and two-level ECL gates are given in [18] and [19] respectively.Modeling and analysis of bridging faults in Emitter Coupled Logic devices were presented in [20] and [21].
In this paper, we first examine an ECL OR/NOR gate for various physical failures and their effects.SPICE simulations are used to verify analytically de- rived results.Delay faults due to various physical fail- ures are not considered in this study.Effects of dif- ferent physical faults are compared with the classical stuck-at fault model and the fault coverage is obtained.
We propose an augmented stuck-at fault model which provides a higher coverage of physical failures, and extend this philosophy to a 2-level complex ECL gate.Morandi et.al. [22] have proposed an ECL logic model obtained using the dictionary for translating each circuit element into a gate level description, which results in a complicated logic model even for a simple ECL OR/NOR circuit description.The proposed augmented stuck-at fault model is much simpler than the logic level fault model proposed in [22].Fi- nally, a design for testability approach is suggested to detect certain error conditions, termed LIKE errors or loss of complementarity [23], exhibited by gates hav- ing true and complementary outputs.
This paper is organized as follows.In section 2, a brief description of Emitter Coupled Logic and ECL OR/NOR gate operation is given.Sections 3 and 4   deal with the analysis of physical defects, application of classical stuck-at fault model and proposed aug- mented stuck-at fault model of one-level and two- level ECL gates respectively.In Section 5, we sug- gest a design for testability approach.Conclusions are given in Section 6.

EMITTER COUPLED LOGIC
Schottky TTL produces speed improvement by pre- vention of saturation, but ECL uses differential am- plifier configuration to control current levels so as to avoid saturation.Emitter Coupled refers to the manner in which the emitters of the differential amplifier are connected within the integrated circuit [24].The dif- ferential amplifier provides a high input impedance and a voltage gain within the circuit.Emitter follower outputs restore the logic levels and provide low output impedance for good line driving and high fan-out ca- pability ].OR/NOR gate is used as the basic build- ing block in most implementations of current day ECL logic designs.The operation of a basic ECL OR/NOR gate can be explained by referring to Figure 1.Transistors Q1, Q2 along with Q3 form a differential amplifier with base voltage of Q3 (VB3) derived from an internal refer- R2 R Vcc2 @ Vccl "" D2 I o2V Vee (-5.2V)

FIGURE
Circuit diagram of a 2-input ECL OR/NOR gate.
ence circuit.The transistor stage Q4 is a temperature and voltage compensation network to provide stable reference (VB) at about the center of the output volt- age swing.The functioning of the ECL OR/NOR gate can be summarized as follows: The transistor 03 will conduct only when the input transistors (Q1) and (Q2) are held OFF with low input voltages as (VIL).As soon as any one of the transistors is turned ON (i.e. an input transition to Vm), Q3 turns OFE Turning OFF of 03 causes output of Q5 (OR output) to go to Vot and that of Q6 (NOR output) to go to Voz ,.Sim- ilarly, when the input signals revert to low state, Q and Q2 are turned OFF again and 03 gets turned ON.
The collector voltages resulting from the switching action of Q, Q2 and Q3 are transferred through the emitter followers to the output terminals.Hence, the circuit provides logic OR and NOR functions in pos- itive logic, or AND and NAND in the negative logic.
No inverters are needed in ECL since every gate pro- vides a direct as well as a complemented output.
The input transistors have their bases held to the Vee line by the pull-down resistors (R and R2) which provide a leakage current path.Unused input termi- nals can be left floating without risk of noise coupling to the differential amplifier inputs.The 50 Kohm in- put resistances maintain logic '0' at inputs with inputs disconnected.The emitter follower output provides sufficient drive capability and also changes the output voltage levels so that the they are compatible with ECL levels.The output of emitter followers are left open without internal load resistances, which allows the connection of matching transmission line and matching impedance/loads at the receive end accord- ing to the user requirement which increases speed and reduces power consumption.When using the faster type ECL gate with no output pull-down resis- tance, there is a choice of a load resistance between using 50 ohm to -2 V or using 510 ohm to the Vee line.A 50 ohm resistor connected to -2 V is com- monly used when transmission lines are used for driving.In practice, Vcc and Vcc2 are connected to ground and Vee is connected to -5.2 V.
The reference voltage (emitter of transistor Q4) which tracks Vcc is approximately -1.3 V.The out- put logic levels are between -1.63V and -1.85V for Voi and -0.810V and -0.980 for Von.Transistor Q4 along with the diode and resistor network forms the temperature and voltage compensated bias network.
Transistors Q5 and Q6 constitute the emitter follower outputs.Resistors R 9 and Rio are connected exter- nally and are not provided internally by the ECL OR/ NOR gate.
Just like complex gates in nMOS and CMOS, mul- tilevel implementations are possible in ECL.One of the techniques is called series gating in which tran- sistor pairs are 'stacked' one above the other in 'tiers' so that current can be steered through different paths.
The penalty for the additional functionality is an in- crease in the propagation delay; however, this generally is less than in the case where the function is decomposed into two or more gates [3].
3. FAULT MODELING OF THE ECL OR/NOR GATE In this section, results obtained for fault modeling of ECL OR/NOR gate are summarized.The response of the basic ECL OR/NOR gate for various faults is evaluated.Possible hard failures considered here in- clude all possible opens and shorts of transistors, di- odes and resistors, transistor junction opens and shorts.ECL OR/NOR gate circuit outputs are ob- tained after performing analysis for all input vectors by simulating one fault at a time for all the possible hard faults (opens, shorts etc.) of all the devices (tran- sistors, diodes and resistors).The ECL OR/NOR gate outputs obtained analytically have been verified with the SPICE simulation outputs to ensure that there are no inconsistencies.
input patterns for which the faulty and fault-free gate produces opposite logic values at any of the outputs.
An interesting observation which needs mention- ing is that of the physical faults R1/R2 short.The purpose of the input resistances are to maintain the inputs at logic '0' with inputs disconnected.If an ECL gate with R1 or R2 short is driven by another ECL gate with output equal to logic '1', then the -5.2V appearing at the input due to the short of input resistance will dominate causing the input to appear as logic '0'.It has been verified with SPICE simula- tion that the input then effectively appears stuck-at-0.Diodes D 1/D2 serve the purpose of temperature com- pensation and shorting only causes degradation of temperature compensation performance.Some of the fault groups represent effects of several equivalent faults.

Effectiveness of Classical Stuck-at fault model
In order to model the physical failures, the classical stuck-at fault model is applied to the ECL OR/NOR gate as shown in Figure 2a.The classical stuck-at OR . . . . . .fault model is exercised with all possible input com- binations for fault-free as well as faulty conditions by introducing one stuck-fault at a time.The defective circuit behavior is then compared with the classical stuck-at fault model in representing various component failures.Correlation between OR/NOR gate classical stuck-at fault model output and physical failures is shown in columns 1-3 of Table II.In Table II, a subscript 1(0) is used to indicate a stuck-at 1(0) of a line, for example, A indicates A stuck-at 1, and A o indicates A stuck-at 0. The physical failures as modeled by fault-groups f 1, f 3, f 5, f 6, f7, f 8 and f14 are modeled accurately using the classical  Xo, Yo f ff fault-free, ** covered by one of the outputs, @ cannot be modeled at gate level, " multiple stuck-at fault, No. offaults Number of Physical failures included, too complex to be modeled at gate level.stuck-at fault model.The faults f 12, f 13 and f 17 cause one of the output to become indeterminate, which cannot be represented by a logical ,fault model.From the rest, the classical stuck-at fault model leaves 7 fault groups uncovered, corresponding to 14 physical failures.In the next section, we present an augmented stuck-at fault model that provides a higher coverage of physical failures compared to the classi- cal stuck-at fault model.

An Augmented Stuck-at fault model
As shown above, the classical input/output stuck-at fault model is not effective in modeling a large frac- tion of ECL gates.Figure 2b shows the proposed aug- mented stuck-at fault model which improves the fault coverage.Here, the device is modeled as a parallel combination of an OR gate and a NOR gate.There are thus six independent nodes to be considered.The augmented stuck-at fault model is exercised with all possible input combinations for fault-free as well as faulty conditions by introducing one stuck fault at a time.
For further classification and correlation between physical failures and stuck-at fault model, comparison is done between the circuit behavior [18] and with that of the proposed augmented stuck-at fault model output.The outcome is presented in column 4 of Table II, which also lists the faults modeled by the augmented stuck-at fault model.Here, (co,eo) indi- cates that the true output is modeled as c stuck-at-0 and complementary output is modeled as e stuck- at-0.It can be seen that fault groups f2, f4, f g, f 11, f 15, f 16, f 17 and f 18 not modeled by the classical stuck-at fault model, are modeled by the augmented stuck-at fault model [25].Fault groups f 15, f 16 and f 17 are modeled and are observable at one of the outputs only (True outputs in these cases).Fault groups f 15, f 16 and f 17 exhibit the fault as a com- plex logical fault.Again, fault groups f 12 (True out- put) and f 13 (Complementary output) are not mod- eled by the augmented stuck-at fault model.These faults cannot be modeled at the gate level, as the erroneous output always appear as an undefined value (U), however the complementary output appears as fault free.Also note that, the multiple fault (co,eo) is equivalent to A o, which may be covered by the output of the driving logic stuck-at-0.The same is true for f 3 and f 5.Only the fault groups f 9, f 11 and f 18 are always required to be represented by multiple stuck-at faults.
The multiple stuck-at fault model is an extension of the single stuck fault model, where in several lines are considered to be simultaneously stuck.If n is de- noted to be the number of possible single stuck fault sites, then there are 2 single stuck faults.Assuming that any multiple stuck fault can occur including the condition of all lines simultaneously stuck, there are 3 possible multiple stuck faults.Assuming that the multiplicity of a fault is no greater than a constant k, then the number of possible multiple stuck faults (F) is given as, F= =1 (') 2i which is usually too large a number to de.al explic- itly with all multiple faults [26].For example, the number of multiple faults (double faults, where k 2) in a circuit with n 1000 possible fault sites is about 2 million.
Applying multiple stuck-at faults to Figure 2a with a multiplicity of faults equal to 2, i.e. double faults, would need 72 multiple faults to be considered, which is obtained by substituting k 2 and n 10 in the expression for F. Considering all 72 multiple stuck faults and obtaining a table for all input vectors is too difficult a task.Referring to column 4 of Table II, we know apriori the behavior of augmented fault model to the 2-level ECL gate.For fault group f9, one possibility is to consider the multiple stuck fault of x and Yl for true and complementary outputs re- spectively.Similarly, multiple stuck faults need to be considered only for f l and f 18.Only 3 multiple stuck faults need be considered out of 72 possible double faults since the multiple faults are known apriori from the augmented fault model.Excluding f 10, f 12, f 13 and f 17, only about 73.58% of the physical failures are covered by the classical stuck-at fault model whereas 94.33% cover- age of all detectable faults is obtained using the aug- mented stuck-at fault model.Even better coverage is obtained if special handling is done for f 15, f 16 and f 17.Test generation and fault simulation would be able to function properly if the complemented output for these cases are assumed to be unknown.In that case 100% fault coverage of the deterministically testable faults would be obtained.Only 8 single and 3 double stuck-at fault groups need to be considered for modeling all the physical failures of the ECL OR/ NOR gate.The proposed augmented stuck-at fault model is also a much simpler and effective fault model compared to the complicated logic model proposed by Morandi et.al. [22], which is obtained us- ing the dictionary for translating circuit elements into a gate level description.
Another possibility is to consider the structure of the fault model shown in Figure 2a with multiple stuck-at faults which would provide 90.56% fault coverage.Fault groups f2 and f4 in this case cannot be included by multiple stuck-at faults using the structure shown in Figure 2a.The fault coverage ob- tained would still be less than the fault coverage ob- tained using the proposed augmented stuck-at fault model but the number of nodes need to be considered would be less.

TWO-LEVEL COMPLEX ECL GATE
In this section we extend the fault model to a 2-level ECL gate.The response of the 2-level ECL gate is evaluated for various faults.The 2-level ECL gate circuit realizing the true function (A + B).(C + D) and its complementary function (A + B).(C + D) is used as an example and is shown in Figure 3.
A list of possible hard failures (opens, shorts etc.) which affect the circuit functionality is given in Table III.Possible hard failures considered include all pos- sible opens and shorts of transistors, diodes and re- sistors, transistor junction opens and shorts.The 2-level ECL gate circuit outputs are obtained after performing SPICE simulations for all input vec- tors by simulating one failure at a time for all the Vee (-5.2V)FIGURE 3 Two-level implementation of (A + B)(C + D) and (A + B)(C + D).
possible hard failures (opens, shorts etc.) of all the devices (transistors, diodes and resistors).The output of the circuit behavior obtained under various defects are tabulated by combining and grouping the various faults 19].Results for a few interesting fault groups are given in Table IV.
Effectiveness of Classical Stuck-at fault model for 2-level Complex ECL Gates Several gate level implementations are possible for the logic function (A + B).(C + D) and its comple- ment (A + B).(C + D).A gate level implementation of the above functions is shown in Figure 4a.In order to model the physical failures, the classical stuck-at fault model is applied to the 2-level ECL gate as shown in Figure 4a.Results shown in Table V were obtained by exercising the model with all possible input combinations for fault-free as well as faulty conditions by introducing one stuck fault at a time.The defective circuit behavior (Table IV) now can be compared with the classical stuck-at fault model out- put (Table V) to obtain the effectiveness of the stuck at model in representing various component failures.
present an augmented stuck-at fault model that pro- vides a higher coverage of physical failures compared to the classical stuck-at fault model.
An Augmented Stuck-at fault model for 2-level ECL Gates The classical input/output stuck-at fault model is not effective for modeling ECL gates.Figure 4b shows the proposed augmented stuck-at fault model which improves the fault coverage.Here, the device is mod- eled as a parallel combination of OR-AND and OR- NAND gates realizing the true and complementary   function.Thus, there are 10 independent nodes to be considered.Table VII presents the behavior of the device under this fault model.
For further classification and correlation between physical failures and stuck-at fault model, comparison is done between the circuit behavior [19] and with that of the proposed augmented stuck-at fault model output (Table VII).The outcome is presented in column 4 of Table VI, which also lists the faults modeled by the augmented stuck-at fault model.The fault groups f2,f4,f6,f8,flO, fll,fl4,fl5,fl6, f 20, f 21, f 22, f 23, f 24, f 25 f 26 and f 30 not mod- eled by the classical stuck-at fault model, are mod- eled by the augmented stuck-at fault model [25].
Fault groups f 2, f 4, f 20, f 21, f 23 and f 24 are mod- eled and are observable at one of the outputs only.For these fault groups, the other output exhibits the fault as a complex logical fault.Fault groups f28 (True output) and f29 (Complementary output) can- not be modeled at the gate level, as the erroneous outputs always appear as undefined values (U), how- ever, the complementary outputs appear as fault free.
Fault groups 0 2, f 4, f 20, f 21, f 23 and f 24) are modeled and observable at one of the outputs only, the other output exhibits complex behavior which cannot be modeled at the gate level.Abnormal behav- ior may be observed on the other output which is not modeled properly and might lead to fault masking when the outputs reconverge on a subsequent gate.
Table VI column 4 appears to indicate that most of the fault groups in augmented fault model are mod- eled as multiple faults (double faults).However, sev- eral multiple faults can be dropped because of equiv- alence, for example, the multiple fault (bofo) mod- eled by fault group f 1 is equivalent to B o, which may be covered by the output of the driving logic stuck- at-0.Only the fault groups f 14, f 15, f 16, f 22, f 25, f26 and f 30 are always required to be represented by multiple stuck-at faults.
Applying multiple stuck-at faults to Figure 4a with a multiplicity of faults equal to 2, i.e. double faults, would need 198 multiple faults to be considered, which is obtained by substituting k 2 and n 10 in the expression for F. Considering all 198 multiple stuck faults and obtaining a table for all input vectors is too difficult a task.Referring to column 4 of Table VI, we know apriori the behavior of augmented fault model of the 2-level ECL gate.For fault group f 14,   we need to consider the multiple stuck fault of x o and Yl for true and complementary outputs.Similarly, multiple stuck faults need to be considered only for f 15, f 16, f 22, f 25, f 26 and f 30.Only 7 multiple  Xo, Yo ff fault-free, ** observable at one of the outputs, @ cannot be modeled at gate level, t multiple stuck-at fault, No. offaults Number of Physical failures included, too complex to be modeled at gate level.stuck faults need be considered out of 198 possible double faults since the multiple faults are known apriori from the augmented fault model. 90.78% coverage of all detectable faults is ob- tained by the augmented stuck-at fault model com- pared to 47.36% coverage obtained using the classi- cal stuck-at fault model.Even better coverage is ob- tained if special handling is done for f2, f4, f20, f 21, f 23 and f 24.In that case 100% fault coverage of the deterministically testable faults would be ob- tained.Only 14 single and 7 double stuck-at faults need be considered for modeling all the physical fail- ures of the 2-level ECL gate investigated.It can be seen that the augmented fault model proposed for 2-level ECL gates is much simpler and effective com- pared to the logic model proposed by Morandi et.al. [22].
Another possibility is to consider the structure of the fault model shown in Figure 4a with multiple stuck-at faults which would provide 68.42% fault coverage.Fault groups f 8, f 10, f 11, f 12, f 13, f 17 and f27 in this case cannot be included by multiple stuck-at faults using the structure shown in Figure 4a.The fault coverage obtained would still be less than the fault coverage obtained using the proposed aug- mented stuck-at fault model but the number of nodes to be considered would be less.

DESIGN FOR TESTABILITY
Careful study of Table IV and corresponding results for ECL OR/NOR gates [18,19] indicate that for some of the physical failures, the input test vectors cause both the true and complementary outputs to exhibit erroneous LIKE outputs (i.e.similar outputs, 00 or 11) or loss of complementarity, instead of the true and complementary outputs exhibiting fault-free UNLIKE outputs (i.e. 01or 10).Out of the 18 classi- fied faults for various physical failures of devices for the ECL OR/NOR gate, 7 of the fault groups exhibit erroneous LIKE outputs with at least one or more input vectors, which is approximately 39% and out of the 30 classified fault groups for the 2-level ECL gate, 20 of them exhibit erroneous LIKE outputs which is approximately 66.66%.By using the follow- ing simple design for testability approach, it is possi- ble to ON-LINE detect such faults.This maybe use- ful in fault-tolerant systems.
A design for testability approach may be based on the use of an exclusive-OR gate connected at the out- put of certain ECL gates, with the output of the exclusive-OR gate termed as the ERROR signal.When the true and complementary outputs of the ECL gate is fault-free UNLIKE output (i.e. 01or 10), then the ERROR signal would be a indicating that ERROR and ERROR 0 (i.e.NO ERROR).
Whenever any of the faults cause the outputs of the gate to exhibit erroneous LIKE outputs (i.e. 00or 11), then the ERROR signal would become a 0 indicating that ERROR 0 and ERROR l(i.e, an ERROR has occurred).Use of an Exclusive-OR or NOR to detect LIKE errors in single level ECL gates would be an increase in area overhead and might be prohibitive.
However, if the gate is multiple level and sufficiently complex, then the overhead may be justifiable in some situations.This approach may be effective at module level, at the end of high speed data bus, in clock chains etc. and in other applications where there is probability of LIKE errors to occur.

CONCLUSIONS
The effectiveness of the classical stuck-at fault model in modeling physical failures that are possible in one and two-level ECL gates have been examined.An augmented stuck-at fault model has been proposed as the classical stuck-at fault model did not model a major fraction of the physical failures.High fault coverage can be obtained using the augmented stuck-at fault model for ECL gates compared to the classical stuck-at fault model.The augmented stuck-at fault model can easily be extended to multi- level complex ECL gates.A design for testability ap- proach was presented for detecting LIKE error condi- tions or loss of complementarity occurring in gates with true and complementary outputs which is a nor- mal implementation for ECL logic devices.
The proposed fault model is also applicable to other logic families such as CVSL (Cascode Voltage Switch Logic), where a logic gate produces a true and a complementary output.It is often noted that test sets based on classical stuck-at model provide a high fault coverage even when a fault is not directly mod- eled as a stuck-at fault.However, in cases where a fault is not covered explicitly by the model, the test set can only be as effective as a random test set in detecting such a fault.The model proposed here can be used with gate level test generation tools to in- crease the explicit fault coverage.Fault simulation is used to evaluate the effectiveness of a test set, generated at functional level or based on a fault model.Incorrect modeling of faulty behavior in either one of the outputs could cause the fault simulator to predict incorrect logic output values.With the augmented model, it is possible to predict the values of both the outputs for a given fault.Consequently, the accuracy of fault coverage estimated using fault simulation can significantly be enhanced by using the augmented model.
Figure shows the implementation used in the Motorola MECL logic family 1 ].
Fault groupsPhysical failures vs Stuck-at faults No. of Classical Stuck-at AugmentedStuck-

FIGURE 4
FIGURE 4 (a) Classical stuck-at fault model.(b) Proposed aug- mented stuck-at fault model.

10 X
ff A o A B o B C C D D Xo X Yo ABCD XY XY XY XY XY XY XY XY XY XY XY XY OR Output, Y NOR Output.

TABLE List of
Fault groups vs Physical failures

TABLE II Correlation
between Physical failures vs Stuck-at fault models.

TABLE III List
of Fault groups vs Physical failures

TABLE IV Circuit
behavior under physical failures of 2-level Complex ECL gate (ff Fault-free, f 1-f 17 Defective).

TABLE V
ECL 2-level ComplexGate outputs for Classical Stuck-at fault model.2-level ECL Gate Classical Stuck-at fault model Input

TABLE VI Correlation
between Physical failures vs Stuck-at fault models for 2-level Complex ECL Gate.

TABLE VII ECL
2-levelComplex Gate outputs for Proposed Augmented Stuck-at fault model.2-levelECLGate Augmented Stuck-at fault modelInput ff ff a a b o b c O c do dl eo el fo f go g h