Application of Dynamic Supply Current Monitoring to Testing Mixed-Signal Circuits

This paper applies the time-domain testing technique and compares the effectiveness of transient voltage and dynamic power supply current measurements in detecting faults in CMOS mixed-signal circuits. The voltage and supply current (iDDT) measurements are analyzed by three methods to detect the presence of a fault, and to establish which measurement achieves higher confidence in the detection. Catastrophic, soft and stuck-at single fault conditions were introduced to the circuit-under-test (CUT). The time-domain technique tests a mixed-signal CUT in a unified fashion, thereby eliminating the need to partition the CUT into separate analogue and digital modules.


INTRODUCTION
Testing is one of the major bottle-necks in the production of integrated circuits (ICs).As the electronic circuits and systems realised on ICs grow in com- plexity and density due to improved VLSI (Very Large Scale Integration) fabrication processes, the task of testing also becomes more complex leading to an increase in the time, and hence cost of production.
For digital ICs, including complex VLSI ones, the task of testing is now manageable.This has been achieved by the use of simple fault-models, devising efficient test pattern generation algorithms to detect the faults synthesized by the fault-models [1-3], and the introduction of design-for-testability (DFT) tech- niques during the early stages of an IC design to en- hance its testability [4,5].Software test tools and au- tomatic test equipment (ATE), that implement most of the testing algorithms and testability enhancement techniques for digital ICs, are now widely available.
The testing algorithms and DFT techniques for digital ICs, and the test tools that implement them, unfortunately, have no counterparts for analogue in- tegrated circuits.This is due to the complex charac- teristics of analogue circuits.The characterisation of analogue circuits depends on continuous descriptive variables, such as magnitude and frequency for am- plifier gain, rather than the discrete variables of logic *Corresponding author.Tel.: +971 (6)355355.Fax.+971 (6)378987.E-mail: maq@ece.ac.ae.*Tel.: +44 (225) 826826.Fax.+44 (225) 826503.E-mail: p.r.shepherd@ssl.bath.ac.uk.224 M.A. AL-QUTAYRI and P. R. SHEPHERD levels in a digital circuits.This makes the design and test of an analogue circuit more knowledge intensive than its digital counterpart.Furthermore, the requirement to handle the complex, and many times conflict- ing, parameters of an analogue circuit results in the lack of efficient simulation and test tools similar to those for digital circuits.A concerted effort has been put, especially during the past two decades, to devise testing algorithms for discrete analogue circuits and systems [6].The algorithms, however, cannot be readily extended to testing analogue ICs due to the need for access to a high number of nodes, and the limitation on the number of components they can deal with [7].At present, testing an analogue IC in- volves verifying that the manufactured IC meets the design specifications, such as gain, bandwidth and noise margin.This process is time consuming and costly.
Mixed-signal integrated circuits are ICs that have both analogue and digital circuitries on a single chip.It is common for a single mixed-signal IC to support analogue voltage references, amplifiers, comparators, analogue-to-digital (A/D) and digital-to-analogue (D/A) converters, and a wide range of digital components including microprocessors for data processing.Such ICs result in an improvement in system performance and reduction in cost.However, the incorpo- ration of analogue and digital circuits on a single de- vice present a formidable problem for testing com- pared to pure analogue or digital ICs.This is due to the difficulties associated with testing analogue cir- cuits, which were outlined above, and the lack of controllability and observability of embedded circuit modules.The testing task is exacerbated further by the presence of interface circuit blocks, such as A/D and D/A converters, and other circuit modules (e.g switched capacitor circuits) that exhibit both ana- logue and digital characteristics.
In practice, mixed-signal ICs are tested by parti- tioning the device into separate analogue and digital modules, by including extra probe pads to provide access to internal signals, and applying mode-specific tests to each module using separate analogue and dig- ital test setups.The inclusion of probe pads results in an increase in the wafer area required, reduces IC reliability and performance, and increases its overall cost.The use of powerful digital signal processing (DSP) techniques to emulate the analogue test instru- ments has enabled the digital and analogue tests to be performed by a single measurement system, thus en- abling control of signal timing to be maintained [8].However, the use of this approach does not eliminate the partitioning requirement due to the need to inject and monitor the response to different types of test vectors.
A testing strategy for mixed-signal circuits called "time-domain testing" was proposed [7,9].The tech- nique eliminates the requirement to partition a mixed- signal circuit-under-test (CUT) by testing the CUT in a unified fashion.An overview of the technique is presented in a later section of this paper.A prototype system that implements the time-domain technique and some practical results were presented in [10].
In this paper we present the results of applying the time-domain technique to testing a CMOS mixed-sig- nal circuit.Both the voltage at the output nodes of the circuit and variation in the dynamic power supply current (iDDT) are measured and processed to evalu- ate their effect on fault-coverage.

OVERVIEW OF TIME-DOMAIN TECHNIQUE
The time-domain testing technique is based on the excitation of the CUT with a sequence of pulses, and subsequent measurement of the transient response at the output node/s [7,9-10].Both the transient voltage at the output node/s and the transient current iDDT of the supply current are measured.The transient current (iDDr) testing technique is similar to the IDDQ testing technique [11][12], except that IDDQ testing is per- formed under static conditions while iiD: testing is performed under dynamic conditions.
A major advantage of the time-domain approach is that the transient response contains a wealth of infor- mation about the CUT.This information can then be processed by applying digital signal processing (DSP) and other techniques to extract measures of the various CUT parameters.In this paper, the primary objective when processing the transient response data is to establish whether the CUT is faulty or not (i.e.go/no[00ff]2Dgo), and not to locate and identify the type of fault present if any.
The type of test sequence to be applied to a CUT is a pseudo random binary sequence (PRBS).The PRBS is chosen because it can be readily generated by a digital tester, such sequences have well defined properties [13], can be used to extract the impulse response of linear analogue CUT and the pulse width can be tailored to force large Fourier components to fall within the sensitive region of the circuit response [7,14].If the CUT is a mixed-signal network, the response generated by applying a PRBS test signal can be used as a signature to characterize the network under-test.

ANALYSIS METHODS
Three methods are proposed to analyze the transient response data extracted at the external nodes of a CUT as a result of exciting it with a PRBS signal.
The objectives are to establish which type of mea- surement (i.e.voltage or current) is best at detecting a particular fault, which method of analysis achieves the highest fault-coverage and which one is most ef- ficient in terms of computation.The methods of anal- ysis are: In this method a fault is detected by comparing the values of the samples of the response of the CUT with those of the fault-free toleranced response, The number of instances (i.e samples) at which the CUT response falls outside the tolerance envelope are counted, and the percentage of deviation from the ideal response is accumulated.A new parameter called the Coefficient of Variation (CV) is calculated for each fault that was detected at least at one instant.
The CV defined in this paper is different from the standard definition of the statistical coefficient of variation.The objective of calculating CV is to deter- mine which type of measurement, voltage or current, detects a particular fault with higher degree of confi- dence.CV is defined by Equations 1 and 2. D I(Yf Yni)/Yn]* 100% CV is then normalised to make it easier to compare the results of processing the transient responses of the voltage and current measured.The example below demonstrates the samples values method.
Example: For a particular circuit assume that the tolerance is _ 10% and the number of samples col- lected for the analysis of its voltage response is M 10.If under fault-free (Yni) and a faulty condition (Yfi) the responses are Yn [0, 0.85, 1.5, 2.3, 3.45, 4.8, 3.2, 2.95, 2.0, 1.25] Yfi [0, 1.05, 1.58, 2.1, 2.85, 3.67, 3.4, 3.58, The number of detection instances dn 6, because samples 1, 3, 4 and 7 fall within the bounds of the nominal toleranced response.Applying Equ.2 gives CV 139.64.When the CVs for all the faults are calculated the results are normalised and compared with those for the current response.If for a particular fault condition the normalised voltage CV is higher than the normalised current CV, it would then be con- cluded that the fault is best detected by voltage mea- surement.

Rate of Change
In this method, the rate of change (Rt) of the response of a CUT between the sampling intervals (At) is cal- culated according to Equation 3. R (mi+ mi)/At (3) where m and mi+ are the values of the response at samples (i) and (i + 1) respectively.
The rates of change ,for the CUT is then compared with that of the fault-free response.This method of analysis is capable of detecting faults which produce responses similar to that of the fault-free one but are shifted in time.
tized fault-free and CUT responses are then com- pared to determine the number of instances at which a fault is detected.
Having tight bounds round a response increases the sensitivity of the measurement to faults and may lead to higher detection rates.However, the bounds should reflect the actual tolerance of the circuit.Otherwise, misleading high detection rate may be achieved by, for example, the imposition of artificially tight bounds.
Varying the threshold value may lead to the detec- tion of faults that otherwise will not be detected, and an increase in the number of detection instances for some faults.Therefore, the program that implements the digitization method varies the threshold value by requesting the number of times the analysis is to be repeated.It uses this to divide the space between the maximum and the minimum values of the fault-free response to a uniform set of threshold values, each one of these values is considered a test.The program keeps track of all these tests, then compares them to determine the overall fault-coverage and which test is best at detecting a particular fault and the highest number of detection instances achieved.

Response Digitization
In the digitization method of analysis the transient response waveforms of both output voltage and sup- ply current are digitized into 3-levels" 1, -1 and 0. This is achieved by assuming a threshold value, Vth and Ith for voltage and current respectively, with a small bound round it.The upper and lower bounds for the voltage response are VthH and VthL respec- tively.Similarly, the bounds for the current response are Ithi_ and IthL.These bounds are the worst case tolerance values for each response.If a sample data value falls above the upper-bound (Vthr or IthH) of the threshold value it is considered a logic high (1), if it falls below the lower-bound (VthL or IthL) it is con- sidered a logic low (-1), and otherwise the logic is considered unresolved and denoted by 0. The digi-

CMOS MIXED-SIGNAL CIRCUIT EXAMPLE
To demonstrate the effectiveness of the time-domain approach and the analysis methods in testing mixed- signal ICs the simple circuit shown in Figure 1 was simulated and tested.The circuit consists of four modules: a low-pass filter (LPF) with a 3-dB band- width of 2-KHz, a sample and hold (SH) circuit, a 2-bits analogue-to-digital converter (ADC), and a full-adder digital logic network.The schematics of the operational amplifier, comparator and analogue switch are illustrated in Figure 2 [15], Figure 3 [16] and Figure 4 respectively.The logic gates are all stan- dard cells.
The CMOS mixed-signal circuit in Figure 1 was tested by injecting a 15-bits PRBS test sequence at the LPF input (Vin), with a 250 lasec bit interval.The transient voltage responses at Vs and Vc, and the sup- ply transient current iDD: were sampled every 10 lasec, resulting in 375 samples for each waveform.
The PRBS input signal and the fault-free transient responses at Vs, Vc and iDDT are illustrated in Figure 5.
A total of 140 single fault conditions were simu- lated.Of these faults 115 were catastrophic faults in the MOS transistors of the various modules, 5 soft faults in the resistive and capacitive components of the LPF, SH and ADC, and 20 stuck-at (s-a-1 and s-a-0) faults at the terminals of the digital logic gates.
The fault model adopted for catastrophic faults in MOS transistors is depicted in Figure 6.The model is based on the studies of integrated circuits yield [17][18], and the work on the likely catastrophic faults in MOS transistors reported in [19-20].The faults syn- thesized by the model in Figure 6 and the status of the associated switches are summarized in Table I.
All the results obtained are based on simulating the mixed-signal circuit under fault-free and faulty con- ditions using HSPICE [21], the analogue circuit sim- ulator.The methods of data analysis, described in the previous sections, were all implemented using the mathematical software package MATLAB [22].In all cases, if the response of the CUT falls outside the bounds of the toleranced response the circuit is con- sidered faulty, hence a fault is detectable.
Analysis of Vs, Vc and iDDT transient response data based on samples values, depicted in Figure 7, shows that the three measurements achieve 100% fault-coverage each.To determine which one of the measurements is best at detecting a particular fault the normalised CVs of Vs, Vc and iDD: were calcu- lated and plotted in Figure 8.The normalised CVs indicate that Vs, Vc and iDD: are best at detecting 72, 32 and 36 faults respectively.
Figure 9 illustrates the results of applying the rate of change analysis method to Vs, Vc and iDDW.It shows that the fault-coverage achieved by each one of the three measurements is 100%.The application of the digitization method of anal- ysis to Vs, Vc and iDD:, with 10 tests specified, re- suited in a fault-coverage of 74.29%, 72.86% and 100% respectively.The plots of the test best suited to detect particular faults and the corresponding highest number of detection instances for Vs, Vc and iDDT are illustrated in Figure 10, Figure 11 and Figure 12 respectively.

CONCLUSIONS
The simulation results of the mixed-signal circuit ex- ample above demonstrate that the time-domain testing is capable of testing such circuits in a unified fashion, and hence eliminating the need for partitioning.Analysis of the transient voltage and power supply current (iDDr) data indicate that both measurements are complementary in terms of achieving a high per- centage of fault-coverage with a high degree of con- fidence.Of the three methods of data analysis, the re- sponse digitization method is the most efficient in terms of computation, because it eliminates the need for floating point computation.

S5
R s = 1.0 Ro = 10 M D method can also be implemented on a digital tester, hence resulting in saving in both testing time and cost.The results presented above are all from the anal- ysis of the extracted simulation data.Implementing the testing technique and methods of analysis in a practical system may lead to a reduction in the detec- tion rates due to the resolution of the measurement system.The resolution of such a system would be particularly important for the data rate method of analysis due to its high sensitivity compared with the other methods.Implementation on a practical system, however, is not expected to result in a substantial reduction in the detection rates discussed above.
The effect of the PRBS length and bit rate on the detection rate was investigated in [7].It was con- cluded that in general a longer PRBS would result in a higher rate of detection because the sequence will be closer to white noise and hence exercise the CUT in more states.However, the methods of analysis still lead to the same conclusions presented above.In its present form, the time-domain testing ap- proach is unlikely to lead to a complete unified test solution for complex mixed-signal circuits due, for ex- ample, to a reduction in the PRBS signal resolution and change in its characteristics.However, the tech- nique is expected to be of substantial benefit when used in conjunction with the mixed-signal test bus [23] or other analogue built-in self test techniques [24].

FIGURE 2 FIGURE 4
FIGURE 2 Schematic of the operational amplifier.

FIGURE 7 FIGURE 8
FIGURE 7 Detection instances by Vs, Vc & iDDT Of mixed-signal circuit.

FIGURE 9
FIGURE 9 Det.intervals by Vs, Vc & iDDT rate of change of mixed-signal circuit.

FIGURE 12
FIGURE 12 Best test & highest detection by digitized iDvr of mixed-signal circuit.