Operational and Test Performance in the Presence of Built-in Current Sensors

The effects of Built-In Current Sensors (BICS) on loon measurements as well as on the performance of the circuit under test are considered. Most of the Built-In Current Sensor designs transform the ground terminal of the circuit under test into a virtual ground. This causes increases in both propagation delay and Io,Q sampling time with the increase in the number of gates, affecting both test as well as operational performance. The effects that current sensors have on the operational and test performance of a circuit are considered. Circuit partitioning may be used for overcoming the effects of BICS on Ioo measurements as well as on the performance of the circuit under test.


INTRODUCTION
The use of leakage current measurement to detect faults in CMOS ICs has been under consideration for a number of years [1 ].Recent studies on leakage cur- rent based testing techniques [2,3], have concluded that it is necessary to include IDDa monitoring to ob- tain highly reliable CMOS ICs.The data presented for four sample CMOS ICs showed that the defect detection increased between 60% to 180% when looQ monitoring is added to a functional test set [2].Izoa testing was demonstrated to reduce line fallout after 99.6% stuck-at fault testing failed to achieve desired quality goals [4].
IDOQ testing is performed using either an external or a Built-In Current Sensor(BICS).The implementa- tion of built-in current sensors has received a lot of interest in recent years.Built-in current sensors have an advantage over external sensors in terms of test speed.They also exhibit some drawbacks in terms of increases in propagation time (tpa) as well as settling time (ts) affecting both operational and test perfor- mances.Built-in current sensors are normally con- nected in series with the circuit under test and the power supply.This results in the ground terminal of the CUT becoming a virtual ground rather than a physical ground.As the virtual ground may not be at the same potential as the physical ground, the capacitance of the ground rail of the CUT assumes an im- portant role.This capacitance consists of the lumped capacitance of the source terminals of all transistors *Corresponding author.
as well as the capacitance associated with the wiring.This phenomenon causes an increase in settling time (ts), thus slowing the IDDQ testing process.The volt- age difference between the virtual and physical grounds may also cause an increase of the propagation delay, thus affecting the normal operational performance of the circuit.In this paper, we present the limitations of BICS which rely on a virtual ground, which in turn affects the operational and test performance of the circuit under test (CUT).
In Section 2, we review the research on current testing.In Section 3, we discuss some of the existing built-in current sensor designs.Section 4 covers the dependence of IDDQ testing on circuit size, where an upper bound on the number of gates in a partition for distinguishing faulty and normal IzDQ values is given.Subsections 4.2 and 4.3 deal with effects of BICS on test speed and operational performances re- spectively.The importance of partitioning large cir- cuits for IzzQ testing is discussed in Section 5. Fi- nally, conclusions are given in Section 6.

BACKGROUND
There are several reasons for using IooQ monitoring for testing ICs [5], [6].Traditional IC testing tech- niques are not effective in detecting a number of fail- ure modes in CMOS ICs.In general, faults such as gate oxide shorts [5], [7]-[ 11 ], certain bridging faults [12]- [15], certain open faults, stuck-on faults [8], punch-through faults, operation induced faults [16], parasitic devices, pn junction leakage, and abnor- mally high contact resistance may not manifest them- selves as logic faults and therefore may not be de- tected by traditional tests which monitor the output logic levels.These localized defects degrade the elec- trical performance of the circuit without affecting its logical operation.Parametric faults such as incorrect threshold voltage, excessive parasitics, etc., are also difficult to detect by traditional test techniques, and often affect circuit signal delays as well as the power consumption.Implementing IDDQ testing prior to burn-in has resulted in a significant decrease in the fall-out [6].
A major fraction of failures caused by circuit fa- tigue will first appear as parametric drifts.Progressive gate oxide leaks, for example, may not initially affect the functionality of a device, but could become shorts within a short time, leading to the failure of a device [8].Eventually, some of them will advance enough to alter the logical behavior or become circuit failure.Leakage current based testing will detect these parametric drifts before they actually change the circuit behavior.Data exists that shows that de- vices that fully pass the logic functional tests but fail the IDDQ tests, fall into a significant category of de- vices that functionally fail more frequently in early life than normal [5].
Current testing also is an invaluable tool for detect- ing faults in devices that contain both analog and digital functions on a single substrate [17].In the near future, a large fraction of devices are expected to combine both digital and analog functions on a single substrate 18].
Off-chip current testing has several other advan- tages over traditional functional testing techniques 1 ].In functional testing, the site of a fault has to be excited and the effect of the fault has to be propagated to an output.In IDDQ testing, the propagation of the effect is automatic.Further, it can provide transis- tor level resolution as opposed to gate level resolu- tion.Off-chip current testing has proved to be very efficient for circuits like static RAMs [19].
Most of the gate oxide shorts cannot be modeled as stuck-at faults, especially for transistors with W/L 1 [20], where W and L are Width and Length respec- tively, of the transistors.The use of current measure- ment techniques to find gate oxide leaks is investi- gated in [21], and techniques are presented to test quiescent IDD to a 1 laa limit on every clock phase of a functional test.It also identifies several problems associated with the measurement of IDDQ.The current drawn by I/O circuits for example, can mask the cur- rent drawn by a fault.Other problems identified in- clude wideband noise across the load capacitance, di- electric absorption in output pads, input capacitance offered by the VDD pin, and the presence of mixed logic and redundant cells.To overcome these prob- lems, the use of several techniques during the design of ICs have been proposed, including the use of sep- arate VDD pins for output buffers and internal logic.
Stuck-on faults in CMOS circuits cannot be de- tected using traditional functional fault testing tech- niques.Test generation for the detection of such faults, when Ioo. testing is used, is considered in [22].Different decision processes involved in detect- ing such faults have been examined.The voltage level in the presence of stuck-on or bridging faults in CMOS circuits depends on the relative impedances of the transistors involved and the bridge [23].This makes detection of such faults difficult using voltage measurement techniques.However, IDDa testing de- tects such faults.It has been shown that IDD a testing also detects multiple stuck-at faults as well as logi- cally redundant faults [23], [24].
Most of the research in this area considers the use of [-----'DDQ measurement techniques for detection of faults in CMOS circuits.This can be attributed to the fact that the static quiescent current drawn by a CMOS circuit is very small and therefore the detec- tion of a fault which increases the Izo2 is relatively easy to detect.With technologies such as nMOS and TTL, the quiescent current can be fairly large, and the increase in current drawn due to a fault may not be significant enough to be detected by measuring equipment.Even so, current testing techniques have been successfully used to detect faults in TTL circuits [25].The faults that have been detected include open circuits, stuck-at faults and multiple faults.The supply current measurement has been supplemented in [26] with the measurement of the low frequency noise in the supply current, the circuit delay as a function of the supply voltage, the transient current as the circuit switches between states, and the noise in the transient current to provide an indication of an incipient failure in CMOS integrated circuits.
One obstacle for commercial acceptance of current testing of ICs has been the relatively slow measure- ment rate compared to normal logic testing.Typi- cally, current testing is done at a rate less than 100K test patterns per second [21], whereas functional test- ing can be carried out at the normal operating fre- quency of the device under test.The speed of IDDQ testing is limited by several factors.The width of the transient current pulse, the loading of the VDD pin due to output buffers and the impedance of the probing circuitry are some of them.It has been demon- strated that the rate of testing can be increased by several orders of magnitude by isolating the output buffers of an IC from the VDD pin [2].
The high resolution required for current testing has been cited as a problem that makes acceptance of current testing difficult at present [3].The key to per- forming an effective Ioo test is the probe circuit used to measure the current.Such a circuit should be capable of measuring small currents, without affect- ing the supply voltage, especially during transients, and must be capable of fast measurements [27].The different types of current probes in use are examined in [27], and a probe circuit has been proposed which allows a system to perform dynamic Ioz tests as an integral part of the functional testing of a CMOS de- vice.
Built-in current sensing techniques have been proposed to overcome the disadvantages of existing off- chip current testin techniques.Current sensors have been proposed and implemented using CMOS tech- nology, some capable of detecting currents as small as 2laa at 1MHz clock frequency [5].In BIC testing, an IC is implemented using a number of modules and each module is connected to the power supply through a current sensor.Another circuit design for built-in current testing has recently been proposed [28].The output of the current sensor of a module is observed with the proper input vectors to detect faults in that particular module.

BUILT-IN CURRENT SENSORS
The simplest current sensor can be built with either a resistive [3] or a capacitive [29] element (labeled by 'X' in Figure 1) along with a voltage comparator, as shown in Figure 1.The current flow L will cause a voltage drop across the element X and the voltage on X is fed to the comparator [27], [29].The other input of the comparator is the standard voltage (Vref) which is the reference voltage.Therefore, if the mea- sured current Iooa is greater than IDoath (IDDQ threshold, which is set by the Vref) the output of the current sensor is 1.If IDDQ is smaller than IDDQth, the output of the current sensor is 0. Various current sensors have been proposed [3, 27,  28, 29].The BICS proposed by Maly, et.al. [3], is based on a non-linear resistance placed in the power supply current path.The exponential I-V characteris- tics exhibited by the non-linear resistance causes dis- tinguishable voltage drop for a wide range of cur- rents.The output of the current sensor distinguishes between the normal and abnormal quiescent currents by comparing the voltage drops with a reference volt- age.
One of the current sensor circuits proposed by Rubio, et.al. [29], uses a capacitor instead of the non- linear resistance.Several schemes for current mea- surement are given in [27].A circuit for built-in cur- rent testing presented in [28] measures the integral of the current during a certain time interval.The mea- sured value of the current is used to decide if the circuit under test is fault-free or not.
In almost all of the BICS designs, the circuit under test is connected in series with the built-in current sensors in a manner such that the power supply ground terminal is connected to the BICS input.The bypass circuit generally is made up of an nMOS tran- sistor which provides a path for the ground terminal of the circuit under test to the physical ground, under normal operation.In the BICS proposed by [3], the bypass circuit is formed by an nMOS transistor and the base to emitter junction of a bipolar transistor.This results in the ground terminal of the CUT being a virtual ground.Limitations on the IDD a measure- ments due to virtual grounds are given in the next section.

DEPENDENCE OF IDDQ TESTING ON CIRCUIT SIZE
When the circuit size is small, distinguishing the dif- ference between normal and faulty IDDQ values is not difficult.When the circuit size becomes large, it be- comes hard to detect a fault using IDOQ monitoring as the distinction between normal and faulty current be- comes difficult to differentiate.Furthermore, the larger the circuit size, the more significant the effect of BICS on the operation speed and the test speed of the circuit will be.Below, we describe several factors regarding the effect of BICS on circuit operation and testing.The solution to this problem will be to parti- tion the device under test into smaller modules.Each of the partitions will have its own current sensor.Partitioning to distinguish the difference between normal and faulty IDD a values is discussed in this section.
The effects of BICS on test speed and on operational performance with increasing circuit size is covered in this section.

Difference between Normal & Faulty IDDQ
Values A statistical characterization of faulty and fault-free IDD a distributions is presented in [30, 31].The dis- tinction between the distributions of normal and faulty IDDQ is easy if the distributions are well sepa- rated.If the number of gates in a circuit is small, then Density function Fault-free Faulty hDDQ "IDDQ Gurrnt FIGURE 2 The 'gap' between fault-free and faulty value of Iz)c,a.the distributions between normal and faulty IDDQ are well separated and thus the fault is detectable.The separation or gap between the distributions for nor- mal and faulty Iz)z) a is given below [30, 31].The same equation for the gap applies for each module: gap Pif-3(/ncr2iAOZQ + o'f + GCriAgZQ) (1) where n is the number of cells in one module, laif and criy are the mean and standard deviation of the addi- tional quiescent supply current (if), and CriAZDQ is the standard deviation of the current through an average cell.Figure 2 shows the gap or the separation be- tween the two distributions.
As the number of gates in a circuit increases, the spread of the current distributions, both faulty and fault-free, increase making the distributions overlap.The spreading of the distributions occurs due to the variations in circuit parameters over different gates in an IC [30].The above expression illustrates the basic problem in testing large devices.To use IDOQ testing in the presence of this phenomenon, the size of each module connected to a BICS has to be such that the faulty and fault-free distributions within each module can be distinguished.
Monte Carlo simulations of CMOS circuits with 10, 50, 100 and 1000 gates were obtained.Tox (oxide thickness) and NSUB (substrate doping) were used as the random variables for the Monte Carlo simulations with a variation of _+ 10% and a normal distribution.
Monte Carlo simulations for a circuit of 1000 invert- ers with 100 runs is shown in Figure 3.In the follow- ':i:i:i:i:i:!:i:!:i: i:i:i:i:i:i:!:i:i:i::i:i:i:i:i:i:i:i:i:.Current drawn (in mA) FIGURE 3 Histogram of faulty current with 1000 gates.
ing analysis, we approximate the distribution using a gaussian distribution.
Let us assume that the maximum size of each mod- ule is determined by letting gap be 0.Although we have to use numerical methods to obtain the exact value of n, we can derive the upper bound of n as follows: Ply 3(/n'aooa + cr + Vn(riaoQ)>--6 iADDa (2) From the above equation, the upper bound of the maximum n, denoted by n b is given as: rib=( luif ]2, (3) where n b is the number of cells covered by a current sensor.Hence, the device can be partitioned into modules whose sizes will not exceed rib, and all the modules will have approximately the same number of cells.The above criterion ensures that the distribu- tions of the normal and faulty IDOQ are separated and distinguishable.
Here, we are not considering the sensitivity of Built-in Current Sensors, which depends on the test frequency being used [32].A higher test frequency will result in lower available resolution of the current sensor which will affect the partitioning size [33].

Effects of BICS on Test Speed
Another reason for partitioning the device into sev- eral modules is that the larger the device or circuit becomes, the larger the capacitance seen at the cur- rent sensor input (node VG in Figure 1).So, it will take a longer period for the current sensor to respond to the value of the current flow in the circuit.The speed is limited due to the fact that the current mon- itoring has to be done after the transients have settled.The duration of the transients will depend, among other things, on the capacitance associated with mea- DDQ Current tail pdmax t c settl e t measur e FIGURE 4 Plot illustrating Power Suppy Current vs.Time for a CMOS circuit.
Inv Inv, Inv-, Inv, Inv= FIGURE 5 An inverter chain with 5 inverters.surement points.Thus, the larger the circuit that is covered by a current monitor, the longer the settling time of the transient.
For Ioo a monitoring, the measurement of the sup- ply current has to be performed by the current sensor after the initial transients have settled.Figure 4 shows a plot of IDO VS.Time for a typical CMOS circuit.tpdma is the maximum propagation delay of the cir- cuit under test.tpdma is caused due to the initial tran- sients in the supply current due to switching in the various gates of the CMOS circuit.It takes a certain amount of time (tc) for the current tail to end, i.e., the current to settle to an almost constant value of the order of pico or nano Amps in a fault-free CMOS circuit.In a faulty CMOS circuit, the value of can be a few orders of magnitude greater than the fault-free Ioo value.The total time taken for the current to settle, tsettle is the sum of tpdma and tc.
Consider the inverter chain consisting of five in- verters shown in Figure 5. Input/Output waveforms along with the current waveform, Ioo, obtained using SPICE simulations are shown in Figure 6.The input pulse applied to the inverter chain is marked on the plot.Output signals O1, 02 05 are the respective output signals of inverters inv 1, inv 2 inv 5.The cur- rent drawn by the circuit is shown by dark line with the axis on the right side of the plot.The current waveform shows almost 0.4mA current drawn by the 5 inverter chains when the gates are switching.The last gate, Inv 5, switches around 9.2ns, shown as tpd in the plot.After the last gate switches, the current goes to a steady, low current in a fault-free CMOS circuit.The time from when the last gate switches, tpdmax, until the current reaches the steady low current value is termed as t.The sampling of the supply current can be done any time after the current tail has reached the almost fixed, very low value of current in the fault-free CMOS circuit.If the CMOS circuit is faulty, then the current at this time would be elevated and hence the BICS would be able to detect the fault.This results in a settling time of tsettle tpdmax c.
One of the important parameters to be obtained is the sampling time for a given circuit partition for Iooo.pling is done well after the current has settled to a steady-state value, then the measurement becomes slow.An ideal sampling time for IDD2 would be when the current is within about 5% of the steady-state value.Here, we consider the parameters that govem the settling time of IDD.
One of the components of the settling time, tsettle is tpdma and the other component is C, caused by the current tail.tpdm can be obtained directly from the maximum propagation delay of the complete chain of gates in a given circuit.The second component, to, of the settling time, caused by the current tail, depends on the rise-time (tr) and fall-time (tf) of the last few gates of the circuit.
CMOS circuits with varying numbers of gates and levels were simulated using a built-in current sensor (BICS) [3], as shown in Figure 7, to study the settling time of the power supply current.It may be noted that when BICS are implemented, the transistor terminals (source or drain) in a CMOS circuit, which otherwise would have been connected to ground is connected to the BICS.The transistor terminal (source or drain) capacitance of all the transistors appears as one lumped capacitance (C) at the input of the BICS.The larger the circuit under test (CUT), the larger the ca- pacitance seen by the BICS.In the absence of BICS, C is always grounded and therefore has no effect on the performance.
In order to study the effects of varying circuit size on iDD settling time and propagation delay, CMOS circuits having different number of levels of gates (1,3, 5 and 10) were chosen for simulation with BICS (Built-in Current Sensor).The maximum number of gates cascaded in series between a network input and output is referred to as the number of levels of gates [34], hereafter referred to as the number of levels of the circuit.For example, simulation for 5 levels total- ing 1000 gates has 5 gates connected in series with 200 such series of gates in parallel.
Figure 8 shows plots for ioo settling time vs. total number of gates for CMOS circuits having different number of gate levels.In Figure 8, the ioo settling time shown also includes the propagation delay (tpa) for circuits with different number of levels and the time for the current tail (tc) to settle.It may be noted that ioD settling time for a circuit with 10-levels is greater than that of a circuit with 5-levels, both with the same number of gates, due to the greater amount of propagation delay in the former.Simulation results for up to 1000 gates are shown in Figure 8.
Figure 9 shows plots for izz settling time vs. num- ber of gate levels for circuits with various gate counts.
In practice, the current is sampled by the BICS only after all the transients due to switching have died down and the current has settled to a steady, low cur- rent value [3].The settling time shown in Figure 9 shows the time when the current has settled to within 5% of the steady, low current value for sampling by the BICS.The settling time for a 10-level circuit, for example, is greater than that of a 5-level circuit with the same number of gates due to the larger propagation delay in the former.For a circuit with a given number of gates, the settling time increases with the increase in the number of levels.For example, for a circuit with 100 gates, the settling time for 3 levels is 10.21 ns and the settling time for 5 levels is 17 ns.The settling time thus has two components, one due to the propagation delay, and the other due to the capacitance at the node to which the current sensor is connected.Thus the    larger the circuit that is covered by a current monitor, the longer the second component of the transient time will be.Another advantage of partitioning is the re- duction of this component of settling time due to the total capacitance.

Effects of BICS on Circuit Performance
The bypass circuit of the BICS offers a finite resis- tance (R') which effectively appears in series with the circuit under test (CUT).This may not cause a sig- nificant problem under test conditions.However, un- der normal operation, the resistance of the BICS ap- pears in series with the CUT and causes an IR' volt- age drop across the BICS.The voltage drop in the BICS causes the effective ground potential of the CUT to be higher than the physical ground, especially during the transitions, thus slowing down the circuit operation.
The propagation delay (tpd) component from the input to the output of circuits with different levels (1, 3, 5 and 10 levels) with different gate count with the implementation of BICS and without the implemen- tation of BICS is shown in Figure 10.The propaga- tion delay (tpd) for circuits with different numbers of gate levels (1, 3,5 and 10) remains fixed with in- creasing number of gates in the circuit, when BICS is not implemented.For example, the propagation delay (tpd) for l-level, 3-level, 5-level and 10-level (shown dotted in Figure 10) are 0.66ns, 4.04ns, 7.58ns and 16.4ns respectively even with increasing number of gates (n), for the case without BICS.
The propagation delay (tpd) for the different levels (1, 3, 5 & 10 levels) with BICS implementation is shown in Figure 10 as solid lines.It may be noted that the propagation delay (tpd) for a given circuit with BICS implementation is greater than that when BICS is not implemented.Also, the propagation de- lay (tpd) increases with increase in the number of gates as the capacitance seen by BICS increases with increasing number of gates (transistors).Table I sum- marizes the settling time (tsettle), propagation delay (tpd) and time for the current tail to settle (tc) for 1, 3, (tsettle) of current for a given CMOS circuit as shown in Figure 8 is a function of the following: tsettle mtpd + f(R', C, Dpa, r, tf) where tpa propagation delay per gate, rn the maximum number of levels in a given CMOS circuit, C total capacitance of the Voo or Ground rail of CUT connected to BICS, R' denotes the effect due to BICS resistance, r, tf rise-time, fall-time of the gate switching to- wards the end.
With the above results, the partitioning of a given circuit becomes very critical as the capacitance at the input of BICS also needs to be considered, in addi- tion to the voltage drop across the BICS and resolu- tion of the BIC sensor.Partitioning the circuit under test into smaller modules reduces the amount of ca- pacitance seen by the BICS.Partitioning reduces the settling time, which in turn helps in performing faster sampling of IDD(2 measurements.The effect of the increase in settling time (ts) with increasing numbers of gates for a given level due to the capacitance (C) is a problem for all BICS designs which rely on virtual ground.
The effect of the lumped capacitance (C) of the circuit and the non-linear resistance (R') of the BICS results in additional propagation delay for the CMOS circuit.This is a problem affecting the operational performance of the circuit caused by BICS.This can be avoided by providing a physical ground pin in addition to the virtual ground pin.This allows the ground pin to be connected to the ground terminal of the system and hence avoids the propagation delay introduced in the circuit by the BICS.This scheme provides for off-line BICS, wherein whenever current sensing is required to be carried out, the BICS is introduced into the circuit by disabling the ground pin and making it a virtual ground.The BICS in this scheme is disabled by connecting the virtual ground terminal to the physical ground, thus avoiding the additional propagation delay introduced due to the capacitance (C).In this scheme, BICS is introduced only during test mode.The off-line BICS scheme suf- fers the disadvantage of switching the circuit into test and normal modes of operation, thus the inability to monitor the IozQ drawn by the circuit on-line.For large circuits with many partitions, it may not be practical to add an additional pin for each partition.For example, for a circuit with 10 partitions, at least 10 extra physical ground pins need to be added.

BUILT-IN CURRENT TESTING OF PARTITIONED ICS
Since each module or subcircuit has its own current sensor, it is impractical to observe the output of every current sensor.One solution to this problem is to propagate the outputs of all the sensors to one observ- able output pin which is designed solely for the sig- nature extractor or information compression unit.This information compression unit maybe imple- mented simply by an OR gate.The outputs from all the current sensors are fed to the OR gate.A counter is connected to the output of the OR gate, as shown in Figure 11, to calculate the total number of times that the detected current IDDa exceeds IDDTth, which is nothing but the signature S.This signature extrac- tor also works correctly if there is more than one faulty module, since in that case S will be even greater than that when there is only one faulty mod- ule.
Figure 11 shows the circuit under test partitioned into n partitions with a BICS for each partition.Ca- pacitor C is the lumped capacitance of the source terminal of all the transistors which other wise would have been connected to the ground terminal if BICS is not implemented.The capacitance (C) plays a cru- cial role in affecting both the operational and test performance when BICS is implemented. 6. CONCLUSIONS Testing of larger ICs using IDDQ monitoring requires larger test times and provides lower resolution be- tween faulty and fault-free devices.Most of the Built-In Current Sensor(BICS) designs transform the ground terminal of the circuit under test to a virtual ground.It is shown that this causes increased delay with increasing number of gates.Performance degradation of the circuit under test due to increased delay with increasing gates is shown.Careful partitioning of large circuits may be required to reduce the effects of virtual ground caused by BICS.An expression for upper bound of the maximum cells (nb) covered by a current sensor is given.Partitioning of large circuits as well as forcing the virtual ground to physical ground using an additional pin may help minimize the limitations of BICS on the performance of circuit under test.Monte Carlo simulation suggests that we can approximate the distribution for the current drawn by the device using a Gaussian distribution.
FIGUREA general current sensor.

HGURE 6
measurement by the BICS.If the sampling of current by BICS is done before the transients have settled, then the BICS would be measuring incorrect, elevated values of switching current.Conversely, if the sam- Input/Output & current waveforms for inverter chain with 5 inverters.

FIGURE 7
FIGURE 7 CMOS circuit with BICS.

FIGURE 8
FIGURE 8 ioo settling time vs. Number of gates for different levels.

FIGURE 9
FIGURE 9 iz)o settling time vs. Number of Levels for various gate counts.

FIGURE 10
FIGURE10 Propagation delay tpd VSo Number of gates for different levels.

FIGURE 11
FIGURE 11 Partitioning and information compression.
ioo settling time vs. # of levels for various gates TABLE