Statistical Module Level Area and Delay Estimation

The increasing complexity of VLSI design process has led to an increasing use of layout synthesis systems. For many components of a high-level synthesis system such as module generators and module generator development environments, an accurate model of area and delay for the layouts generated by a layout synthesis system is extremely desirable. We have experimented with a statistical model for area and delay of function modules. This model is surprisingly accurate for a standard cell based layout synthesis systemmVPNR. The area of adder and shifter modules can be modeled to with in 5% accuracy while the error in delay model is bounded by 4%. This model can be taken through another level of indirection without significant loss in accuracy. The area of all the modules that fit a ripple-template (such as carry-ripple adder) can be modeled with in 30% accuracy. The delay of these modules has a better fit, 15%. The square-template designs (such as array multiplier) have an area model with 1.7% coeificient of variance. In these cases, the model is parametrized by the area and delay of the leaf cells in the template.


INTRODUCTION
Module generators have been used in design synthesis for close to a decade now.High-level synthesis systems have incorporated them in order to generate layouts for datapath modules.They have also been used in stand-alone mode by the system designers.
However, the integration of a module generator into a high-level synthesis system introduces an entirely new set of problems.A high-level synthesis system bases many of its crucial tasks, such as scheduling and allocation, on the layout attributes of area and delay of its datapath operators.Hence, we need a model for the area and delay of the designs produced by a module generator, that can be built into the scheduling and allocation algorithms.In general, this 141 model is parametrized by the datapath width n.Note that the accuracy of these models is of paramount importance since it directly affects the quality of the schedule and allocation.The area and delay modeling gets more complicated for a module generator that can build a variety of designs for a datapath function for the same datapath width.This capability is usu- ally provided to enable a module generator user to explore a broad area-time design space.This type of module generator is indispensable in a similar system level design-space search by a high-level synthesis system.An area and/or delay model for these module generators has to incorporate several design types, i.e. function implementation architectures.
The problem, then, can be stated as follows.The problem input is a module generator which builds a function level netlist in response to the datapath width specification.If the module generator incorpo- rates a large design _space for the given function, it may either choose the most optimal design for the given datapath width on its own or the user might be required to specify the design type in addition to the datapath width.In either case, the area and delay modeling task has to face the existence of multiple design types.The problem output is a set of equa- tions, parametrized at least by one parameter: datap- ath width n, that model the area and delay of the designs produced by the given module generator.Note that the model need not be continuous in n, in the sense that a different set of equations could model the behavior of the module generator for n in the range 1-8 and for n in the range 8-16.Hence the model need not be continuous at n 8 in this exam- ple.
In this paper, we propose to use statistical model- ing as a solution to this problem.In particular, we demonstrate this technique on a specific set of mod- ule generators that use netlist leaf cells and build netlist level function designs.The final layout for these module generators is derived by deploying a standard cell based place and route system, VPNR [Brglez, Kedem [6]].The reason behind using these module generators for adders and shifters was that they were developed by the author [15].The only reason to use VPNR was the easy availability of VPNR expertise and the OASIS compilation environ- ment.Our decision to build module generators for netlist level designs was a pragmatic one.The inte- gration of design-space exploration into a module generator with full-custom layout leaf cells is at best a tedious task.The full-custom layout leaf cells also make the module generator quite inflexible.However, with a netlist leaf cell even the cell area figure A is not available.In fact, the layout area per tipple cell is not even a fixed value A since each leaf cell netlist can be placed and routed differently.One way out of this situation is to see if the area and delay values of the layouts generated by the chosen layout synthesis system for the given module are an acceptably accu- rate statistical function of a model.We explain the statistical layout area and delay modeling idea further in the following.
The module generators are designed for structured datapath functions such as adders, shifters and RAM.
These functions have well-defined analytical area and delay models as a function of datapath width n.For instance, the area of an n-bit carry-ripple adder is expected to be c o + c ln where Cl may correspond to the area of the carry-ripple logic cell.For a full-custom carry-ripple adder design we should be able to get a very good area model from the area of the carry-ripple leaf cell, if we are willing to ignore the aspect ratio, by arranging the leaf cells in a linear array.Similarly, we expect the area of an n-bit parallel-prefix adder to be of the form c o + c log n + c2n + c3n log n.These constants must depend on the layout systemmfor full custom, there might be a set of constants for each individual designer style; for standard cell based placement and route system, the constants depend on the standard cell sizes and the routing algorithms.
For a standard cell based placement and route sys- tem, it is not even evident that the layout system would preserve the known analytical behavior.It may introduce dominant area terms resulting from the routing algorithm's idiosyncrasies.The question then is if a layout synthesis system generates layouts whose area values fit a statistical model.We show that for a variety of adder and shifter designs a statistical area model for the VPNR-generated layouts with in a coefficient of variance (C.V.) 5% can be developed.The delay models show an even tighter coefficient of variance, 3%.This means that with a high probability (at least .9) the area value predicted by the statistical area model is with in 15% of the correct area value.The delay model is within 9% error with probability at least .9. Section 3 contains the details of the experiments and results.
A natural extension of this question is "what does it take to extend statistical area and delay estimation into module generator development environment?".The most common approach to module generator de- velopment environment design is to identify the com- mon, basic building blocks and their relationships.
The system, then, provides either graphical or proce-dural means of specifying a function with these blocks and their compositions.For example, a user wishing to build a module generator for an adder will first choose a design to be implemented, say, a carryripple adder.S/he would then have to represent this design in the environment's form, e.g., either as a collation of some blocks, or as a class in an objectoriented language.An environment is capable of pro- ducing a (module-generator) program from this de- scription.In order to incorporate design-space explo- ration into the resulting module generators, we need area and delay models for a module type.For a mod- ule generator environment we do not even know a priori the type of function for which a module-generator would be built.How can we, then, predict area for the layouts to be produced by not-yet-determined module-generatorma capability, seemingly indis- pensable for a program which can explore design spaces in order to produce a design that matches the area specified by a user in h a units?
The module generator development environments typically rely on a template to represent a type or class of modules.For instance, a ripple template can represent all the tipple designs for adders, counters, parity generators.The particular ripple logic used in each case is different, but the global template is the same, a linear array of cells.A parallel-prefix tem- plate can similarly implement parallel-prefix designs for adders, counters and parity generators.In this case, does there exist a good statistical area model which is parametrized by n and the area of the ripple logic cell for the given function?We show in Section 4 that the coefficient of variance varies from 2% to 30% for the area models.The delay models' coeffi- cient of variance is bounded by 15%.

Previous Work
Chen and Bushnell [3] show a methodology to char- acterize the area requirements of a layout system.Kurdahi and Parker describe a general methodology for estimating the expected area of a netlist in [7].Wallace and Chandrasekhar [18] give a technology-independent technique to derive a delay model for a set of logic equations assuming an underlying struc- ture for the logic.Ji et al. [5] estimate area and delay of an RT level structure given its leaf cells and struc- tural description.But all these methods involve ex- pensive computation for estimating the approximate area for a random netlist.In contrast, the module netlists have a very regular structure and their area as a function of the datapath width n is known a priori.Gajski et al. [ [20,2] considered abstract layout area and delay models for high-level synthesis.The data- path and controller were modeled separately in these models.Kurdahi et al. [12] present an area and delay modeling technique for RT-level designs that allows a high-level synthesis system to undertake design trade-offs.Jha and Dutt [4] also develop statistical models for area and delay of RT level components.We do not know of any previous work in the module generator development environment area and delay estimation.

STATISTICAL BACKGROUND
In this section, we introduce some statistical con- cepts.For more details, the reader is referred to Norusis [ [10], [11]].
The linear regression analysis models a population as a linear function of a variable, y b o + blX.It determines the values for the coefficients b o and b such that the sum of the squares of the distance of the model from the sample data is minimized.This method is also known as the method of least squares.The multiple linear regression builds a model linear in many independent variables, y b o + blX q-b2x2 + + b.Note that any two variables xi and xj are independent if their contributions to the value of y are independent.There will be many instances of two variables in this paper which appear to be dependent functionally, such as xi n and xj log n, but their contributions to y (area or delay) are independent.
Once the coefficient bi's values have been deter- mined b /i, we have a prediction model f /k= 0 /X i.The predicted value 33 models some popu- lation parameter, area and delay of modules in our case.Its accuracy can be characterized by its statisti- cal characteristics such as mean, variance, and stan- dard error.The regression analysis minimizes the prediction error for the mean of the sample data.Hence, for instance, if the input data for area consists of n 2,4 and 9 then the model is most accurate for n 5, the mean of 2,4,9.The error in the predicted value attributable to the difference in the input value and the sample mean is called regression error.In addi- tion, the actual value y and the predicted value 3 can differ.This difference ABS(y ) is referred to as residual error.
What parameters can be used to determine how good a fit does the model provide?A commonly used measure of the goodness of fit of a linear model is R2, the coefficient of determination.It can be thought of as the square of the correlation coefficient between input variables xi's and the dependent variable y.It is also the square of the correlation coefficient between y, the observed value of the dependent variable, and 29, the predicted value from the model, which is 1 SSE SST, where SSE is sum of residual error squares and SST is the sum of residual squares and regression value squares.If all the observations fit the model exactly, the value of R 2 is 1.
Another measure of the goodness of fit is coefficient of variance (C.V.).It is the ratio of the standard error of the estimate and the mean value of the regression expressed as a percentage.The stan- dard error of the estimate corresponds to the standard deviation of the residual error values for a large sam- ple..Hence the C.V. value measures the magnitude of error with respect to the expected value of the parameter.The Chebyshev's inequality says that the proba- bility that the value of a random variable falls with in k times its standard deviation of its mean is at least 1 1 k 2 i.e., Prob{IX-/.tl-< k r} -> 1 1 k where and o" are X's mean and standard deviation respectively.Hence a C.V. of 5% for an area model, for instance, can be interpreted as "the probability that the area value is within 10% of its mean is at least .75.".
Note that the absolute error in a model could be lower than the coefficient of variance.This is because C.V. measures the variance of the whole error sample as a percentage of the mean.However, the points where the error is large may also have a large ob- served value as compared to the mean and hence the error as a fraction of correct value might be smaller than the C.V. value.Hence another measure we report is the largest error.

AREA AND DELAY MODELS FOR MODULES
In this section, we build statistical area and delay models for the standard-cell based placement and route system VPNR [Brglez, Kedem][6] for various adder and shifter designs.The statistical area models have coefficient of variance at most 4.8% and the coefficient of determination R 2 at least .99957.This is a surprisingly good fit.This says that we can predict the area within 5% of the actual value.The RC delay is dominated by the routing capacitance.The routing resistance is ignored in these calculations (as in RNL [8] or ESIM [14]).Only the device resistance is used to compute the delay values.The routing capacitance is proportional to one dimension of the layout intu- itively, which is the square root of the area.It would seem that if the area is tracked so nicely then the wire lengths also might be tracked very closely.We found that the delay can also be estimated within a 2% co- efficient of variance.Let us explain our experiments and results at length.

Experiment
We generated a wide variety of n-bit modules for n ranging from 4 to 128.Specifically, the following adder and shifter designs were considered.
For each of the above mentioned designs we gen- erated the netlist modules for at least 6 datapath widths, usually 4, 8, 16, 32, 64 and 128 bits.Then the standard cell based system VPNR was used to gener- ate the magic layout from these netlists.We con- strained all these layouts to place their input/output signals at the borders.We let VPNR choose a squar- ish aspect ratio.Now we had 6 design points for each expected area profile listed above.We used a statisti- cal package SPSS [11] to perform the multiple linear regression analysis on this set of data.Table I lists all the model equations with corresponding C.V. and R 2 values.Recall that the coefficient of variance (C.V.) is the error variance as a percentage of the mean of area values.Thus all the designs generated by VPNR were within (C.V.) % of the expected area estimate from the prior analysis.A small C.V. value signifies a good fit.A high value of R2, the coefficient of determina- tion, also signifies a good fit.Note that a better R 2 fit need not necessarily guarantee a better C.V. fit.

Observations on Area Models
The area expressions specify the area value in h 2 units.Note that all the modules in the list have a fairly tight fit, an R 2 value at least .999and a C.V. value at most 4.8%.There are several points to be considered in building such a model.data set size: In all the models reported, the data set consisted of only 6 data points, for n 4, 8, 16, 32, 64 and 128.This may lead to the question if the results are statistically valid despite the small data set size.The number of independent variables, the num- ber of terms in the model with large coefficients, in all these models seems to be at most four: a constant and 2 or 3 of log n,n and n terms.The six data points are certainly sufficient to determine four inde- pendent terms.However, it is possible that a larger data set may lead to a better fitting model, perhaps with a lower value for C.V. and a higher value for R2.The reason that it might not be practical to generate a large data set is the effort involved in generating it.One design with a complete layout has to be built for each data point.It has to be extracted and then sim- ulated for delay.The maximum information about the area and/or delay model is derived from the first 4-10 data points.The incremental improvement to the model beyond that is usually not worth the effort of enlarging the data set.We did increase the data set size for the carry-ripple adder to 30 data points.The resulting model is shown in Figure 4.The new area model is given by166002n- 2279112   It's coefficient of variance improves to 1.4% from 1.8% and the R 2 value improves to .99999.average value of sample datapath width: The residual error is minimum at the average of the sam- ple data.It increases as a function of distance from mean.For instance, for a sample data set with n 4, 8, 12, 16, 32, the average value of n is 14.4.Hence this model is most accurate for the values of n in the vicinity of 14.The care should be taken to select the data set in such a way that the average parameter value is closest to the desired range for the model, i.e. if it is known that the model would be primarily used for the range n 32-64 then a data sample with the average value for n 48 will make sense.
layout synthesis system behavior: The analytical model for a carry-tipple adder's area is plain c o + c ln.However, a regression fit to this model had C.V. 22% and R 2 .97871.Adding the log n term to the model makes C.V.
The introduction of n term improves it further to C.V. 1.8% and R 2 =. 99995.This observation leads us to the conclusion that V15NR tends to introduce some log n and n components to the layout area.
Note that the initial combined placement and route phase of VPNR is based on a recursive quadrisection [13] algorithm.It is very likely that the overhead of combining two recursive solutions (channel routing between two solutions) adds some area cost not intrin-  sic to the analytical layout area model.This cost, then, is proportional to the number of recursion stages log n.The n cost can be due to our insistence on a squarish aspect ratio.Note that a carry-ripple adder is primarily a chain (linear) structure.Folding it around to make it squarish must add some signal routing overhead from border to the internal points.
This distance (and hence area) is proportional to n.
We tabulate some of these incremental improvements in the model in Table II with the most improved model, shown in Table I.
The objective of this discussion is to point out that one has to be extremely careful in understanding the internals of the layout synthesis algorithms in order to determine a good model.From the layout synthesis system's perspective, this analysis points out the area factors attributable to the layout synthesis algorithms.Adders 'Ripple-model' and 'Select-model' are the area models while 'data-ripple' and 'data-select' are the actual layout area val- ues.absolute errors: Note that the C.V. value is mak- ing only a statistical statement about the probable values of error.As we pointed out earlier, by Cheby- shev's inequality, a 5% C.V. implies that the predicted value is within 10% of the observed value with probability at least .75 or the predicted value is within 15% of the observed value with probability at least .89.Also note that the errors of this magnitude occur for the values of n away from the sample data aver- age n.For instance, we found the maximum error for a carry-ripple adder between the observed and predicted area values to be at n 4 which was 5.1%.
The average value of n for the sample data for the carry-ripple adder was 50.Note that it doesn't mean that the observed value for n 50 + 46 96 should also have 5.1% error.In fact, for n 128, the error is only .005%!It only says that the values of n further  away from the sample data average n can have large errors.We tabulate the maximum errors for all these designs in Table III.We also show this data graphi- cally for carry-ripple and carry-select adders in Fig- ure 1, for parallel-prefix and carry-skip adders in Fig- ure 2, for select-prefix adder in Figure 3, and for shifters in Figure 5.
The delay values were derived as follows.For all the magic layouts generated by VPNR, we extracted the netlists that contain both the device and routing capacitance.This netlist was used in a simulation by RNL [8], an extension of ESIM [14].It is a switch level simulator based on RC delay model.The rout- ing resistance is not considered in the worst-case de- lay calculations, but the routing capacitance is in- cluded.These delay figures (in nano-second units) were then used for statistical multiple regression analysis by SPSS in a way similar to the area case.Table IV lists the RC delay models for all the adder modules.Note that the value of C.V. is below 2.1% in all the cases except parallel-prefix adder.We also list the maximum residual error for the delay values in Table V.The maximum error did not exceed 3% in all the cases.Figures 6 and 7 show plots of delay models versus simulation data.In the preceding discussion, we have demonstrated that the area and delay models can be built for our module generators using VPNR generated layout area values.The natural question is how can this tech- nique be applied by some one using a different mod- ule generator and layout synthesis method.Here is a summary of steps that can be followed to generate a statistical model.
First determine the analytical area and/or delay model for the module in question.Note that most datapath functions consist of constant terms, n terms, log n terms and n terms.The constant term accounts for any logic that is used only once in- stead of being repeated in several bit slices.The n term accounts for the repetitive structure with re- spect to the datapath width.A log n term could be introduced either by the extraneous routing factors attributable to the recursive nature of the layout synthesis algorithms or it could be intrinsic to the module implementation as in parallel-prefix adder.
Similarly, a n term could either signify the recur- sive algorithm's contribution or it could be the re- petitive structure contribution as in carry-select adder.Hence, a naive model would consist of c o + cln q-c2G -[-c 3 log n.
Build the layouts for at least as many values of n as the number of terms in your model.This will usu- ally mean that at least 4 data points need be gen- erated.Determine their area and simulate the de- signs for their delay values.Use a statistical package to perform regression analysis for this model.Ideally, the regression vari- ables should be presented in the order of their con- tribution to the model.However, their coefficients are not known in advance!In almost all situations, n term carries the highest weight.You will have to choose an order between the remaining terms based on your intuition about the underlying mod- ule.In worst case, all the orders (usually less than 6) can be tried.When the introduction of a term into the regression model gives rise to a higher value of the standard error, you probably have a dependent term.A dependent term always improves the R e value, but degrades the standard er- ror.

MODULE GENERATOR DEVELOPMENT ENVIRONMENTS
In this section, we extend the module level area and delay modeling to module generator development en- vironments.The tricky part here is that the area and delay models are for a template, where the area and delay parameters for the template components are not known in advance.The results are encouraging de- spite this handicap.

Template Specification
Note that a ripple design has a carry-chain type of computation.We view a ripple template as consisting of the skeleton structure shown in Figure 8.The rippie computation is performed in the R cells.There is one R cell for each bit-slice.Sometimes, the actual input bits to the circuit need to be preprocessed to   compute the signal participating in the ripple computation.The I cells at the bottom perform this task.For full generality, the output signals of the R cells are not necessarily the primary outputs of the function.
The O cells postprocess the R cell output into the output bits for the function.Note that I and O cells can be very trivial cells (or even null/empty cells as in the case of a parity-generator).Figure 9 shows these cells for an adder.
Another type of template we consider is the square template as shown in Figure 10.A square design for shifter [17] fits this template with empty B cells.The A cells in the array contain some logic to process the inputs derived from their neighbors.The output of an A cell is also available to its neighbors only.An array multiplier [19] also fits this template with B cells cor- responding to adder cells.In this section, we show that the area of the ripple template layouts produced by VPNR follow a statis- tically derived model with in a coefficient of variance (C.V.) of 30%.Their delay has a much tighter C.V. bound of 14.4%.The square template design area val- ues, on the other hand, fit with in a C.V. of 1.7%.The following experiment was used to determine the area and time models with VPNR.We generated VPNR layouts for three ripple functions (adder, parity-gen- erator and a hybrid counter function) with datapath width n ranging from 8 to 128.The layouts for the three component ceils: R-cell,/-cell and O-cell, for each of these three functions were also generated with VPNR to determine their areas AR, AI, Ao (in h 2 units) respectively.Then the expected area of these layouts ought to fit a statistical profile for Co + c l(A I + AI + Ao)n for some values of the constants Co, Cl.
Once again, we constrained all these layouts to place their input/output signals at the borders.These layouts were also simulated for RC delay with RNL.In addition, the leaf cells L R and O were also simulated for their RC delays to determine T I, Tn and T O re- spectively.Note that the delay of a tipple design should fit the profile Co + cl(Ti + To) + CzTRn.
These area and delay values were put through SPSS multiple linear regression analysis.The models are presented in Table VI.The area model is plotted along with the actual data for ripple designs in Figure 11.The data set in Figure 11 results in R 2 value of .96176.The delay models with the simulation data are displayed in Figure 12.The coefficient of deter- mination, here, is .98101.
We also generated layouts for two square template functions, shifter and multiplier for n 4, 9, 16, 25, 36, 49.Note that n refers to an n-bit shifter design, but in the case of multiplier, it refers to a n-bit by n-bit multiplier.The layouts for the cells A and B were produced to determine the cell area values A A and A n. Note that for a shifter, A n 0. The area profile for square template is Co + Cl Aan + 2C2AB n.Table VI shows the area model for the square template, which has a remarkably low C.V. of 1.7%.The area models are plotted along with the layout data in Figure 13.

Validation
We ran the following experiment for a validation of the statistical area and delay models.We built a mod- Template Area Model vs Layout Area Values for Ripple De- ule generator for an artificially defined ripple tem- plate function (with two bits in the carry-chain).Let us call this module rune.The bit-slice for this func- tion rune is shown in Figure 14.Note that this bit slice has not been optimized for logic minimality.
Getting some area and delay figures for a new ripple design is the sole objective of this exercise.We used this module generator with several area and delay specifications and datapath width (n) values to generate 6 rune designs.The actual area of the layout pro- duced by VPNR from the netlist generated by the module generator was always within 18% of the area estimated by the model.Figure 15 shows a plot of the model-predicted area values vs actual layout data for rune.The delay figures were even tighter--within 14% of predicted values.Figure 16 displays the de- lay-model values for rune along with the simulation delay data.FIGURE 13 Area Models vs layout data for square designs.

CONCLUSIONS
We presented a statistical technique to build models to predict area and delay for modules.It involves generating layouts for many values of the datapath width n with the layout synthesis method that would be employed in generating layouts from the netlists produced by the module generators.We showed that remarkably tight area and delay models for various adders and shifters can be produced for a standard cell based layout synthesis systemnVPNR.The co- efficient of variance (C.E) for these designs was at most 5% with a coefficient of determination (Re) at least .999.The maximum error was less than 10% for every design except parallel-prefix adders.Note that these results do not imply that VPNR is the only well- behaved layout synthesis system.Many comparisons at the International Layout Synthesis Workshop have shown time and again that most of the layout synthesis systems tend to produce designs with area values with in 10% of each other.Hence, it is very likely that such statistical models for area and delay with comparable C.V. and R 2 values can be built for most of the layout synthesis systems.When this technique is tried for area models for templates, instead of modules, the error increases.But, the C.V. is still below 30% for ripple template and is only 1.7% for the square template.Given that the exact area of the leaf cells is not known at the time of model-building, we consider this to be an excellent fit.In summary, we believe that statistical area and delay models have acceptable accuracy.The ease of building them makes a case in their favor.The computation for model-building involves generating many layouts and multiple linear regression analysis, which is not excessive.However, the main advantage comes in the computation savings in area and delay prediction, which involves a simple expression eval- uation.This makes it especially attractive for design- space exploration, where approximate models (cer- tainly errors less than 10% will do) with quick run- time will allow a high-level synthesis system to undertake extensive design space search.

FIGURE 2
FIGURE 2 Area Model vs Layout Data for Skip and Parallel-Prefix Adders 'Prefix-model' and 'Skip-model' are the area models while 'data-prefix' and 'data-skip' are the actual layout area val- ues.

FIGURE 3
FIGURE 3 Area Model vs Layout Data for Select-Prefix Adders 'Selprefix-model' is the area model and 'data-selprefix' is the ac- tual layout area values for select-prefix adders.

FIGURE 4
FIGURE 4 Area Model vs Layout Data for Carry-Ripple Adders with Large Dataset 'Ripple-model' is the area model and 'data- ripple is the actual layout area values for carry-ripple adders'.

FIGURE 5
FIGURE 5 Area Models vs Layout Area Values for Barrel, Square and Linear Shifters

FIGURE 7
FIGURE 7 Delay Models vs Simulation Data for Skip and Par- allel-Prefix Adders.

FIGURE 8
FIGURE 8 The Skeleton Structure of a Ripple Template

FIGURE 9
FIGURE9 An Example of I, R and O Cells for an Adder Gen- erator FIGURE 12 signs.

FIGURE 14 BitFIGURE 15
FIGURE 14 Bit Slice for a Ripple Function func

FIGURE 16
FIGURE 16 Delay Model and Simulation Data Comparison for Ripple Function rune.

TABLE V
Maximum error points for adder delay models

TABLE VI
Area and delay model for ripple and square templates