Monte Carlo Simulations of Impact Ionization Feedback in MOSFET Structures

Monte Carlo (MC) transport simulation is a widely recognized tool capable of accurately obtaining the high energy tail of the electron energy Distribution Function (DF) responsible for impact ionization, oxide degradation and gate currents, I, in MOSFETs. MC simulations and measurements of these hot electron effects have shown that the oxide interface DF in MOSFETs is composed of two parts [1]: the conventional channel electron DF, and a secondary electron DF coming from Impact Ionization (II) FeedBack (FB) [2]. The channel electron DF is enhanced by Electron-Electron (EE) scattering, and at low biases is principally populated by this effect. Although the secondary electron DF, generated by the coupled impact ionization of electrons and holes is usually ignored, it can dominate the


INTRODUCTION
Monte Carlo (MC) transport simulation is a widely recognized tool capable of accurately obtaining the high energy tail of the electron energy Distribution Function (DF) responsible for impact ionization, oxide degradation and gate currents, I, in MOSFETs.MC simulations and measurements of these hot electron effects have shown that the oxide interface DF in MOSFETs is composed of two parts [1]: the conventional channel electron DF, and a secondary electron DF coming from Impact Ionization (II) FeedBack (FB) [2].The channel electron DF is enhanced by Electron-Electron (EE) scattering, and at low biases is principally populated by this effect.
Although the secondary electron DF, generated by the coupled impact ionization of electrons and holes is usually ignored, it can dominate the 13 channel DF tail.The relative importance of the two depends on the channel and substrate doping, drain junction depth, oxide thickness and most importantly, the substrate bias, Vss.This work emphasizes the inclusion of impact ionization feedback in Monte Carlo device simulation, and its implications for carrier heating in sub-micron MOSFETs.In addition, results from a new class of EEPROM devices based on the II FB effect will be discussed.

HEATING BY II FEEDBACK IN MOSFETs
In the following, simulations have been performed using the full-band MC transport simulator, SMC [3], as a post-processor for the device simulator PADRE [4].Doping profiles and device geometry are computed using the 2D process simulator, PROPHET [4], and electric fields are computed for a given bias condition by PADRE.Then, given these fields, SMC solves for the device DFs in a manner similar to [5].For more details, see [6] and references therein.Also, in this section, in order to clarify the essential elements of the II FB process in MOSFETs, EE scattering will not be consi- dered.
Figure illustrates the general phenomenon of II feedback in an nMOSFET [2].Channel elec- trons, el, are injected into the drain where they II forming low energy electron-hole pairs with current II multiplication M1.The secondary electrons, ee leave through the drain while the secondary holes, he, diffuse to the Drain-Substrate Junction (DBJ), are heated by its fields and are injected into the substrate where they II again with multiplication Me forming e3 and h3.The h3 holes leave through the substrate, but the e3 electrons fall back through the DBJ and vertical gate controlled potential drops reaching the oxide interface.This process continues with e3 ionizing leading to a series of pair productions alternating between electrons and holes (II feedback) with multiplications M3, M4, etc.Here, IB Is(1 + M1 + MIM2 + M1M2 M3 +...).The DBJ is in breakdown when this series diverges, but in the following, the devices are not in breakdown and all the Mi < 1.
A LI-I 0.25 tm device with strong II FB effects has been simulated to quantify the feedback effect.Figure 2 shows the potential energy along the channel (from A to B in Fig. 4) and from the drain to the substrate (B to C) with V6s 2V, VDS 3 V. Figure 3 shows the DF integrated over the device domain.The el DF (no II FB) shows a rapid decay for energies above the pinch-off potential energy drop, Vp 2.5 eV.There are no channel electrons above the oxide conduction band discontinuity of about Aox 3.1 eV, but there are many at the ii rate threshold of about 1.1 eV, so IB > 0. The e3 contribution is also shown in Figure 3 (II FB, full 6esec).The channel electrons ionize with M1 0.065, initiating the FB process.The h2 holes ionize with M2 0.02, so that the current carried by the secondary e3 electrons is quite small: Ie3 lie1 M1M2 0.0013.
Although the DBJ is far from breakdown, there is a broad tail extending to high energies > Aox, dominating the el DF above Vp.It is sufficient to consider only the e3 secondary electron DF since the DBJ is not in breakdown.
The energies of e3 electrons reaching the oxide interface can be as great as E nax q VDB + q Vbi+ 6see, where esec is the energy of formation of the e3 electrons by the II of the h2 holes, and qVbi is the   built-in junction potential.Typically, q Vbi 0.7 to 0.8 eV.The importance of esec (a table generated during the II rate calculation [7] from the full Si band structure) is clear comparing the full gesec curve to that computed with gesec=0 (Fig. 3).The full curve extends to high energies uniformly, whereas the curve with no energy of creation begins to drop rapidly for energies near q VIB + qVbi 4 eV.

GATE CURRENTS BY II FEEDBACK
It is clear from above that VBs should have a large effect on the tail of the DF.When a negative substrate bias, Vs < 0, is applied, changes in the channel potential are small, but q VD changes rigidly with Vs (see Fig. 2).Therefore, el heating and I are not strongly affected, whereas e3 heating and I6 should change exponentially.Figure 4 shows the electron DF integrated along the oxide interface for VBs 0, -1 and -2 V.The low energy channel DF (below 2.5eV) changes very little ( < 2 X) whereas the secondary tails responsible for I6 change exponentially ( 1000 X) as Vs goes from 0 to -2 V.This is confirmed experimentally in Figure 5 which shows I6.=I6/Is versus IR=I/Is for Vies V6s at various Vs.For a given value of IR (which represents an equivalent channel heating) I6R increases exponentially as Vs is made more negative.This result contradicts the "effective temperature models" which predict a direct correlation between IR and IR [8] based on the assumption that both currents are gener- ated by one thermalized channel DF. Figure 5 also shows a comparison between simulated and measured I6R and IBR.Qualitative trends are clearly reproduced by the simulation.Considering the approximate treatment oxide injection and transport, the remarkably good quantitative agreement with experiment is more questionable.
In addition to enhancing the high energy tail, II FB also changes the spatial distribution of the hot carriers.Figure 6 shows the number of hot secondary electrons with energies above the oxide barrier (3.2 eV) as a function of position along the oxide interface (conditions of Fig. 4).As Vs is made more negative, the hot carriers spread out into the channel, enhancing L6 when V6s is low.
For I generation, the fields in the oxide at the Relative Substrate Current IBR 10"2 FIGURE 5 Measured and simulated/(JR versus IBR for diff- erent Vss on a LCH--0.25 gm device.Squares, 0.5 V steps and circles, 0.1 V steps down from VDS V(Js 4 V. FIGURE 6 DFs integrated at the oxide interface for condi- tions of Figure 2.
point of injection must accelerate the electrons to the gate electrode.When V6D <0, accelerating fields only exist in the channel back towards the source.The secondaries, coming from the sub- strate, provide oxide injection at these points.This figure suggests that 16 enhancement by VBs is stronger the smaller V6s is compared to VDs.This is confirmed in Figure 7 which shows measured gate injection efficiency, I6R versus V6s .as a function of VBs for a 0.25 lam device [9].Note also that for VBs -3 V there is strong gate injection for VGs all the way down to the threshold voltage of the device, 1.3 V.For V6s, 1.3 V, IG will go to zero with the sub-threshold drain current.
TWO-PART DISTRIBUTION FUNCTIONS 10"6 10. 7   10"8  As noted in the introduction, EE scattering can extend the channel DF to higher energies than Vp and VDS [1, 10--11].This EE enhanced channel DF will compete with the II FB at high energies.
The relative importance of the two depends primarily on m2 and T, factors which are con- trolled primarily by the sharpness of the DBJ junction and the strength of the gate field.M2 and T become large for shallow junction devices with high channel or junction doping, and as shown above, negative Vss.One easy way to determine the importance of the two is through sensitivity to Vs.The channel DF is fairly independent of Vs, even when EE scattering is included, but the II FB tails are strongly affected by it.In general, for a hot electron effect with a threshold energy of ETH, there will always exist a Vs such that for VBs < Vs, the secondaries will dominate the channel DF.For I, ETH is 3.2eV for points on the interface where gate fields are favorable for injection.When VBs < Vs, dI/dVBs will become large.In devices of older technology generations in which II FB effect tend to be weak, Vs[ can be as high as -7V [1]. Figure 8 shows I versus VBs measured on two devices.The curves have been normalized by the same factor for both devices.DEV1 is a 0.25 lam device with strong FB effects similar to that of Figure 3, and DEV2 is a LCH 0.32 lam device optimized for high I (see below).The measured data was obtained by measuring floating-gate VTIq shifts, and the simu- lations were performed with both II FB and EE scattering.In DEV1, the FB DF begins to dominate I for Vs < -0.5V as shown by both measurement and simulation.In DEV2, the FB DF controls I even at Vs=0V.Oxide DFs for DEV1 in Figure 8 are shown in Figure 9. -VBs (V) FIGURE 8 Measured and simulated Ia for two different devices: DEV1, similar to that in Figure 2, and DEV2 a LcH=0.32 gm device optimized for high Ia.IGR t 0.5 0.9 1.3 1.7 2.1 2.5 2.9 3.3 3.7 Electron Energy (eV) Approximate 1B and Ia thresholds are labelled as in Figure 4.

THE CHISEL FLASH EPROM CELL
Nonvolatile memories (Flash EPROMs) use hot carrier gate injection for programming.Previous devices have relied on channel hot electron injection for programming which requires high Vs (10V or more) and Vrs (5-6V) to achieve adequate programming times of 100 gs or faster.MC simulations and measurements like those shown above suggested that the II FB effect could be utilized to greatly improve programming performance for low Vr)s and Vas, leading to a lower power, better scaled EPROM cell.Based upon the physical understanding provided by these simulations, Flash EPROM devices and a writing methodology were designed to optimize the II FB process to produce a CHISEL (channel initiated secondary electron) EPROM cell [9].
Simulation optimization of the cell concentrated on the following: heavily doped junctions increase substrate current, hole multiplication, M3 and e3 electron transmission to the gate, T; shallow junc- tions enhance M1 and T; and, Vs < 0 enhances M2 and T. CHISEL memory devices (Fig. 10) were fabricated by forming a stacked gate on nominal 0.25 lam nMOS devices exhibiting thin oxides and shallow junctions (tox 6 nm, xj 75 nm).Because this device is based on a fully scaled CMOS technology, it is ideal for scaling into the deep submicron regime.Boron halos were added to increase junction doping, hence, M2 and T. Most importantly, a VBs < 0 writing scheme was adopted.control gate bias of 4 V; efficient programming for times less than 100 gs can be attained with biases much lower than standard Flash devices require.Note also that the cell has strong programming until it turns itself (high IG with floating gate potentials down to the cell threshold voltage-Fig.7). Figure 12 highlights the strong writing time dependence on Vs as anticipated.

CONCLUSIONS
Physically based MC transport simulation have clarified the importance of II FB and the two-part nature of the high energy DF tails in sub-micron MOSFETs, showing good agreement with experi- ment.This knowledge has led to the creation of a new class of scalable low voltage, low power EPROM devices.

M h 2 FIGURE
FIGURE Diagram illustrating II feedback in MOSFETs.

FIGURE 2 FIGURE 3
FIGURE 2 Potential energy through LcH 0.25 tm device of a 0.25 tm process from A-B, B-C (Fig. 1).

FIGURE 4
FIGURE 4 DFs integrated at the oxide interface for condi- tions of Figure2.Approximate energy thresholds for substrate currents (IBR) and gate currents (I6R) are labelled with arrows.

FIGURE 7
FIGURE 7 Measured /(JR for different Vas as a function of V(js on a LCH =0.25 gm device.

FIGURE 9
FIGURE 9 Simulated interface DFs for different VBs on DEV1 for Figure 7 including II FB and EE scattering.

Figure 11
Figure11shows CHISEL cell programming transients for Vas -VBs 2.5 and 3 V and a

FIGURE 12
FIGURE 12 Time to reach a vth change of 1V during programming of a CHISEL EEPROM cell.

FIGURE 11
FIGURE 11 Measured programming transients for a CHI-SEL EEPROM cell.