Syndrome Signature in Output Compaction for VLSI Built-in Self-Test

In this paper, we focus on the use of signature-based output compaction technique for 
built-in self-testing of VLSI circuits. We give algorithm for single-output and multiple-output 
signature generation using exhaustive test patterns extending the syndrome conccpt. 
The signature wc develop is a functional signature and is very effective for both input 
and internal line fault detection, as seen from simulation on various benchmark circuits. 
The signature generators can bc easily implemented using the current VLSI technology.


INTRODUCTION
As the digital circuit technology is moving to high densities of integration, built-in self-testing (BIST) has bccornc a primary issue in the realm of VLSI circuit design.Techniques for design for testability and built-in self-test consider the testing problem during the design stage of digital devices and have bccn found to bc extremely effective.The central idea behind built-in self-testing or BIST is to have the chip test itself.This technique generates test patterns and evaluates output responses inside the chip [4, 9, 12].It is already well recognized that BIST can significantly improve the testability of VLSI chips and save testing time as well.
The test patterns used in BIST can be either random or exhaustive.Exhaustive test patterns have the following advantages over random test patterns: test patterns can be generated with relative ease, no specific fault models arc required, and a high fault coverage can be achieved.
However, the main drawback of using exhaus- tive test patterns is the exponential growth of test length with increase in the number of inputs [8].*(on sabbatical leave from Dept. of Electrical Engineering, Faculty of Engineering, University of Ottawa, Ottawa, Ontario, Canada KIN 6N5).tCorresponding author.
The test output responses in BIST are com- pressed by output response analyzer into signa- ture.The signature is compared with a known correct value, and faults are detected if a match does not occur.The various available output compaction techniques include parity-bit checking [1 3], transition count [6], ones count [11], Walsh coefficients [7,13], and linear feedback shift register or LFSR [5].Based on these approaches, the compressed response data can be used to evaluate the correctness of the circuit under test (CUT).
In this paper, we have proposed an output data compression technique called syndrome signature, particularly suited for exhaustive testing of VLSI circuits.The syndrome signature is based on and an xtension of the novel idea of syndrome of a circuit originally conceived by Savir [10] and is related to the number of minterms ralized by the corresponding switching function.The signature derived is an (n + 1)-element vector consisting of the primary syndrome of the function and n other subsyndromes corresponding to the subfunctions obtained by setting each of the n input variables to 0 or 1.The proposed tchnique is implemented on various ISCAS 85 benchmark combinational circuits (both single-and multiple-output), and the results look very encouraging.

SYNDROME SIGNATURES
A single-output syndrome signature is defined as follows.For an n-input single-output combina- tional switching function F with input variables Xl,X2,...,xn, the syndrome signature s(F) of F is-given by an (n+ 1)-element vector s(F)= (So, s1,...,Sn) where So=so(F) and si(F)= si(Fio), 1, 2,... ,n, so denoting the primary syndrome, while s denoting the subsyndrome of the subfunc- tion (Fg) obtained by setting the th variable in F equal to b (0 or 1).I. The syndrome signature s(F) of F is given by the five-element vector: s(F)= 3/8, 5/8, 1/2, 1/2, 1/8) where So so(F) 3/8, and si si(Fio), 1,2,...,4, so denoting the primary syndrome of the function F, with s representing the syndrome of the subfunction (F) obtained by setting the th variable in F equal to b (0 or 1) as shown in Table I.
Figure shows a straightforward implementation of this (n + 1)-element signature in which the (n + 1) bit streams of interest are directed towards syndrome registers with equality checkers as an extension of the scheme as used for primary syndrome by Savir [10].Syndrome signature for a four-variable function X4 f fl f2 The concept of single-output syndrome signa- ture can be readily extended to the multiple-output case.Evidently, the simplest strategy to extend the single-output syndrome signature to the multiple- output case is to generate a separate signature for each output.Given an n-input m-output combina- tional circuit, a multiple-output syndrome signa- ture is generated by EXORing all the outputs to produce a single new output which is then fed to a single-output syndrome signature generator.
Figure 2 shows the proposed implementation of a multiple-output syndrome signature.Consider as illustration of multiple-output syndrome signature the following example.
Example 2 A 4-input 2-output function together with its multiple-0utput syndrome signature is given in Table  II.THEOREM A syndrome signature s(F)=(So, S1,...,Sn) for an n-variable switching function F is a functional signature.Proof The proof of the theorem follows ob- viously since a syndrome signature does not depend on the particular implementation involved in its realization.THEOREM 2 A syndrome signature s(F)=(So, Sl,..., Sn) for an n-variable switching function F is test-order independent.
Proof It is evident that the order in which the exhaustive test patterns are generated has no effect on the number of minterms realized by the function F as well as by the n subfunctions si(Fio),i 1,2,..., n, and hence in the signature.THEOREM 3 A syndrome signature s(F)=(So, Sl,...,Sn) for an n-variable switching function F is nonuniform.Proof For an n-input arbitrary combinational function F, the parity-bit signature s(F) of F is uniform since all of the 2 Cn+ 1) possible (n + 1)-bit signatures are equally likely to result.With most counting procedures, this is, however, not the case.Some signatures are more likely to occur than others, thus making the signature nonuni- form.
3. SYNDROME SIGNATURE PROPERTIES Some desirable properties of syndrome signature s (F) (So, Sl,..., Sn) for an n-variable switching function F are summarized below: To prove the nonuniformity of the syndrome signature, consider the first element So of the syndrome signature s(F).Now So is the syndrome of F and can have any value (nonnormalized) between 0 and 2n.Now there can be 22n possible ways of assigning 2 n input combinations to F, and of these exactly 2Cr result in an F with the same number of minterms or syndrome K. Hence, the probability that the function F has the syndrome K (0<_K_<2n) is 2CK/22, which obviously is a function of K, unlike the probability of its parity p(F) being 0 or 1, which is 1/2.We can similarly prove this for the other elements of the signature s(F).Consider, for instance, the (i + 1)th signature element si, 0 < _< n, X2 X3 x, 0,..., Xn)] s(F') where F' (Xl, x2,... x i= 0,..., Xn) is a subfunc- tion of (n-l) variables xx, x2,...,xi-x, xi+ 1,...,x,,.
Following identical reasoning as before, we can again show that this (i + 1)th element of s(F) has a probability dependent on its syndrome value.
Thus, we conclude that all different (n+ 1) elements of the signature can have any value (normalized) in the domain {0,1}, and therefore the signature is nonuniform.
The main advantage in using a syndrome signature rather than the primary syndrome is to achieve fault coverage of existing circuits with- out taking resort to a testable design which is impossible for off-the-shelf circuits.A fault which may not be syndrome testable could be syndrome signature testable.Now an important question that arises is: is the syndrome signature going to work for every case of single fault in a given circuit?The answer is obviously no, though it will work in most of the cases as our intensive experimentation with benchmark and other cir- cuits conclusively shows.THEOREM 4 Two n-variable switching functions F1 and F2 comprised of the same number of minterms m and thus having the same syndrome K=m/2 n must have at least one subsyndrome corresponding to the subfunction (Fib) obtained by setting the th variable in both F1 and F2 equal to b F (0 or 1) different, i.e., si(flo) si( 2o), in order that F1 and F2 are syndrome signature testable.
Proof The theorem follows from the very notion of syndrome signature testability.[5] COROLLARY If functions F1 and F2 are not syndrome signature testable because si(Fo si(Fio), then the implication is simply N(2iF) # N(2iF2), where N(2iF1) and N(iF2) denote respec- tively the number of minterms in the reduced functions $iF1 and 2iF2.THEOREM 5 Two n-variable switching functions F1 and F2 comprised of the same number of minterms m and thus having the same syndrome K m/2 n and F F2, may not have their syndrome signatures s (F1) and s (F2) different.Proof We will prove the theorem by considering different situations in which F and F2 having the same number of minterms m, some of which are different.
Case I m-1 minterms are identical, and only one minterm is different.
Obviously; since the functions consist of the same number of minterms, their primary syndromes are identical, i.e., so(F1 )= so(F2).Assume that the minterm m of F1 is different from the minterm m2 of F2.If we now examine the n-tuples corresponding to minterms ml and m2, obviously ml and m2 must differ in at least one variable position, say xi.Here, xi is primed in one and unprimed in the other.Hence N(i F1) # N(i F2), N denoting the number of minterms in the res- pective reduced functions, according to Corollary 1.Thus, si(ro si(Fi2o), and the syndrome signatures are different.
Case 2 m-2 terms are identical, and two minterms are different.
Assume ml, mE of F1 are different from m, m of F2.Then, ml, m2 and m, m must differ in at least two variable positions, say xi and xj.In this case, N(,iF1)--N(,iF2) as well as N(2jF1)--N(2jF2), and hence si(F]o)= si(Fio)and sj( Fo sj(Fg2o).
Thus, there may bc two switching functions comprised of the same number of mintcrms and having the same primary syndrome but might have some identical subsyndromc as well.This implies that their syndrome signatures arc also identical.
Case 3 Similarly, wc may consider the case where FI and F2 arc identical in m-r mintcrms and differ in r mintcrms, and can conclude that their syndrome signatures for the case could possibly bc identical.
Thus, the theorem follows in general.
The following results are related and important in the context of syndrome signature testability.THEOREM 6 Consider two n-variable switching functions F1 and F2 and let F1 and F2 differ in M minterms.Then the minimum number of variables in whose assignments in the truth table these must differ equals

[log2M]
where M=N1 + N2, N1 and N2 being the terms in F1 and F2 respectively which are different (NI N2= M/2).COrtOLLARY 2 Let F1 and F2 be two n-variable switching functions and let F1 and F2 have M of their minterms different.Let F1 and F2 need [log2M] variables with all their possible combina- tions in such a realization.If any variable xi has equal number of O's and l's in M/2 minterms in F1, any input line fault in xi cannot change F1 to F2 having the same distribution of O's and l's.That is, the distribution of O's and l's must be different and as such N(2iF :/: N(iF2) and si(F]o) # si(Fo) and hence the subsyndromes must be differentfor at least one such xi. 4. VLSI IMPLEMENTATION ISSUES The primary hardware in the implementation of the proposed signature generator is the syndrome register which can be readily implemented by using a counter.However, since the proposed signature generator, besides recording the primary syn- drome, needs to record, for an n-variable function, n other subsyndromes, si (Fio), each corresponding to one of the variables, xi, in a parallel implemen- tation of the signature generator we need to use a total of n + counters, the first one counting from 0 to 2 n-1, while the rest n counters counting from 0 to 2n-l-1 each.This apparently leads to an excessive overhead in incorporating the signature generator in a self-test environment.This is obviously a drawback if the implementation has to be strictly a parallel implementation.
One simple way to overcome this obvious shortcoming of the proposed generator is to use a serial implementation.In the serial implementa- tion a single counter can be used to record both the primary syndrome and the other subsyndromes.
The amount of storage is the same although RAM is smaller than flip-flop.The test strategy can be appropriately modified to take into account the nature of implementation.
Finally, the recent, advances in VLSI technology may not prove to be a deterrent even in the parallel implementation of the signature generator.The inclusion of only binary counters consistent with the number of primary inputs may not be big hardware overhead afterall, while compared with the complexity of the original circuit that needs to be tested using BIST.

SYNDROME SIGNATURE ALGORITHM
A procedure describing an algorithm for testing a circuit for syndrome signature testability is pre- sented here.The algorithm first calculates the fault-free syndrome of the circuit and then cal, culates the faulty syndrome for any given fault in the circuit.If the two syndromes are different, the circuit is syndrome testable and the procedure stops; otherwise, it proceeds with the signature calculation and tests for syndrome signature testability.Procedure 1.Given the number of inputs n, calculate the number of rows and the number of columns.2. Given the faulty input and the fault in it, start the process of initialization: X(n) 0 Fault-free input array XX(n) =0 Faulty input array Asum 0 Sum of fault-free outputs, whenever the output is 1.Final value of this will give the fault-free (actual) syn- drome.
Fsum 0 Sum of faulty outputs, whenever the output is 1.Final value of this will give the faulty syndrome.and also, for rn 1, n   Asubs(m) 0 Fsubs(m) 0 Sum of the fault-free outputs for each of the reduced functions, whenever the output is 1.Final value of this will give the actual subsyndromes.Sum of the faulty outputs for each of the reduced faulty func- tions, whenever the output is 1.Final value of this will give the faulty subsyndromes.
Main calculation loop Generate next fault-free and faulty input pattern (to start with, an all O's combination will be the first fault-free input pattern and an all O's combination with a given fault inserted will be the corresponding faulty input pattern).
Calculate actual and faulty functions, aF and fF respectively and perform the following assignments: If ae 1, increment Asum by Iffe 1, increment Fsum by 1   Now calculate fault-free and faulty subsyn- dromes as: For m= 1, n If X(m)= 0 and ae increase then, Asubs(m) by If X(m)= 0 and fe= increase then, Fsubs(m) by Repeat Step 3 until all the combinations (2n) are done.4. The decision to be made here is: Is Asum equal to Fsum?
If false, then the circuit is syndrome testable and goto Step 2; If true, try syndrome signature testing and goto Step 2 until all faults of interest are analyzed.
Note Division by 2 n on final Asum and Fsum and by 2 n-1 on final Asubs(m) and Fsubs(m) are not performed here (according to the definitions of syndrome and subsyndromes), as we are doing only the comparison.Also, this avoids the round- off errors while computing these values as the circuit size increases.

EXPERIMENTAL RESULTS
To verify the proposed syndrome signature method, simulations were performed on combinational circuits.The simulator (implemented.on a 486 PC) consists of an input pattern generator, logic simulator, output compressor, and fault generator.All possible single stuck-at faults were introduced on primary input lines and on internal lines of the ISCAS 85 benchmark circuits, and the outputs were compressed by syndrome signature technique.Fault-free signatures were compared with the faulty signatures using syn- drome counters.
In general, the dominating factors in the simulation were the number of input patterns and the number of faults that were injected.Some of the benchmark circuits are not very large and can be handled quite easily whereas some others are really large with respect to the number of primary inputs, internal lines and primary outputs.Since our method of testing using syndrome signature (in case the primary syndrome fails) is exhaustive, as far as input test patterns are concerned, storage and time become a problem if the circuit has more than 20 inputs.One obvious way out of such a situation is to partition the circuit into certain subcircuits depending on the dependence of a particular output on a proper subset of the inputs to make the problem tractable.We used this technique in the case of large benchmark circuits.
The results obtained can be considered to be sufficient to show the implementation of the proposed technique on large combinational logic circuits.We have considered both, the primary input as well as the internal line faults.Since our major objective was only to see how the bench- mark circuits relate to our concept of syndrome signature for detection of single faults, no attempt has been made to keep track of the CPU time.
It can be seen from the results that benchmark circuits "C17", "CKT" and a subcircuit (considering only that output which depends on less than 20 inputs) of "C432" are syndrome testable for both input and internal line faults.The fourth circuit, "C880", was partitioned into several subcircuits.Only two subcircuits of "C880" were considered for experimentation, one with 13 inputs and 9 outputs and the other with 10 inputs and 1 output.For some input and internal line faults, these subcircuits are syndrome testable, while for some they are syndrome signature testable.There are some faults which are neither syndrome nor syndrome signature testable.
Tables III and IV show the number of faults missed by syndrome (and their percentage) as well as the number of faults missed by syndrome signature (and their percentage) with respect to the total number of faults injected in each case of single-output and multiple-output circuits.In our simulation results, in case of single-output circuits, syndrome signature has provided the same fault coverage as that of syndrome, but for multiple- output circuits syndrome signature has given better fault coverage than syndrome.
Since in most of the multiple-output benchmark circuits we used circuit partitioning, we never had to consider number of inputs exceeding 18 which generates 218 test patterns and could be handled without appreciable difficulty.With today's com- puting power, normally 22 test patterns could be generated in less than ms and as such testing a particular fault of interest should not be much of a problem, even if the syndrome signature (which uses exhausti-ce test patterns) needs to be used.Obviously, the signature would be working in most of the cases where the syndrome fails, though there may be cases where this signature might also fail.

CONCLUSIONS
In this paper, we have proposed an output data compression technique called syndrome signature, particularly suited for exhaustive testing of VLSI circuits.The syndrome signature is based on and an extension of the novel idea of syndrome of a circuit originally suggested by Savir [10] and is related to the number of minterms realized by the corresponding switching function.The results of implementation, on some ISCAS 85 benchmark circuits (involving both single-output and multi- ple-output circuits) look very promising.Some circuits which according to Savir need extra inputs in order to make them syndrome testable, are shown to be syndrome signature testable.Also, the signature generation discussed for multiple-output circuits seems to work and preserves all the desirable properties of the single-output response analyzer.Masking effect of the proposed signature generator does not seem to be very high as only one case was reported from 11 sample circuits, use although an extensive simulation is needed for this statement to hold true, which is an important measure of a good compression technique.Though this paper is not primarily about the VLSI implementation of the proposed signature generator, some thought has been given in this direction.The size of the compactor seems high as compared to the commonly used methods.The counters will require O(n2) flip-flops and O(n2) XORs and ANDs.In an n-input combinational circuit, this seems an excessive overhead in incorporating the signature generator in BIST environment.If the implementation is strictly a parallel implementation, this can be considered as a drawback of the proposed signature generator.On the other hand, the serial implementation has the advantage of requiring only n flip-flops, but, a disadvantage of requiring n.2 n tests (thus increas- ing the test time).The number of memory cells required is the same as that of in parallel implementation.
As the main drawback of exhaustive test patterns is their exponential growth with the number of inputs, such exhaustive testing is acceptable in cases (most of the benchmark circuits) where combinational circuits can be partitioned into circuits of under 20 inputs to keep the testing time under control.
Further research in this area needs to focus on relative effectiveness of the syndrome signature technique as a useful test compaction tool for fault detection through implementation of many more real world circuits where conventional syndromes fail.Also, implementation of such a signature in VLSI could be a real worthwhile sequel to the whole exercise.
Dr. Das edited jointly with P. K. Since 1994, she is working for Tecsis Corporation where she is developing software applications for software assurance, databases for medical applica- tions and web based tools and applications.Her interests are in developing applications for large software systems.
Wen-Ben Jone was born in Taipei, Taiwan, Republic of China.He received the B. S. degree in computer science in 1979, the M. E. degree in computer engineering in 1981, both from National Chiao-Tung University, Taiwan; and the Ph.D. degree in computer engineering and science from Case Western Reserve University, Cleveland, OH, in 1987.
In 1987, he joined the Department of Computer Science at New Mexico Institute of Mining and Technology, Socorro, where he was promoted as an associate professor in 1992.He has been with the Department of Computer Engineering and Information Science, National Chung-Cheng Uni- versity, Chiayi, Taiwan, R.O.C since 1993, and is currently a full professor.He was a visiting research fellow with the Department of Computer Science and Engineering, the Chinese University of Hong-Kong, in 1997 summer.
His research interests include fault-tolerant computing, VLSI design and test, and computer architecture.He has published more than.60 papers and served as a reviewer in these research areas in various technical journals and confer- ences.Prof. Jone is also listed in the Marquis Who's Who in the World (15th Edition, 1998).He has also served on the program committees of VLSI Design/CAD Symposium (since 1993, in Taiwan), 1995, 1996  Dr. Amiya R. Nayak got his B. Math in Computer Science from the University of Water- loo, Waterloo, Ontario, Canada in 1982, and his M.Sc.and Ph.D., also in Computer Science, from the Carleton University, Ottawa, Ontario in 1986 and 1991, respectively.Dr. Nayak worked for the Canadian Marconi Company in Kanata, Ontario for about 12 years before he moved to NORTEL in Ottawa as a technical consultant.
Dr. Nayak is an Adjunct Professor in the School of Computer Science at Carleton University.He is

FIGURE 2
FIGURE 2 Proposed implementation of multiple-output syndrome signature.

TABLE II Multiple
-output syndrome signature X4

TABLE IV
Srimani a book entitled, Distributed Mutual Exclusion Algorithms, published by the IEEE Computer Society Press, Los Alamitos, CA 1992 in its Technology Series.He is also the author jointly with C. L. Sheng of a text on Digital Logic Design being published by Ablex Publishing Corporation, Norwood, NJ.Dr. Das serves as the Co-Chair of the IEEE Computer Society Students Activities Committee from Region 7 (Canada).Dr. Das is a Fellow of the Institute of Electrical and Electronics Engineers (IEEE), Inc. (with Membership in the IEEE Computer Society, IEEE Systems, Man, and Cybernetics Society, and IEEE Circuits and Systems Society), and a Member of the Association for Computing Machinery (ACM), U.S.A.He was elected a Fellow of the IEEE in 1994 for contributions to switching theory and computer design.Dr. Das is the 1996 recipient of the IEEE Computer Society's highly esteemed Technical Achievement Award for his pioneering contribu- tions in the fields of switching theory and modern digital design, digital circuits testing, microarchi- tecture and microprogram optimization, and combinatorics and graph theory.On sabbatical leave from the University of Ottawa, Dr. Das is presently with the Department of Electrical Engineering and Computer Sciences, Computer Science Division, University of Califor- nia, Berkeley, CA.Nita God received the Bachelor's degree in Electronics and Telecommunications in 1985 from MBM Engineering College, Jodhpur, India and the Master's degree in Electrical Engineering in 1994 from the University of Ottawa, Canada.
AsianTest Conference,1995-1997Asia and South Pacific Design Automation Conference.Dr. Jone received the Best Thesis Award from The Chinese Institute of Electrical Engineering, (Republic of China), in 1981.He is a member of IEEE and the IEEE Computer Society Test Technology Technical Committee.