Analysis of Q 0-Independent Single-Electron Systems

Correlated single-electron tunneling [1] is a promising candidate for the physical basis of a new generation of integrated digital devices capable to replace the conventional semiconductor VLSI circuits beyond the 30-nm minimum feature size frontier. However, there are several serious problems on the way to practical integrated single-electronic circuits. Firstly, attempts to directly imitate semiconductor digital circuits by replacing FETs by SETs (Single-Electron Transistors [2]) would lead to relatively large power dissipation at very high integration level (~ l0 II transistors per cm:z) [1-3]. This problem may be circumvented by using one of the Single-Electron Logics 1, 2, 4] where digital bits are presented by single electrons and static power dissipation is negligible. Secondly, in order to avoid thermally induced digital errors, the structures with extremely small capacitance, C~ O.OleZ/kBT, and hence of extremely small size should be employed [3]. For room temperature operation, this results in the need of ~l-nm patteming of circuits. Finally, the switching thresholds of digital single-electronic devices are very sensitive to charged impurities trapped in their non-conducting environ-


I. INTRODUCTION
Correlated single-electron tunneling [1] is a promis- ing candidate for the physical basis of a new generation of integrated digital devices capable to replace the conventional semiconductor VLSI circuits beyond the 30-nm minimum feature size frontier.However, there are several serious problems on the way to prac- tical integrated single-electronic circuits.Firstly, attempts to directly imitate semiconductor digital cir- cuits by replacing FETs by SETs (Single-Electron Transistors [2]) would lead to relatively large power dissipation at very high integration level (~l0 II tran- sistors per cm:z) [1][2][3].This problem may be circum- vented by using one of the Single-Electron Logics 1, 2, 4] where digital bits are presented by single elec- trons and static power dissipation is negligible.Sec- ondly, in order to avoid thermally induced digital errors, the structures with extremely small capaci- tance, C~O .OleZ/kB T, and hence of extremely small size should be employed [3].For room temperature operation, this results in the need of ~l-nm patteming of circuits.Finally, the switching thresholds of digital single-electronic devices are very sensitive to charged impurities trapped in their non-conducting environ- ment [1][2][3].For example, a single charged impurity located near a conducting island of the device, may shift its background charge Q0 by AQ 0 e, while the switching thresholds are e-periodic functions of Q0.
The objective of the present work is to suggest Q0insensitive single-electronic devices which may allow the last problem to be avoided, and also facilitate fabrication of the single-electron circuits by softening size requirements by a factor of ~5 (i.e.allowing ~5 nm minimum feature size for room-temperature operation).

II. THE OPERATION PRINCIPLE
The basic idea of the Q0-independent operation of the capacitively-coupled single-electron transistor is demonstrated in Fig. 1.The "source-drain" current I through the transistor is a e-periodic function of Oo+CgUin with amplitude A/~eG/C, where G and C are the tunnel junction conductance and capacitance, respectively, while Cg is the gate capacitance.The randomness of the background charge Q0 makes the device response to small signals AUin unpredictable.Let us consider, however, a ramp-up of Uin by AUin > e/Cg.The transistor response will be an oscillation of ...L SET _J_ C tunnel junction small conducting island AI FIGURE (a) SET-FET transistor system and (b) transfer function of the single-electron transistor (schematically) the current I with the full swing equal to AI, regard- less of Qo.After amplification (say, by a FET sense amplifier) this response may be rectified and serve as the output signal Uout.In order to prevent its contami- nation by the Q0-dependent dc background, a block- ing capacitor C b may be used between the SET and FET stages (Fig. a).In contrast to the logic circuits based on SETs [3], our devices do not require the voltage gain by SETs.This considerably increases the maximal operation temperature: a reasonable modula- tion of the I-Uin dependence is achieved up to kBT O. e2/C.III.ULTRADENSE SET/FET DYNAMIC RAM As an example of the application of this general con- cept, consider a non-volatile dynamic RAM combin- ing SET-based cells and FET sense amplifiers (Fig. 2).As in traditional non-volatile semiconductor memories [5], digital bits are stored in the form of electric charge Q of a floating gate.In our case the gate lnay be extremely small (of the order of 10 nm) and the charge is just a few electrons.The charge may be changed by its injection/extraction via an element with a sharp conduction threshold V t.We have con- sidered two possible implementations of this element.The simplest option is to use just a graded dielectric layer with Fowler-Nordheim tunneling above Vt [5].
An alternative is to use an Ohmic resistor R >> h/e 2 104f2 in series with a small tunnel junction [1, 2].
The system dynamics is presented by the phase dia- gram shown in Fig. 2c; in this diagram, each thin hor- izontal line corresponds to a certain number n of electrons trapped in the floating gate.The writing threshold V for the effective voltage Ve/= Cg(Vw Vb)/C 2 may be reached by the application of positive voltage V D to the word line and similar negative volt- FIGURE 2 Hybrid SET/FET memory: (a) structure, (b) possible threshold elements, and (c) memory cell dynamics shown schematically on its phase diagram age to both bit lines (C: is the total capacitance of the floating gate).Before readout, the cell is precondi- tioned by the application of a voltage V D to the corre- sponding bit lines (this operation increases parameter margins substantially).Finally, write 0/read operation is achieved by the application of positive V/ V D and negative V w -V D. The charge of the floating gate changes by AQ eAn -CV9, so that the effective charge Q0 of the SET island changes by AQ 0 eAnCg/C> e.Because the drain-source voltage 2Vr.
e/C is applied to the transistor simultaneously, its cur- rent performs several oscillations (Fig. lb) during the last process.These oscillations are picked up by a FET sense amplifier (Fig. 2a), which may serve simultaneously a block of N >> SET cells connected in parallel (the use of SETs as primary sensors allows the ultrahigh density while FETs provide the voltage amplification).After rectification, this waveform is sent to the output, signaling that the selected cell had the state before the write/read operation; if the state was 0, than An 0, and no output signal is formed.
Parameter estimates show that the density of 1011 bits/cm2and the room-temperature operation can be achieved using 10 nm 10 nm highly doped Si islands as the floating gates and 4 nm 4 nm islands as the middle electrodes of SETs. 3 ns mostly by charge injection to/ extraction from the floating gate through a 5-nm graded tunnel barrier with the maximum height of 3.5   eV; processes of charging the SET-FET interconnects (-0.1 ns) and of FET output lines (--1 ns) are consid- erably faster.The calculation of the intrinsic noise of the SET within the 300 MHz bandwidth shows that even if N 100 SETs are connected in parallel, the signal-to-noise ratio (--10) is still acceptable for a reliable read-out.
Another example in which the Q0-independent operation of the SET could be used, is the data read- out from a superdense (up to 1012 bits/cm2) electro- static storage disk (Fig. 3).Binary data may be written as few-electron charges into the ultrafine con- ducting grains (-lnm) separated from conducting substrate by a 5-nm-thick graded barrier, using the voltage pulse applied to a head (tip) moving close to the surface.Readout of the data may be performed with the same tip carrying the SET/FET transistor pair.

IV. CONCLUSION
We believe that the new Q0-independent principle of operation of single-electron devices suggested above, and the recent demonstration of silicon-based singleelectron transistors with e/C O.leV by several groups, may lead to implementation of the first room- temperature single-electron devices in the nearest future.
The work was supported in part by AFOSR and ONR/ARPA.