Two-dimensional Carrier Transport in Si MOSFETs

The importance of 2-dimensional (2D) features of carriers in Si MOSFETs on the device performance is re-examined experimentally and theoretically from the viewpoint of low-field mobility, velocity in high tangential fields and the inversion-layer capacitance. It is confirmed that low-field mobility and inversion-layer capacitance can be understood well in terms of the 2D subbands and the 2D carrier transport. In order to obtain fully-quantitative understanding of low-field mobility, however, it is still necessary to more accurately determine the amount of the scattering parameters in the inversion layer. On the other hand, saturation velocity is considered to be less influenced by the 2D quantization, while it is found experimentally that saturation velocity is slightly dependent on surface carrier concentration.


INTRODUCTION
It is well recognized that 2-dimensional (2D) features of carriers significantly affect the carrier transport in the inversion layer of Si, which determines the drain current of MOSFETs.The influence of the 2D quantization on the I-V characteristics of MOSFETs appears typically in the following ways.(1) Mobility is modulated through the change of the scattering probability due to the differences in the density-of-states, the form factor of the envelope function of 2D carriers and the scattering parameters.(2) Gate capacitance is decreased by the inversion-layer capacitance, which is determined by the finite thickness of the envelope function.(3) The threshold voltage of MOSFETs is increased by the existence of the subband energy.The influences of (1) and (3) are pronounced more with an increase in the substrate impurity concentration of MOSFETs and the influence of(2) is pronounced more with an decrease in the gate oxide thickness.Thus, the accurate tion, the analysis based on the self-consistent subband calculations is performed to explain the experimental results.The present understanding and the questions still unsolved are presented with comparing the self-consistent subband calculations.
Moreover, based on the knowledge of the 2D carrier transport in the inversion layer of Si, a subband engineering scenario to obtain the higher performance of $i MOSFETs is introduced.Electrons in the 2-fold valleys have higher mobility due to smaller conductivity mass and thinner inversion-layer thickness due to higher effective mass perpendicular to the Si/SiO2 interface than those in the 4-fold valleys.As a result, the electrical properties of inversion-layer electrons on (100) need to be understood as the weighed combination over these two electronic systems.structure for inversion-layer electrons on a (100) surface, on which MOSFETs are com- monly fabricated.Electrons confined near Si/SiO2 interface by normal electric field are quantized in the direction perpendicular to the interface and grouped into electronic subbands as 2D Electron Gas (2DEG).A characteristic point of the sub- band structure on (100) is that electrons in the inversion layer are classified into two electronic systems, the 2-fold degenerate valleys and the 4- fold degenerate valleys, as shown in Figure 1.

Low Field Mobility
Low field mobility in Si MOSFETs has so far been studied most extensively as the 2-dimensional carrier transport from both the theoretical and the experimental viewpoints.Recently, the inver- sion-layer mobility has come to be explained in terms of the scattering theory for the 2D carrier gas [2-6], even at room temperature.Figure 2 shows the experimental relationship between electron mobility on (100) and the normal effective field, Eeer, as a parameter of the substrate impurity concentration, Nj'.Eer is defined by q(Nar, + rlNs)/ esi), where Na is the surface concentration of the space charge in the depletion region, Ns is the surface carrier concentration and esi is the permittivity of Si.One evidence of the 2D quantiza- tion effects on the inversion-layer mobility appears as its Eefr dependence, which is the origin of the "universal curve".The universality ofthe inversion- layer mobility for Eefr, typically seen in Figure 2, has been verified experimentally over a wide range ofthe substrate impurity concentration for n-and p- MOSFETs [7][8][9][10][11] fabricated on several surface orientations [12].The Eefr dependence in low and moderate Eefr region, which is roughly proportional to E -'3 is thought to be attributable to phonon eft scattering for 2DEG, while the stronger Eefr dependence in higher Eefr region is influenced by surface roughness scattering.The mobility limited by intravalley acoustic phonon scattering for 2DEG is represented under the approximation ofthe single subband occupation [12,13]   Ndpl + -Ns 'eff (1)   NA Ee
FF@TI Fi /cm FIGURE 2 Relationship between inversion-layer electron mobility on (100) and the effective normal field, Eefr, as a parameter of the substrate impurity concentration.Eefr is defined by q(Ndpl -I-Ns/2)/esi (/= 1/2), where Ndpl is the surface concentration of the space charges and Ns is the surface carrier concentration.
mc is conductivity mass, md is density-of-states mass, nv is the valley degeneracy, Dac is the deformation potential of acoustic phonon, Sl is sound velocity.This Eefr dependence originates in the fact that the mobility is in proportion to the inversion-layer thickness, which is proportional to -1/3 under of 11/32.Since the inverse of the E eft inversion-layer thickness determines the energy band width of acoustic phonon that can couple with 2DEG, the thinner inversion layer leads to the higher scattering rate with acoustic phonon.
In order to more quantitatively describe mobility at room temperature, however, it is necessary to take the contributions of all the subbands and the interactions with intra-and intervalley phonons into consideration.At present, the amount of the phonon-limited mobility and its Efr dependence seems not to have been perfectly represented by the theoretical calculations [3,4,6].Figures 3 and 4 show the Eefr dependence and the temperature dependence of the experimental and the calculated phonon-limited electron mobility, respectively.The  Three parameters sets of intervalley scattering, set A, B and C, which are listed in Table I, are compared with the experimental results, which are shown as closed circles.
mobility calculation was carried out under the relaxation time approximation, based on the results of the self-consistent subband calculations [14] including 20 subbands.Three different parameter sets of intervalley phonon scattering, which are listed in Table I, are used in the calculations.It is found that the amount of the mobility calculated under the bulk phonon scattering parameters (parameter set .4 [15] and B [16]) is higher than that of the experimental one and the calculated tem- perature dependence is weaker than the experimen- tal one.
One possible origin of this discrepancy might be the difference in the scattering parameters in the inversion layer from those in bulk, which might be partly due to the difference of phonons relevant to intervalley scattering between 3DEG and 2DEG, coming from the selection rule in the wave-vector conservation.As one example of the different scattering parameters, a parameter set including larger deformation potential of intervalley f- phonon scattering (parameter set C) was used for the mobility calculation.The results are also shown in Figures 3 and 4. It is found that the higher coupling with intervalley phonons than in bulk can provide better agreement with the experimental results for both the magnitude of mobility and its temperature dependence.Further- more, as described later, the analysis of the mobility enhancement in strained Si MOSFETs also suggests the higher coupling between 2DEG and intervalley phonons.The mobility enhance- ment factor, the ratio of the mobility in strained Si MOSFETs to that in conventional Si MOSFETs, is also explained well by assuming the higher coupling with intervalley phonons (see Fig. 8).In order to more quantitatively obtain the values of the scattering parameters in the inversion layer, other experimental evidences through the direct evaluation of the scattering parameters are re- quired.On the other hand, even if the parameter set C is used, the calculated Eefr dependence is still TABLE Parameters for intervalley phonon scattering models.Ek and D k are the values of phonon energy and deformation potential, respectively.The parameters of models A and B were taken from [15] and [16] weaker than the experimental one.Further refine- ments on the phonon scattering model including the effect of the anisotropic deformation potential [4,17,18] are also expected to provide better agreement.
Another unclear point regarding the universal mobility curve is the origin of in Eer.It has already been reported that the value of r/is 1/2 for electrons on (100) [7][8][9]11] and 1/3 for holes on (100) 10, 11] at room temperature.Furthermore, it has also been found [12] that the value of r/is 1/3 for electrons on (110) and (111), suggesting that the subband structure can affect the value of r/ significantly.Although, according to (1), r/ is roughly 1/3, the only one subband is assumed for this equation.Thus, the detailed analysis of including all the subbands and the contributions of intra-and inter-valley scattering [19] are required to clarify the origin.

I" I"
Ns [cm-] 1.0 X 10 TANGENTIAL FIELD kV/cm FIGURE 5 Experimental results of the electron velocity- electric field curves in the inversion layer at room temperature as a function of N..The direction of the electric field is parallel to (110) axis.The inset figure shows the schematic cross section of resistive gate MOSFETs to evaluate carrier velocity in the inversion layer.In order to realize the uniform Ns along the channel, the voltage of Vgl + Va is applied to the terminal Vg2.

Saturation Velocity
Saturation velocity, Vsat, in the inversion layer is a quite important physical quantity in determining the drain current in ultra-short channel MOS-FETs.It seems, however, that the magnitude of Vsat in the inversion layer and the dependences on the physical parameters such as Eefr, Ns and T have not been fully established yet, partly because the large variation is seen in the measured values among the references [20][21][22].While several data have suggested that Vsa in the inversion layer is lower than that in bulk, it has not been clarified whether the 2D quantization at the Si/SiO2 inter- face has any influence on Vsat in the inversion layer.Thus, the relationship between the carrier velocity in the inversion layer and the tangential electric field has been evaluated, using MOSFETs with the resistive gate [20], in order to study the effect of the 2D quantization on Vsat. Figure 5 shows the experimental v-E curves as a parameter of The schematic cross section of the device structure is shown as the inset of Figure 5.It is observed that Vsat is dependent on Ns and decreases from the value in bulk Si, 107 cm/s, with increasing Ns, though the saturation of v is not obtained at Ns of x 1012 cm-2.
One of the most important points in experimen- tally evaluating Vst in the inversion layer is to realize the uniform distribution of Ns and the electric field along the channel of MOSFETs.Note that the velocity determined from the drain current in conventional MOSFETs is inaccurate because of the non-uniformity of Ns along the channel, unless MOSFETs with sufficiently thick gate oxides or SOI MOSFETs with sufficiently thick buried oxides are used [22].The uniformity of Ns along the channel in the high-resistive gate MOSFETs shown in Figure 5 has been examined [23], using device simulations.As a consequence, it was found that, although a distribution of Ns along the channel is observed, the Ns dependence of vst in Figure 5 cannot be explained only by this non-uniformity of Ns, but this Ns dependence is provided by some feature inherent to carriers in the channel of MOSFETs.
In order to examinewhether the lowering of Vsat with an increase in N is attributable or not to the 2-dimensional properties of ca;rriers, the substrate S. TAKAGI bias dependence of the velocity was measured.It should be noted that the Ns dependence of Vsat in Figure 5 can include both effects of the normal electric field and the carrier concentration, because Vg was simply changed to control Ns.The application of both Vg and Vsub allows to control Ns and Ee separately.If the 2D quantization plays an important role in the lowering of Vsat, Eer is expected to determine Vsat in the inversion layer.
Figure 6 shows the v-E curves in the inversion layer with and without the substrate bias.The gate voltage in the curve B was adjusted so as to make Ee in the curve B identical to that in the curve C, where the substrate bias of-6 V was applied.On the other hand, the curve A and the curve C have the same Ns.It is found in Figure 6 that the velocity in the curve A is almost the same as in the curve C and, thus, the velocity is determined not by Ee but by Ns itself.This fact means that the lowering of Vsat with an increase in Ns might be attributable not to the 2-dimensional properties of carriers, but to an effect inherent to Ns or carrier concentration itself like carrier-carrier scattering.
One possible mechanism responsible for the Ns dependence of Vsat might be plasmon scattering [24].If plasmon decays into electrons through the Vsub.While the value of Ns is in Curve C is the same as in Curve A, the values of Eefr in Curve C is the same as in Curve B.
emission of phonons, this process could become the energy dissipation mechanism of hot carriers under the high electric field.Note that the plasmon energy with the carrier concentration of 51018 cm-3, which is typically seen in the inversion layer, is 40 meV, which is almost the same as the energies of intervalley phonons seen in Table I.As the carrier concentration increases, the plasmon en- ergy increases and the possibility of the energy loss due to the phonon emission might also increase.Further experimental evidence and theoretical verification on the relevance of plasmon with the energy loss of hot carriers in the inversion layer are strongly required.

INVERSION-LAYER CAPACITANCE
One of the most crucial limitations in the miniaturization of MOSFETs is that the gate capacitance cannot be sufficiently increased by thinning the gate oxide, because of the existence of the inversion-layer capacitance, Cinv [25-27].
Since the total gate capacitance, Ctot, is described by Cox/(1 +Cox/Cinv), the influence of Cinv be- comes more serious with reducing the oxide thickness.Thus, it is quite important to clarify the origin of Cinv and to quantitatively evaluate Cinv. Figure 7 shows the schematic diagram of Cinv as a function of N under the simple analytical models [27], suggesting that the effect of the 2D quantization on Cinv is dominant in higher Ns region.The reason why the 2D quantization is important on Cinv is that the finite inversion-layer thickness, which effectively works as the series capacitance to the oxide capacitance, is much thicker in 2D carrier gas than in bulk carriers.In the model of the single subband occupation, Cinv due to the finite inversion-layer thickness under the 2D quantization can be simply described by Here, Zinv is the average thickness of 2DEG, h is the Plank constant and m3 is the effective mass of Si perpendicular to the Si/SiO2 interface.Accord- ing to this formulation, Cinv should have the dependence on m 3. Figure 8 shows the experi- mental Cinv at room temperature as a function of Ns for (100), ( 110) and (111) surfaces, which have the different values of m3.It is found that the measured values of Cinv become smaller in the order of (100), ( 110) and (111).Actually, it is confirmed that the surface orientation dependence of Cinv is explained quantitatively by the m13/3 dependence.This result is the direct experimental evidence for the fact that Cinv at room temperature is determined by the quantum mechanical inver- sion-layer thickness, because the surface orienta- tion does not make any difference for 3D carrier gas.This result also means that a larger value of m3 leads to the suppression of the degradation of the gate capacitance due to Cinv.
Figure 9 shows the experimental and the calculated Cinv for inversion-layer electrons on (100) at room temperature.The calculated Cinv was determined directly from ds/d Vg through the self-consistent subband calculations without using any definition of the inversion-layer thickness [27].
It is confirmed that Cinv is accurately represented by the calculation, meaning that Cinv is quantita- tively understood even at room temperature in terms of the 2D subband. -7 .0 i 10 ta Ns cm -2 FIGURE 8 Experimental Cinv Ns curves for electrons in the inversion layer on (100), ( 110) and (111) surfaces at 298 K.The value of effective mass perpendicular to the interface, m3, is described for each surface orientation.

SUBBAND ENGINEERING FOR HIGHER PERFORMANCE MOSFETs
In order to obtain the higher current drive in MOSFETs, higher mobility and higher inversion- layer capacitance are required.In terms of the effective mass, these requirements mean lighter effective mass parallel to Si/SiO2 interface, which increases mobility, and heavier effective mass perpendicular to the interface, which maximizes Cinv.From this viewpoint, the 2-fold valleys on a (100) surface are an optimum electronic system in the inversion layer of Si, as summarized in Figure 1.In conventional MOSFETs, however, the energy difference in the lowest subband energy of the 2-fold valleys, E0, and that of the 4-fold valleys, E, is small.As a result, the occupancy of the 2-fold valleys in conventional MOSFETs is not sufficiently large at room temperature.Therefore, an effective strategy to obtain the higher current drive is to increase the energy difference in the lowest subband, E-E0.There are two possible ways to realize such a modulation in the subband structures.One way is to apply the tensile strain in Si substrate.It is known that tensile biaxial strain parallel to the interface causes the band splitting between the 2-fold valleys and the 4-fold valleys.This structure corresponds to strained Si MOS-FETs.The other way is to utilize the size effect due to built-in confinement potential such as the band discontinuity at hetero-interfaces.For example, when SOI films in SOI MOSFETs is thinner than the inversion layer in bulk MOSFETs, the sub- band structures can be significantly modified and the resultant occupancy of the 2-fold valleys can increase by the size effect of the SOI film itself.The effectiveness of this subband engineering is exam- ined through the subband and mobility calcula- tions.

Strained Si MOSFETs
It is known that tensile strain in Si, which is typically seen in Si grown on relaxed SiGe, causes the band splitting between the 2-and the 4-fold valleys, which leads to the increase in E0 E and the resulting higher occupation in the 2-fold valleys.As shown in Figure 10, it has been confirmed experimentally [28], [29] that the inver- sion-layer mobility in strained Si MOSFETs at room temperature increases up to around twice as high as in conventional MOSFETs with an increase in tensile strain, which is controlled by the Ge content of SiGe substrates.The calculated phonon-limited mobility for 2DEG in strained Si is also shown in Figure 10.Good agreement with the experimental mobility ratio is obtained by using the higher coupling constants with inter- valley phonons (parameter set C).This is another evidence for the higher coupling of intervalley phonons with 2DEG in the inversion layer than with bulk electrons, as described in 3.1.The calculated results have also revealed that, in addition to the preferential occupation of the 2- fold valleys, the suppression of intervalley scatter- 2.0 $ 1.8 "6 Ns lx101 cm.Substrate Ge Content % F]GURE ]0 obi]ity cbaccmcnt factor (thc ratio of tbc mobility in strained Si MOSFETs to that i ustaid (comioa]) substrat o which the straid layer is foxed.The amount of sttai i strained Si cxpcdmcta] results wr takc from [28].Th dottcd, dashed ad solid lis rcprcst th ca]cu]atd results using the intcrva]]ey pboo scattering parameter sets , B and C.
ing due to the band splitting leads to the mobility enhancement in strained Si MOSFETs [6,30].It has also been found that Cinv in the inversion layer of Si slightly increases with tensile strain.

Ultra-Thin Film SO1 MOSFETs
In order to examine the possibility of the modula- tion of the subband energy and the resultant occupancy of the 2-fold valleys in SOI MOSFETs with SOI films thinner than the inversion layer in bulk MOSFETs, the calculations of the subband structures and the phonon-limited mobility were performed [31].Figure 11 shows the calculated phonon-limited mobility as a function of the SOI thickness, Tsoi.With decreasing Tso the mobility decreases slightly at first, and increases with decreasing Tsoi from 5 nm to 3 nm.With decreasing Tsoi from 3 nm, the mobility decreases again.It is found, moreover, that the mobility with the SOI thickness of around 3 nm can be higher than that in conventional MOSFETs.This en- hancement is attributable to the fact that, with decreasing the SO1 thickness, the electron occupation of the 2-fold valleys becomes higher, because of the increase in E. The calculated occupancy of the 2-fold and the 4-fold valleys is shown as a function of Tsoi in Figure 12.It is confirmed that the occupancy of the 2-fold valleys increases with a decrease in TsoI and becomes almost 100% around 3 nm of Tsoi.The reason why E increases more rapidly than E0 with a decrease in Tsoi is that the inversion layer thickness of the 4-fold valleys is thicker than that of the 2-fold valleys and, thus, E is more sensitive to the SOI physical thickness than E0.
It has been also confirmed that Cinv in SOI MOSFETs with Tsoi thinner than 5 nm is significantly improved, because the inversion-layer thickness is determined by the SOI thickness itself [32].These results demonstrate that, if the SOI MOSFETs that have the perfectly fiat interfaces with the gate oxide and buried oxide can be realized, the performance of SOI MOSFETs with Tsoi of 3 nm to 5 nm can be much higher than that of bulk MOSFETs.S. TAKAGI 6. CONCLUSION The importance of the 2D features of the inversion layer electrons on the current drive of MOSFETs at room temperature has been re-examined through the systematic experiments and the self-consistent subband calculations.Inversion-layer mobility and inversion-layer capacitance can be understood well from the viewpoint of the 2D subband and the 2D carrier transport.However, further refinements in the scattering parameters and models are still needed to have fully-quantitative description of inversion-layer mobility.On the other hand, satura- tion velocity in the inversion layer is considered to be much less affected by the 2D features of carriers.
Based on the knowledge of the Si subband structures, an effective strategy for higher MOS-FET performance, the enhancement of the occu- pancy of the 2-fold valleys on a (100) surface, has been presented.Higher mobility of strained Si MOSFETs and SOI MOSFETs with ultra-thin SOI films, both of which are the typical examples of this subband engineering, has been confirmed by the theoretical calculations.
FIGURESchematic diagram of the subband structures for electrons on a (100) surface and the characteristics of the 2-fold and the 4-fold valleys. by

FIGURE 3
FIGURE3 Calculated phonon-limited mobility in the inver- sion layer at room temperature as a function of Efr.Three parameters sets of intervalley scattering, set A, B and C, which are listed in TableI, are compared with the experimental results, which.areshown as closed circles..

FIGURE 4
FIGURE 4 Calculated phonon-limited mobility in the inver- sion layer at Ns of x 10 r2 cm -2 as a function of temperature.

FIGURE 6
FIGURE 6 Electron velocity-electric field curves with (Curve C) and without (Curve A and B) the substrate bias,

FIGURE 9
FIGURE 9 Comparison in Cinv-Ns curves on (100) surface at 298 K between the self-consistent calculation and the experi- mental results.The open circles and the closes circles represent the results before and after the influence of the depletion layer in the poly-Si gate was subtracted from the experimental data.

FIGURE 11
FIGURE 11 Calculated phonon-limited mobility in SOI 12MOSFETs as a function of SOI thickness at Ns of 3xl0 cm- 12 and 9x 10 cm-.The substrate impurity concentration and the 15 buried oxide thickness are 5x 10 cmand 100 nm, respec- tively.

FIGURE 12
FIGURE 12  Calculated electron occupancy of the 2-fold and the 4-fold valleys as a function of the SOI thickness at Ns of 3x10 -12 cm-2.
Schematic diagram of the physical origins of Cin and the Ns dependence of Cin under the simple analytical [27]ls[27].