Monte Carlo Calibrated Drift-Diffusion Simulation of Short Channel HFETs

In this paper we present a methodology to use drift diffusion (DD) simulations in the design of short channel heterojunction FETs (HFETs) with well pronounced velocity overshoot. In the DD simulations the velocity overshoot in the channel is emulated by forcing the saturation velocity in the field dependent mobility model to values corresponding to the average velocity in the channel obtained from Monte Carlo (MC) simulation. To illustrate our approach we compare enhanced DD and MC simulation results for a pseudomorphic HEMTs with 0.12 lam channel length, which are in good agreement. The usefulness of the described methodology is illustrated in a simulation example of self aligned gamma gate pseudomorphic HEMTs. The effect of the gamma gate shape and the self aligned contacts on the overall device performance has been investigated.


INTRODUCTION
Commercial device simulators like MEDICI [1] and BLAZE [2] are flexible, fast and work in a user friendly environment.Employing finite ele- ment approach they can describe accurately the complex geometry of modern short recess gate heterojunction FETs (HFETs).Interface charge, surface states, and deep levels can be eventually included in the simulations and the self heating can be treated through coupling to the heat flow equation.The transient algorithms are stable and allow for large time steps.Frequency domain analysis is readily available.External circuit elements like contact and gate resistances, pad inductances and capacitances can be included in the simulations and in the rf analyses.Unfortu- nately the drift-diffusion (DD) approach, which is at the heart of such simulators, cannot predict the velocity overshoot responsible for the high performance of many short channel HEFTs [3].The hydrodynamic (HD) options offered as extensions to the DD engines of the above simulators deal with the overshoot but slow down the simulations and often have convergence and parameter in- dentificatio problems.The ensemble Monte Carlo (MC) method, usually implemented in in- house software [4], is still computationally expen- sive and cannot match all the features of the DD commercial simulators, particularly their speed.
In this paper we describe a methodology for using MC calibrated DD simulation with en- hanced channel velocity in the design and optimisation of short channel HFETs including HEMTs and strained Si channel SiGe MODFETs.The DD simulations are calibrated with respect to our finite element Monte Carlo simulator H2F [5].The usefulness of this approach is illustrated in simulation examples of self aligned gamma gate pseudomorphic HEMTs.

Figure
illustrates the velocity along the channel of a 0.12 t gate length pseudomorphic HEMT with 22 nm gate-to-channel separation, 50 nm recess offset and delta doping in the supply layer.The device is described in more details elsewhere [7].The velocity profile obtained from DD MEDICI simulation with vs forced to 2.8107cm/s, #0 5000 cmZv-ls-land b=2 matches well with the MC velocity profile in the source region and in the channel.In the drain region, where most of the particle in the MC simulation are in the L-valley, the DD simulation overestimates the velocity and hence underesti- mates the drain resistance.This however does not affect seriously the simulated rf performance since the drain resistance has usually a weak influence on the measured and extracted s-parameters.

EMULATION OF THE OVERSHOOT
The enhanced DD approach is based on the observation from MC simulations that in many short channel (0.1-0.2 tm gate) HFETs the velocity overshoot extends along the whole high field channel region.The average velocity profile in the channel obtained from MC simulation can be emulated by increasing the saturation velocity vs in a simple, three parameter, silicon-type field dependent mobility model [6] with velocity v is given by #0E \vl where E is the electric field, la0 is the low field mobility and b is a model parameter.The calibration is done by adjusting the three para- metes #0, v and b in order to match the MC velocity profile in the source and in the channel region for a bias point in the middle of the uselful part of the device characteristics.In most of the cases this is enough to achieve satisfactory agree- ment between the MC and the DD simulation results over the whole range of applied voltages of interest.

COMPARISON OF DD AND MC DC AND RF RESULTS
In order to justify the use of the enhanced DD approach in practical short channel HFET device simulation and design we compere the dc and the rf results obtained from both DD and MC simulations.The comparison is based on the same 8E+07 6E+07-4E+07-2E+07 0E+00.
Average velocity in the channel of a 0.12 tm pHEMT obtained from DD and MC simulation at Va 0 V and VD 1.5 V.
Exactly the same simulation geometry is used in both the DD MEDICI's and the MC H2F's simulations.The source and drain contact resis- tances which cannot be directly included in the MC simulation are also excluded from the DD simulations.The velocity profile is calibrated at one dc bias point corresponding to V=0V and Vz 1.5V.The dc ouput characteristics are compared in Figure 2 and are in remarkably good agreement in both the low and in the high drain volatge regions.This is partially due to the fact that the deconfinement which cannot be properly treated in the DD simulation does not affect seriously the operation of the simulated pseudomorphic HEMTs with relatively deep (In0.3_Ga0.vAs) channels.
The comparison of the rf results obtained form DD and MC simulation is based on time domain transient technique which is the only available choice in the MC case [8].Complex two port y- parameters are extracted by Fourier transforming the gate and drain current transients in response to small changes in the gate and drain voltages.The frequency dependence of the real and the imagin- ary parts of yl and y12 is plotted in Figure 3.The y-parameters extracted from the DD and MC transient simulations are in good agreement.This  from DD and MC simulation of a 0.12 gm pHEMT at Va 0.2 V and V/ 1.5 V.The channel width is 100 gm.
agreement holds also for the small signal circuit elements and the cut-off frequency fr extracted from the y-parameters and for the maximum frequency of oscillations fmax extracted after transforming the y-parameters into s-parameters.

SELF ALIGNED GAMMA GATE EXAMPLE
Calibrated DD simulations can be used confi- dently to investigate device geometry effects which do not affect strongly the lateral field profile in the channel but are important for the rf device performance including the gate and contact shapes, self-alignment, cap layer modification, recess design etc.When the lateral field profile is altered, for example as a result of channel length scaling, the DD simulations have to be recali- brated with respect to a new MC calculation.We illustrate the described DD approach in the simulation of self aligned gamma gate pHEMTs.
The vertical layer structure of these devices is the same as the structure described in Section 2. The profile of the gamma gate and the corresponding solution domain are outlined in Figure 4.In the DD simulation we investigate the effect of the gate overlap dc-r on the drain side of the channel on fr and frnax.The results are presented in Figure 5. design itself is a trade off between the reduced gate resistance and the increased gate-to-drain parasitic capacitance.The velocity overshoot in the channel of modern short gate length HFETs can be satisfactory emulated in DD simulations by increasing the saturation velocity in a simple silicon type field dependent mobility model.Usuallly calibration of the DD simulations to one properly selected bias point of the corresponding MC simulations leads to good agreement in the DD and MC dc and rf characteristics over a wide range of applied voltages.Calibrated DD simulations can be used to speed up the design of modern short channel HFETs where geometry related parasitic effects complete with the enhanced channel transport in determining the overall device performance.In the self aligned technology a trade-off between the reduced series resistances and the increased gate-to-contacts parasitic capacitances determines the over all device performance.The gamma gate

FIGURE 2
FIGURE 2Comparison between DD and MC simulated output characteristics of a 0.12 gm pHEMT.

FIGURE 3
FIGURE 3 Comparison between Y parameters extracted

FIGURE 5
FIGURE 5 Dependence offT, and fmax on the gate overlap d,.__r for the self aligned gamma gate pHEMT illustrated in

Figure 4
Figure 4 with channel width is 100 gm, contact resistance [ and gate resistance 5 f.DD simulations.