Cellular Automata Studies of Vertical Silicon Devices

We present systematic theoretical Cellular Automata (CA) studies of a novel nanometer 
scale Si device, namely vertically grown Metal Oxide Field Effect Transistors 
(MOSFET) with channel lengths between 65 and 120 nm. The CA simulations predict 
drain characteristics and output conductance as a function of gate length. The excellent 
agreement with available experimental data indicates a high quality oxide/semiconductor 
interface. Impact ionization is shown to be of minor importance. For 
inhomogeneous p-doping profiles along the channel, significantly improved drain 
current saturation is predicted.


INTRODUCTION
As a numerically very efficient discrete variant of the Monte Carlo (MC) technique [1], the CA [2] method significantly reduces the gap in computa- tional speed between simulation techniques based on solving the full Boltzmann equation, and moment-based approaches such as the hydrody- namic method.The CA method is therefore particularly suited to simulate highly nonlinear charge transport, typical for the ultra-short devices described in this paper.

VERTICAL MOSFET
Molecular Beam Epitaxy (MBE) and Chemical Vapor Deposition (CVD) allow the realization of vertical devices with characteristic channel lengths well below 0.1 tm.Recently, CVD epitaxy was utilized to grow vertical MOSFET's with ultra short channels (see [3,4]).The epitaxially grown layer structures are selectively etched to a depth of 0.8 tm and thermally oxidized to grow the SiO2 gate dielectric with a thickness of 5 nm.The quality of the oxide is comparable to planar structures.Figure shows the cross section of such a vertical MOS [4].The simulated geometry is shown on the left side of the figure, and corres- ponds to one half of the real device.Devices with different doping levels and channel length were fabricated.The doping concentra- tion in the source and drain n + regions are in the range 1018 cm -3 .'-2x 1019 cm-3, while the p-buffer layer contains an acceptor concentration of 2 x 1018 cm-3.These devices were grown with an effective channel length varying from 65 to 170 nm.
To investigate the influence of nonlinear trans- port on the electrical characteristics of such ultra short devices, we performed systematic calcula- tions for all the realized structures and compare our results to experimental data.We further explore the influence of inhomogeneous p-doping along the channel in improving the drain current saturation behavior.As a critical test for the nominal geometry settings like oxide thickness and p-doping level, we have compared the experimental and calculated sub- threshold behavior of the devices described above.
Excellent agreement was obtained for several devices with different geometries and doping concentrations, which indicates that the nominal and technologically realized values of the geometry agree well with each other.This is exemplified in Figure 2 for the 65 nm CVD vertical MOSFET structure.There, the applied drain voltage is 0.5 V.
Based on these geometries, we investigated the drain current saturation behavior of the vertical MOSFET for different channel lengths.Figure 3 shows the output current versus drain voltage for three different channel lengths of 170 nm, 120 nm and 65 nm, respectively.The bias of the gate was fixed to the value of 2V.Clear drain current saturation behavior is found even for the ultra- short, 65 nm device.The increasing output current Oxide 5nm N FIGURE Layout of the vertical CVD-EPI MOS.The growth direction is shown, while the equivalent simulated region, is on the right side.FIGURE 2 Sub-threshold output current of the simulated device versus gate voltage when a low (VI 0.5 V) drain bias is applied.

Cellular Automaton
Experiment L 65 nm L--120 nm L= 170nm Vdrain (V) and output conductance with decreasing channel length reflect a strong barrier reduction at the source junction.Nevertheless, even for high bias condition, no parasitic charge transport occurs in the bulk parallel to the conduction channel.The increase of drain current and output conductance due to the electrostatic effects mentioned above are further enhanced by velocity overshoot in the shorter channels.This velocity overshoot is driven by a high, inhomogeneous electric field along the channel.For the 65 nm n-p-n + structure biased at VD VG 2 V, we find a peak value of 800 kV/cm at the n +p drain junction.
For this bias condition, the average electron velocity in the conduction channel of the 65 nm device is shown in Figure 4. Pronounced velocity overshoot is evident all along the conduction channel, the maximum velocity being reached at the drain end of the p-buffer, where it peaks to a value of three times the saturation velocity in homogeneous Si.The overall agreement for the complete current- voltage characteristics between the CA results and experimental data is exemplified for the 70 nm device in Figure 5.For this device, simulations were performed up to a bias value of VD 2.5 V, to investigate the occurrence of impact ionization at higher bias.Up to the highest bias point shown, negligible contributions due to impact ionization were found.However, this process becomes im- portant at higher drain bias.Analogous results were found for the 65 nm device.

Bulk Effects
The potential barriers due to the np (source) and pn (drain) junctions prevent a parasitic bulk current from flowing parallel to the channel inversion layer.At the same time, the electric field due to these junctions can reach high values, giving rise to impact ionization or even field breakdown.Optimization of such devices must account for the electrostatic behavior of the bulk region in order to improve saturation and avoid impact ionization at a given operating bias.Figure 6 (left) shows the concentration of carriers in the bulk 65 nm n+pn system when a bias of 2 V is applied between the n and n + regions corresponding to the source and drain of the device shown in Figure 1.The fact that the potential barrier due to the npn junction (Fig. 6) is still intact at this drain bias ensures that no parasitic bulk current is flowing.

Design Optimization
In order to improve the saturation behavior of the vertical MOSFET, an additional 20 nm p+-buffer was introduced in the central p-region.The chosen 0 0.1 0,2 0,3 0,4 0,5 0,6 position FIGURE 4 Average drift-velocity of electrons in the CVD- EPI MOSFET of Figure 1" a pronounced velocity overshoot is evident in the p-buffer.doping concentration in this p+-buffer is 3x1018 cm -3 The buffer was placed 10nm from the n-p source junction.The buffer extension and position were optimized to reduce the influence of the drain potential on the output current, thus improving the saturation behavior.Its separation from the n-p source junction keeps the value of the junction field low enough to avoid impact ioniza- tion.Additionally, punch-through action is reduced due to the higher doping, which is crucial for devices with shorter channels.The drain current reduction due to the presence of the buffer was compensated by reducing the oxide thickness to 4 nm.
Simulation results for the device with the p+buffer are compared in Figure 8 with measure- ments made on a transistor with a homogeneously doped channel.The saturation behavior is re- markably improved compared to the character- istics shwon in Figure 5, and the reduced oxide thickness completely compensates the current reduction due to the p+-buffer.excellent agreement with the experiments.The crucial role of the bulk parasitic conduction was stressed, and an optimized device design was proposed which improves the overall performance of the device.
The capability of the CA approach to accurately predict highly nonlinear transport behavior and the resulting electrical characteristics in real nanostructured semiconductor devices was de- monstrated.A novel family of vertical MOSFET's was investigated, giving results which are in

FIGURE 3
FIGURE 3 Computed (points) and experimental (full lines) current-voltage characteristics with decreasing channel length at VG 2 V gate bias.

FIGURE 5
FIGURE 5 Computed (points) and experimental (full lines) current-voltage characteristics of the 70 nm vertical MOS-FET.

FIGURE 6
FIGURE 6 Carrier concentration (left) and potential profile (right) in the bulk n-p-n structure present in the vertical 65 nm MOSFET.

FIGURE 8
FIGURE 8 Improved saturation behavior of the simulated MOSFET after adding an additional 20 nm p+ buffer.The simulation results (full lines) are compared with experimental data of Figure 5.