Placement with Incomplete Data *

ion 1. AddNetAbstraction(circuit Ci) { 2. Get net statistics discussed above. 3. Create unassigned terminal list 4. while/2 is not empty, do { 5. Create a net data structure. 6. Determine the number of terminals on this net using the appropriate statistics. 7. Randomly pick nn terminals from ;. 8. Assign these nn terminals to this net. 9. Delete these n terminals from/2. 10. } 11.} Intuitively, fusion makes much more sense than abstraction, since it appears thatfusion will generate a circuit more like the original one, circuit C, while abstraction will almost never look like C. Contrary to people’s intuition, experimental results show that abstraction offers much more accurate prediction than fusion does. In the next section, we will present this interesting experimental result, followed by an explanation. 5. EXPERIMENTAL RESULTS AND DISCUSSION In Section 4, we gave the pseudo-code for our approaches. These approaches were implemented using C + +. All experiments were run on a Sun Sparc-20 workstation. Three MCNC benchmark standard cell circuits were used for experiments. Table I shows some basic statistics for these three benchmark circuits. We delete all the I/O pads from all three of these circuits, allowing us to concentrate on the effects of incomplete data on core cells. As shown in Table I, circuit Nprimaryl is the MCNC benchmark circuit primary without I/O pads, and circuit Nprimary2 and Nstruct are MCNC benchmark primary2 and struct without I/O pads, respectively. We feed the reconstructed circuit to the high quality placement tool called NRG [12]. Since this is a statistical approach, we needed to run a good number of trials to get the data. Thus we run NRG using the fast mode. For each benchmark circuit C(3//,A/’), for a specified degree of incompleteness pc. We first delete Pc" 13/[] cells and the nets attached to them to form Ci. Then we run our two reconstruction procedures, fusion and abstraction, to get a "reconstructed" circuit C’ (fusion and abstraction were discussed in detail in Section 4). After that, we use the NRG placement tool to get the total wirelength of C and compare this value with the value of the original circuit C. Table II shows the basic statistics for the "reconstructed" circuit Nprimaryl using different degrees of incompleteness. The first row, 0% incompleteness, is the statistics for the original circuit Nprimary . Table III shows the total wirelength results achieved from the reconstructed circuit Nprimaryl For each degree of incompleteness, column "Ave WL" shows the average total wirelength over all trials; column "std. Dev." shows the standard deviation of all trials, and "% error" shows the percent error compare to the real value from the original complete circuit Nprimaryl.


INTRODUCTION
The placement problem is defined as problems given a set of cells and a netlist of connections, optimizing the placement to minimize area, wirelength, delay, etc.In this problem, 100% cells and netlist is known.
Numerous placement algorithms exist, such as force directed approach [1,7, 18, 6], simulated an- nealing [14,15], and partitioning-based placement algorithms [3,2,5,8].A constructive placement method that employs resistive networks as a work- ing domain was proposed in [4].Various optimiza- tion objectives have been used.In [17], a comparison between linear and quadratic cost functions was reported.The linear cost function used in the GordianL placement tool achieves results with up to 20% less area than the quadratic cost function of the original Gordian procedure.Therefore, in this paper, we will use the half-perimeter cost func- tion for area minimization.
The timing-driven placement problem has also been studied.The notion of zero-slack was intro- duced in [11].In [9] criticality was used as a guide to select cells from a cell library.For a history of the timing-driven placement problem, see [10,16,13].
In this paper we study the placement problem with incomplete data (PID).This problem is of fundamental importance since VLSI design is get- ting more and more complicated.Now a state- of-the-art VLSI design contains millions of gates, and this number keeps increasing according to Moore's law.Such a complicated design will typi- cally take 2 to 3 years to complete.In the first 2 years, a detailed netlist is not available.However, for area estimation and performance estimation, several placement runs are done with such incom- plete information.Traditional placement problems are based on a fully specified cell library and a complete netlist.Obviously, this cannot handle this problem.
Another source of incompleteness will come from re-use of instances from earlier generations.The hardware instances are modified to some ex- tent and more information may be added as the project moves forward.Thus even if we do have a complete cell library and netlist, this cell library and netlist will not be the same library and netlist as in the final version of the design.The designer will definitely want to know how much he or she can trust the placement result.If 5% of the cells in the library are changed later, it will not be good news to know the placement results will therefore change by 50%.In the re-configurable computing area, this problem is also practical.Sometimes we need to perform quick placement before all infor- mation is available from a compiler.PID is the problem of trying to place the final design while only a part of the netlist and a fraction of the cell library is known.PID is of fundamental importance.It is also a very challenging problem, as will be shown later.To the best of our knowledge, no research has been done on this problem.
In our experiments, we use MCNC benchmarks.We randomly delete p% of the nets and p% of the cells.We then try to re-construct the netlist us- ing different "patching-methods".We compare the wire-length of the original circuit against the wire- length of the "patched" circuit as a basis to judge the quality of the proposed patching-methods.Experiments on different values of p and p and dif- ferent benchmarks have been performed.
This paper is organized as follows: In Section 2 we introduce some terminology which we are going to use throughout the paper.In Section 3 we formally described the placement with incomplete- ness problem followed by a detailed summary of approaches and implementations in Section 4. In Section 5, experimental results will be shown and discussed, followed by conclusions in Section 6.

TERMINOLOGY
In this paper we assume that we are given a complete synchronous circuit denoted C(A//,A/'), which consists of a set of modules A//= {Mili and that the remaining sink terminals Sa:-{s0,a:} are module inputs.This assumption simplifies the capture of signal flow directions and is used in the construction of the timing model.Terminals are given a location on the surface of an IC by the placement process.This location is used by many of the physical design steps.The location of a termi- nal is represented by si,k (Xi, k; Yi, a:), thus Sk C 2, where R is the set of real numbers and si,a: is the ith terminal in net net Na:.The rectilinear distance between two terminals si,a:, Sj,m is [Ise,,S,mll-Ixi,a:-Xj,ml + lYe,a:-Yj,ml.Similarly, each module M contains a set of terminals S(Mj)= {s,li 0... IS (Mj)I}.Let the location on the plane of the module Mj be denoted by (xej, y,j).Then the loca- tion of a terminal s,a: E S (Mj) is a function of the module location.
For this work, we only consider standard cell layout style.We shall use the terms modules and cells interchangeably.Restriction on standard cells adds simplicity to our initial algorithms and im- plementation.The concepts developed here can be applied to other styles.However, we have not explored them yet.

PROBLEM FORMULATION
The general idea of the placement problem with incomplete data has been illustrated in Section 1.
We are going to further formalize the problem here in this section.
During a design process, what we have in hand is the incomplete netlist and library.The complete netlist and library in the future will never be known at this time.Suppose there is an algorithm which can predict the final placement result only using the known incomplete information about the circuit.The question then is how good this result is.Therefore it is very important to first establish a standard for evaluating any PID algorithm.
Obviously, the best way to do this is to start from a complete circuit.This circuit, including the complete netlist and the cell library, will be no doubt the only fair metric to measure how good any kind of PID algorithm is.A good algorithm will give a good prediction on area or performance using only part of the original circuit information.
Starting from this complete circuit C, we can easily build an incomplete circuit Ci simply by deleting or modifying cells and nets from the original circuit C.There are two numbers to quanti- tively measure the incompleteness, pc and Pn.We denote by Pc the percentage of cells we deleted or modified from C to get Ci.Similarly, Pn is the per- centage of nets we deleted or modified from C to get Ci.For example, a complete circuit C contains 100 cells and 100 nets.After modification, the in- complete circuit has only 90 cells and 95 nets which are still the same as in C. The other 10 cells and 5 nets are either deleted or modified.Then in this case, Pc 10% and pn 5%.Now we are ready to describe the placement with incompleteness problem formally: Given a complete circuit C(A4,A;), an incom- plete circuit Ci(A4i, A/'i) is formed by deleting a number of cells and nets from C(A//,A/').Two real numbers Pc and Pn satisfy the following conditions: 1. 0<pc < 1,0 <pn< 1.
2. ]A//f) ail (1 Pc)" 3. IA/" n./g'i[ (1 -Pn)" We are going to make predictions on issues like final chip area, power consumption, etc., of the circuit C(A//,A/') based only on the circuit Ci(Ji,Ji) and parameters Pc, P.These predic- tions will be compared to the actual value of the circuit C(A4, A/').
This above description concludes the formula- tion of the placement problem with incomplete data.There will be numerous ways to obtain such predictions for circuit C. In this paper, we are actually trying to "reconstruct" the circuit C from the incomplete circuit Ci.Specifically, we are going to find a set of modules Ja and a set of nets A/'a.We use Ja and A/'a, together with Ji and A/'i, to form a new circuit C'((ja I,.J .A/[i) (Ja I._J Jr'i)).Figure 2 shows an example of a complete circuit C with 8 cells and 10 nets.The incomplete circuit   C; can be obtained by deleting cells M4, M6 and all the nets attached to them. Figure 3 shows the result of Ci.In this case, Pc 25% and Pn 20% since only 2 nets are gone.We can add two new dummy cells, N1 and N2 and some dummy nets to get circuit C . Figure 4 shows a possible way to get C .O f course, most probably, C will not be exactly the same as the original circuit C. Our hope is that by using a "clever" way to get C , the placement result of C will be very close to the placement re- sult of C. Now the question is how can we get the sets .A/[ a and N'a.One approach is by randomly determin- ing all the details, such as the size of the new dum- my cells, the number of pins on the new dummy cells, etc. Obviously, this is not a good method since we have not made use of the known informa- tion.Since the missing part of the circuit will not be too large, we will expect the missing part to be "very much" like the rest of the circuit.
In the next section, we will study appropriate approaches to this problem.
Note that in this paper, we only try to make a prediction on the total net lengths, which is con- sistant with the final chip area."Half perimeter bounding box" is what we will use to measure the length of each net.

OUR APPROACH AND IMPLEMENTATION
As mentioned in the previous section, a totally random approach is not good.On the other hand, we should notice the following fact: FACT There are no algorithms which can always reconstruct a totally identical circuit as circuit C us- ing only the imcomplete circuit Ci.
Proof The proof is simple.Suppose Ci is the incomplete circuit with which we will start with.Then arbitrarily add two different sets of cells and nets to Ci.This will give us two different circuits C1 and C2, and they share the same incomplete cir- cuit Ci.After we run our "universal" algorithm on Ci, we get the reconstructed circuit C'.If then C' :/: C2, and vice versa.This means that this "universal" algorithm cannot get an identical cir- cuit for both C1 and C2 at the same time.Since both C1 and C2 are the correct results, the above fact is true.This fact suggests that the problem itself is very hard since we have no hope of getting a completely correct answer.Before we start thinking about the actual approach, let us first make some assump- tions about this problem.
First, the incompleteness measurement Pc and pn should not be too large.We cannot get any sort of prediction if we only know 5% of the netlist.We should know at least half of the original circuit, and it is very reasonable to assume that the missing part of the circuit is very much like the remaining part of it.That is, if we miss a very special part in this incomplete circuit, we should not expect to get a decent prediction, Foliowing this assumption, sets .A/[ a and ./V" a should be "similar" to sets Adi and Jfi in circuit Ci.The question is, what does "similar" mean here.Our interpretation for this is that they have similar statistics.For example, two module sets should have similar size distribution curves (to be discussed later).
There are a lot of possible statistics on which we can base our studies.Among these, we chose three of them to be the statistics for the module set.They are: 1.The size distribution of cells.
2. The number of terminals distribution on each cell.
3. The I/O type distribution of all terminals.
There is no question that the size of cells is the most important information in area estimation.Besides this, the number of terminals on each cell is also important since it determines the connec- tivity of each cell.The larger this number is, the larger the total final area will be.An appropriate I/O type distribution of terminals will assure a netlist similar to the original circuit.An I/O type .distributionmeans that we should know approxi- mately how many terminals we are going to add are inputs, how many are outputs and how many are bidirectional.Without this I/O type distribu- tion, any pair of terminals can be hooked up, leav- ing too much freedom to deal with.If we know this distribution, since an output terminal has to be hooked up with an input or bidirectional one, it is easier for us to construct a "similar" netlist as the original one.
The above is a brief description of these statistics and reasons why they are important to us.We will discuss them in detail in the following paragraphs.
The size distribution function Ps(s) is a prob- ability function of cell size.For any possible physi- cal size s of a cell, Ps (s) will give us the probability that a cell in the circuit has size s.
Since the probability function P(s) is not ana- lytical, we will use a linear array to represent it.Thus we need to quantitize the size s first.
The actual implementation is: first find the mini- mum cell size Smin and the maximum cell size Smax in the circuit.We assume that function P(s) will have a non-zero value only when Smin_<Size_< Sma.This means, all the cells to be added later will have sizes no larger than Smax and no smaller than Smin.
Then we evenly divide the range [Smirl, Smax] into 100 sub-ranges so that we have 100 buckets.Each bucket corresponds to a sub-range and records the number of cells whose size falls into this sub-range.Finally, in order to get a real probability function, we normalize the values in all buckets.The result is the size distribution function which actually is a discrete function.Let us revisit the example shown in Figures 2, 3  and 4. In that circuit, we have 3 types of cells, inverters, AND gates and OR gates.Suppose an inverter has a size of 1, and AND gate and an OR gate each have a size of 100.Note that all statistics should be derived from circit Ci since Ci is the only information we know in PID.As shown in Figure 3, we have four inverters, one AND gate and one OR gate.Thus the number in our first bucket is 4, the number in our last bucket is 2, and the numbers in the other buckets are all zero.After normalization, the probability of being in the first bucket is 66.7% the probability of being in 100th bucket is 33.3% and probability of being in other buckets is zero.function is not independent of the size distribu- tion.A smaller cell will almost certainly have fewer terminals than a larger cell.We have to take this fact into account.Remember we will have 100 buckets for cell sizes.Then for each bucket, we have a separate distribution function of the num- ber of terminals in a cell.
Take the same example circuit Ci as above.The first bucket contains only inverters, so in this bucket, all the cells have a 100% chance to have 2 terminals.The last bucket contains AND gates and OR gates, but since they both have 3 terminals, so all the cells there have a 100% chance to have 3 terminals.Figure 6 shows two distribution functions of the number of terminals corresponding to the first and the last bucket.Finally, due to the same reason as above, the I/O type distribution for terminals is not an inde- pendent function either.Thus we have a separate I/O type distribution function for each bucket.
Specifically, for all cells in a certain bucket, count the number of input, output and bidirectional terminals.Then normalize the values.Again for circuit Ci shown in Figure 3, the first bucket has four inverters, so 50% of the terminals are inputs and 50% of them are outputs.Similarly, the last bucket has one AND gate and one OR gate, so 66.7% of the terminals are inputs and 33.3% of   the terminals are outputs.Figure 7 shows two I/O type distribution functions for these two buckets.This is useful in determining the I/O type of a newly added terminal.If a terminal belongs to a cell in bucket 1, there is a 50% chance that it will be an input or output terminal.
It is natural to have these three for the set of cells.If timing information is an issue in the placement, we should also include some statistics about the timing information.For constructing a missing cell, we think these three statistics are adequate to represent the characteristics of the set Adj.
Based on this discussions, we can write the pseudo-code for finding missing cells, set Ja as following: 1. AddCell(circuit C,i,pc) { 2.
Get these three statistics discussed above.
Create a cell data structure.

6.
Determine the size of this cell using the size distribution.

7.
Determine the number of terminals on this cell using the appropriate distribution function.8.
For each terminal on the cell, determine its type using the appropriate terminal type distribution.

9.}
In Steps 6, 7 and 8, we use randomly generated numbers and distribution functions to determine different properties of each missing cell.For example, the size distribution function Ps (s) gives the percentage of cells in each of the 100 buckets.Thus we can randomly pick a bucket according to this probability function.The size of the cells in this bucket will be assigned to the to be added missing cell.This method can also apply to Steps 7 and 8.
After this procedure is done, we have added a set of cells -/a to the circuit C'.These newly added cells are isolated since no nets are connected to them.The next step is to add some nets to the in- complete circuit C,i.We will refer to all the exist- ing nets already in Ci as "old nets" and all the nets we will add later as "new nets".Similarly, all the cells previously existing in C,i are called "old cells" and all the cells added by AddCell() are called "new cells".
Things are not so easy when finding the set of new nets, A/'a.The reason for this is because the set of nets is more like a graph, so it is vague to say one graph is more similar to a given graph than another one.On the other hand, netlist informa- tion is the very factor which we cannot ignore.
In the actual implementation, we use only one statistic for the set of nets, the number of terminals in each net.That is, we need to know how many nets are 2-pin nets, how many nets are 3-pin nets, etc.This is no doubt be an important statistic, but it should not be the only one to determine the set of nets.The reason why we only chose this one is because: 1.It is not clear what other statistics will be good representatives for the set A/'i.
2. This one is easy to implement, and other useful statistics can be easily added later.
Even after deciding to use only one statistic, it is still not clear how to get the whole missing netlist, the set A/'a.
The first thing we need to know is the number of nets to be added.This can be found by using the input parameter Pn.
After that, a natural scheme will be similar to what we did on adding new cells: Look at all the cells in the circuit, including those "old" cells in and those "new" cells added by AddCell(), and create a list of all the terminals unattached to any nets.Initially, this list/ will include all ter- minals from all new cells and those unattached ter- minals in the old cells.
As the example shown in Figure 4, this list will contain two pins in N1, two pins in N2 and the input pin in M8.
After the list/ is created, for each to be added new net, first determine the number of terminals in it using the distribution function.Then assign terminals from the list/ to this new net and delete those assigned terminals from the list Z;.Repeat this procedure on the next to be added new net.
One of these following three cases will happen during this procedure.
1. List/2 is empty after all nets have been added.
(This is great.)Then we have finished our re- construction procedure on the circuit C .
2. There are no terminals left in list/2 when adding a new net.
Then we can randomly pick any terminals in the circuit C and assign it to this net.
3. There are still some terminals left in list/2 after all nets have been added.
Actually, Case 3 will happen a lot in real life.This is because of the way we get the circuit Ci.For example, if in the original circuit C, a 4-pin-net is connected to cell A, B, C and D, and later we only delete cell D from the circuit C to form the circuit Ci while retaining cells A, B and C, then this net will still exist in the incomplete circuit Ci, except that now it becomes a 3-pin-net instead of a 4-pin- net.
This fact suggests that some terminals in newly added cells should be assigned to an old net as well.That is why the number of terminals in list/2 is almost always larger than the total number of terminals in all new nets.
Based on this analysis, if Case 3 happens, for each terminal left in the list ;, we will randomly pick either an old net or a new net and assign this terminal to it.We will refer to this patch method as fusion as shown in Figure 8.
However, fusion is not the only way to accomplish such a task.We have an alternative patching method, abstraction, described as the following: if Case 3 happens, instead of assigning the remaining terminals to an existing net as in fusion, we will keep adding new nets and assign these terminals to these new nets until the list/2 becomes empty.Since most terminals initially in list/2 are just terminals in new cells, in abstraction, all new cells are inter-connected and rarely is there a connection between new cells and old cells.This is shown is Figure 9.We briefly summarize the difference between fusion and abstraction as in the following: In fusion, new cells are attached to both new nets and old nets, so they are connected to both old cells and new cells; while in abstraction, new cells are only attached to new nets, new cells form kind of a cluster since most of their nets are internal nets.
Another difference is that the circuit C created by abstraction will have more nets than its counter- part created by fusion.
Based on these discussions, we write the pseudocode for both patching methods as in following: Get net statistics discussed above.
Create a net data structure.

7.
Determine the number of terminals on this net using the appropriate statistics. 8.
Randomly pick n terminals from 9.
Assign these n terminals to this net. 10.
Delete these nn terminals from .
Get a terminal from/3.13.
Randomly pick a net from 14.
Assign this terminal to this net.15.
Delete this terminal from/2.Get net statistics discussed above.
while/2 is not empty, do { Create a net data structure.

6.
Determine the number of terminals on this net using the appropriate statistics.7.
Randomly pick nn terminals from ;.

8.
Assign these nn terminals to this net.

} 11.}
Intuitively, fusion makes much more sense than abstraction, since it appears that fusion will generate a circuit more like the original one, circuit C, while abstraction will almost never look like C.
Contrary to people's intuition, experimental results show that abstraction offers much more accurate prediction than fusion does.In the next section, we will present this interesting experimen- tal result, followed by an explanation.

EXPERIMENTAL RESULTS AND DISCUSSION
In Section 4, we gave the pseudo-code for our approaches.These approaches were implemented using C + +.All experiments were run on a Sun Sparc-20 workstation.Three MCNC benchmark standard cell circuits were used for experiments.
Table I shows some basic statistics for these three benchmark circuits.We delete all the I/O pads from all three of these circuits, allowing us to con- centrate on the effects of incomplete data on core cells.As shown in Table I, circuit Nprimaryl is the MCNC benchmark circuit primary without I/O pads, and circuit Nprimary2 and Nstruct are MCNC benchmark primary2 and struct without I/O pads, respectively.
We feed the reconstructed circuit to the high quality placement tool called NRG [12].Since this is a statistical approach, we needed to run a good number of trials to get the data.Thus we run NRG using the fast mode.
For each benchmark circuit C(3//,A/'), for a specified degree of incompleteness pc.We first delete Pc" 13/[] cells and the nets attached to them to form Ci. Then we run our two reconstruc- tion procedures, fusion and abstraction, to get a "reconstructed" circuit C' (fusion and abstraction were discussed in detail in Section 4).After that, we use the NRG placement tool to get the total wirelength of C and compare this value with the value of the original circuit C.
Table II shows the basic statistics for the "reconstructed" circuit Nprimaryl using different degrees of incompleteness.The first row, 0% in- completeness, is the statistics for the original circuit Nprimary .
Table III shows the total wirelength results achieved from the reconstructed circuit Nprimaryl For each degree of incompleteness, column "Ave WL" shows the average total wirelength over all trials; column "std.Dev." shows the standard deviation of all trials, and "% error" shows the percent error compare to the real value from the original complete circuit Nprimaryl.Figure 10 shows the prediction error vs. percentage of incompleteness for circuit Nprimaryl.
It's clear that fusion has a much bigger error than abstraction for any percentage of incompleteness.Since this is a non-deterministic procedure, stand- ard deviation is another important factor to look at. Figure 11 shows the std.deviation vs. percentage of incompleteness for Nprimaryl.However, there is not a clear pattern in this figure.All the data points are spread in the range between 0.7% and 1.7%.Standard deviation does not increase as the percentage of incompleteness increases.This is determined by the nature of fusion and abstrac- tion.Since fusion and abstraction rely heavily on the statistics from the incomplete circuit Ci, the increase of incompleteness really does not affect the degree of randomness in reconstructing cir- cuit C t.That is why the standard deviation does not increase along with the percentage of incompleteness.
Similar statistics and results for Nprimary2 and struct were provided in Tables IV, V, VI and VII.
Figure 12 shows the prediction error vs. percentage of incompleteness for circuit Nprimary2.Figure 13 shows the prediction error vs. percentage of in- completeness for circuit Nstruct.From Figures 10, 12,13 and 14 we can conclude that abstraction's prediction is much more ac- curate than fusion's.That is very surprising and counter-intuitive.
The reason we might think fusion is better than abstraction is because it seems that fusion has at least some chance to reconstruct the original circuit.However, the chances of perfectly % of incomp.
# trials    reconstructing the original circuit is too small to be realized.According to the Fact described in Section 3, there is no hope to reconstruct an iden- tical circuit as C. Our only hope is that the "netlist-space" is smooth enough so that even if we make some mistakes in the wiring, the final total wirelength would not be affected by much.This is not a bad guess, but unfortunately, it is proven not to be true.Figures 10, 12, 13 show that with fusion, even for 5% incompleteness, the final re- sult can be altered by more than 50% (Nprimary2 and Nstruct), which is not tolerable.The reason why abstraction is successful is because almost all the nets it adds are within the newly added cells.That is to say, it does not alter the netlist topology in the incomplete circuit C i.As for the final prediction, the wirelength for the newly added part may not be correct, but at least the wirelength for the old part is very accurate.Based on the assumption we made in Section 3, the old part should be the dominating part, so we are going to get a decent prediction for the final result.

CONCLUSIONS AND FUTURE WORK
We formally proposed a new problem in place- ment area, placement with incomplete data.This problem arises along with the increasing complex- ity of current VLSI designs.It will become more and more important in the future.
We tried two approaches: fusion and abstraction.
We want to see how good they can predict the final wirelength/chip area using only an incomplete net- list and library.Experimental results show that abstraction is a much better patching method than fusion.With 10% incompleteness in the circuit, abstraction can still predict the wirelength with an error of 5.8%; while fusion can have an error more than 50% even with a 5% incompleteness in the circuit.

Comparisons between fusion and abstraction
shows that the netlist topology is essential to the final wirelength.In order to get a good prediction, we should try to preserve the original topology as much as possible.
Although abstraction did a decent job on prediction, there are still quite a few things we need to work on in the future.If we look at Tables III, V and VII carefully, we will notice that for the same circuit, errors for abstraction are either all positive or negative.This suggests that some systematic error exists.This gives us an opportunity to find a way to make the prediction error even smaller.Based on some properties of circuit Ci, if we can predict the sign of the error, then we can add or substract a small amount from our prediction to get a more accurate value.
However, the relationship between the signs of the predicted error and circuit properties is not known yet.

FIGURE 2
FIGURE 2 Original circuit

Figure 5 FIGURE 5
Figure5 shows this size distribution function P. The probability function Pt is a function of the number of terminals in a cell.It tells us for a cer- tain cell, what the probability is of having a cer- tain number of terminals on it.Obviously, this probability function for the first bucket (b) probability function for the last bucket

FIGURE 6
FIGURE 6 Distribution function Pt for circuit in Figure 3.

FIGURE 7 I
FIGURE 7 I/O type distribution function for circuit in Figure 3.

FIGURE 11
FIGURE 11 Std.deviation vs. percentage of incompleteness for Nprimaryl.

TABLE III
Table VIII and Figure 14 are a summary table and a summary figure of these three circuits.

TABLE VII
Wirelength results for Nstruct after reconstructing the circuit