Influence of BJT Transit Frequency Limit Relation to MOSFET Parameters on the Switching Speed of BiCMOS Digital Circuits

The use is made of the BJT transit frequency limit (fTL) dependence on the MOSFET parameters (L, Vth) to design BiCMOS digital circuits. The fTi relation is used in conjunction with the established BiCMOS gate delay models. It is shown that the minimum delay BiCMOS circuits driving the large capacitive load, can be designed at the transit frequency limit with the reduced BJT AREA factor. The time delay calculations are presented for a typical BiCMOS circuit and comparison is made with the results simulated using SPICE.


INTRODUCTION
BiCMOS is the technology combining the low power of CMOS with the high-speed and drive capability of bipolar for realizing high performance digital circuits [1][2][3].Over the years BiCMOS integrated circuits have been well char- acterized for high-speed digital logic applications [4][5][6][7][8][9][10][11][12][13][14][15][16].The circuit delay time model of the BiCMOS has been extensively studied and as a performance measure of the BiCMOS technology [12].Many closed-form analytical expressions for the gate delay have been derived through the physical and electrical modeling and are available in the literature [5,9,[10][11][12][13].Greeneich and McLaughlin [5] have obtained closed-form analytical expressions for the gate delay and have shown its dependence on device and circuit parameters.The analysis does not include high-level injection effects in the bipolar transistor model.For the devices used, high-level injection effects are not a major consideration in transient response studies.Rosseel and Dutton [6] have studied the influence of device parameters on * Tel.: (225) 388-5622; Fax: (225) 388-5200; e-mail: ashok@ee.lsu.edu the switching speed of a BiCMOS buffer circuit.The analysis examines the high-level injection effects through the parameters Ikv, the upper knee current in bipolar transistor, and shows to strongly influence the performance.The analysis also examines the influence of different emitter sizes on the delay time and it is shown that for a given area, the delay is minimum for one optimal size ratio for the MOS and bipolar transistors.Rofail and Elmasry [11] have derived analytical and numerical BiCMOS gate delay models to char- acterize BiCMOS structures using long and short channel devices.Their numerical model include high-current effects and other second order effects.
Raje et al. [12] have provided a piecewise delay expression of the BiCMOS gate delay model which takes into account high-current effects in bipolar transistor, short-channel effects in MOSFET and parasitic capacitances at the base and output.
Fang et al. [10] have proposed a BiCMOS overall delay-optimization scheme.Under this scheme, the delay is minimized when the maximum collector current is equal to the onset current of high current effects of bipolar transistors.This indicates that the bipolar transistor in BiCMOS circuits operates at a collector current density below the highcurrent region for speed-optimized BiCMOS circuits.It is also shown that BiCMOS circuits can keep the speed advantage over CMOS circuits down to submicron dimensions under constant load conditions.
A comparison of these papers shows that different analytical solutions have been obtained through the use of different assumptions.None of these work seems to include and provide a proper correlation between the MOS and bipolar transis- tors dimensions in gate delay modeling and delay minimization in BiCMOS circuits.Rothermel and Hosticka [7] have shown that there is a transit frequency below which the bipolar transistor does not contribute to the speed improvement, and hence the digital BiCMOS design techniques do not offer any speed advantage over CMOS.In this work, we have further explored the usefulness of the relationship between the transit frequency limit of the bipolar transistor and MOSFET parameters on BiCMOS gate delay models.

THEORY
In the following, we will describe the relation between BJT transit frequency limit and MOSFET parameters, and BiCMOS gate delay models.
BJT Transit Frequency Relation to MOSFET Parameters In order to develop a realistic BiCMOS speed improvement model, consider a simple BiCMOS buffer circuit which includes an internal logic as shown in Figure 1.The buffer circuit in the Figure drives a capacitive load, CL. Figure provides the necessary parasitics which are to be included in developing a relation between the bipolar and MOS transistors parameters.Figure 2 shows the equivalent circuit for the buffer part of the Figure where the transistor acts as a digital switching device.In Figure 2, the MOS transistor provides the input current source and bipolar transistor simulates the output stage of the buffer.We now assume that bipolar or MOS transistor charge and discharge the load capacitance, CL, by the same output current (louT).The input current is also assumed to be constant during switching.Thus, the time needed to build an active charge in base or channel region of bipolar and MOS transistors can be calculated from the input charge.Now for the same charging and discharging current, both transistors will have the same speed under identical input conditions, and BiCMOS drivers con- structed with them will have the same delay times.
In BiCMOS circuits, if the bipolar transistor has to switch faster than the MOS transistor, charge build-up in the base of bipolar transistor should exceed the charge build-up in the channel region of the MOS transistor.This sets a lower limit on the bipolar transistor to perform better than the MOS transistor.The limit is described by the transit frequency limit, fTL relation and is of the following fTL-- where #ON is the mobility in low electrical field, Lov the overlap length, Vth the threshold voltage, Ecm the critical electric field, and VDD the power supply voltage.The transit frequency limit, fTL is related to MOS transistor parameters (LEvy, Lov and Vth) and supply voltage VDD.For a BiCMOS circuit to perform better over the CMOS circuit, the transit frequency fT of the BJT should be equal to or greater than the transit frequency limit, fTi.
Equation (1) forfTL can be used to design BJT and MOSFET more realistically in a BiCMOS circuit for the optimum delay.

BiCMOS Delay Models
In Figure 1, transistors M1 and M3 provide base current to transistors Q1 and Q2, respectively.
Transistors M2 and M4 remove the base charge from the bipolar transistor during discharge process in switching transient.The buffer design provides identical pull-up and pull-down response.
The delay time model can be developed by applying a step voltage at the input of the buffer circuit.It can be followed from Figure that larger the transistor M1, the higher is the base and emitter currents of transistor Q1 which results in shorter gate delay.This condition may lead to BJT entering into the high-current region where Kirk effect [17,18] takes place.In practical situation, the buffer circuit is driven by an internal CMOS logic circuit as shown in the Figure 1.Now, if the transistor M1 is made larger in size by increasing its width, the gate capacitance of M1 will increase.
The gate capacitance of M1 acts as a load to the internal logic circuit (inverter in the present design) and will reduce its speed.Thus, in order to achieve the shortest delay of the BiGMOS circuit of Figure 1, it may not be necessary to drive BJT(Q) in the high-current region during the pull-up transient.BiCMOS gate delay is composed of pull-up delay due to charging of load capacitance CL through the combination of M1-Q1 transistors, and pull-down delay due to discharging of C through the combination of M3-Q2 transistors.It has been shown in Ref. [10] that pull-up and pull- down transient response of the BiCMOS buffer circuit can be made equal by making BJTs Q1 and Q2 identical and keeping widths of M1 and M3 same.Thus, one can describe the switching behavior of a BiCMOS circuit either through pull-up or pull-down delay models.In the present work, we will study the switching response through the pull-up delay models.
It was stated earlier that BiCMOS buffer circuit operates below the current level (maximum output current) at which high-current effects set-in when integrated with the internal CMOS logic.The maximum output current can be approximated to be equal to upper knee current IkF of the BJT as done by earlier workers [10] for an optimum delay calculation.It was also stated in this work that the BiCMOS circuit can be made to perform better over the CMOS circuit if transistors are designed to operate at the transit frequency limit fVL described by the Eq.(1).The transit frequency limit fw can also be assumed to be the frequency at which high-current effects set-in.Thus, opti- mum gate delay for the BiCMOS circuit can be obtained at the fT at which it can be approxi- mated that the maximum output current is equal to the knee current/kW.Earlier delay models [5,10] can be suitably modified to include the transit frequency relation of Eq. ( 1) and its dependence on MOSFET parameters.The operation of the BiCMOS circuit can be divided into three time intervals as shown in the Figure 3. (i) The time interval tl is defined as the initial delay time.The MOSFET (M1) turns-on and BJT (Q) begins to conduct until its base- emitter voltage VBE reaches about VBE(on)_0.7V.At the end of the time interval tl, the MOSFET (Ma) still remains in saturation and the BJT (Q) turns-on.The initial time delay can be obtained from an analysis of the equivalent circuit during the time interval t and is given by [5]   V. (on) where (ii) (3) WI#pCox(VDD-Vth,PI) Rch is the equivalent dc channel resistance of the MOSFET (M1).Cz, Co RB and Rc are the emitter and collector capacitances, RB and Rc are the base and collector resistances, respectively of BJT (Q).Cz, Cc, RB and Rc are assumed to be constant.Ccs is the collector- substrate capacitance of Qz and is assumed to be constant.W1 and L are the channel width and length of the transistor M1. #p and Vth,P are the hole carrier mobility and thresh- old voltage.In a typical BiCMOS circuit, Rc < Rch which makes the second term in Eq. (2) negligible.
The delay time t2 is the time interval during which BJT (Q) is on and the MOSFET (M) is still in saturation.It is to be mentioned that M remains in saturation provided its thresh- old voltage [Vth,P > VBE(On) 0.7 V of Q1.
The time delay can be obtained from an analysis of the equivalent circuit during the time interval t2 and is given by [5] t2-- where C[ is the equivalent load capacitance, 7is the equivalent forward transit time of the BiCMOS circuit.C[ and r are given by CL / CCS CL (iii) "r."rT + R c C c (6) where 7" T (1/(27rfT)).fT is the cut-off fre- quency or transit frequency of the transistor.
Cz is neglected since Vz(on) nearly remains constant and equals to 0.7 V, (Vnz -0.7 V).
The delay time t3 begins when VOUT--Vth,PI--V E(on) and M enters the linear region, and ends at the point where the output reaches the switching threshold Vs 2.5V.M1 can be substituted by an equivalent channel resistance Rch in the equivalent circuit during the time interval t3 which is of the form [5] VDD-VB(on) } t3 -Tcos -2(VDD gth,P[) (7)   where and r r5 v/(Rch / RB)C7"r ( 9) Cc (0) /: 3F C L It should be noted that for a typical device and circuit parameters To << 2/3-.For ]Vth,P] VBE(On), Eq. 7 reduces to the form t3 -Tcos-(0.5)T The total delay time td is the sum of time delay intervals t, t2 and t3, described by Eqs. ( 2), ( 4), (7), or (11), respectively.
It should be mentioned that the delay time interval t3 will create a discontinuity in the collector current at the boundary between t2 and t3.This is due to a constant term (C) which is set to 0 for mathematical simplicity in the derivation of Eq. ( 7) [5].However, it was suggested in Ref. [10] that for high-speed BiCMOS circuits, Vth,pl can be approximated to be equal to VBE(On)-0.7 V. Thus, it can be assumed that the MOSFET (M) operates in the linear region during the time interval t2 without causing a significant error.It implies that t2 0 and the time interval t3 can then be described in the following form [10] t3-Ttan_ (2/3-)T (12)   Equation ( 12) can be further simplified to the form t3 TM " T-- 2 (13) for 2/7->> T for typical devices.
The delay time to is now the sum of time intervals t and t3 since t 0, described by Eqs.
(1) and (13), respectively.The maximum output current It(max) of Q at the end of the time interval t3 can then be described by the equation of the form [10] {goD--gag(on)} The maximum output current described by the Eq. ( 14) can be assumed to be approximately equal to the knee current Ikv at which high-current effects start.Equation (14) for It(max) in combination with the Eq. ( 1) for fTL can be used to design optimum delay BiCMOS circuits.It should be noted that fTL influences time delays through the time delay interval equations for t2 and t3.

RESULTS AND DISCUSSION
Figure 4(a) shows the dependence of BJT transit time on the MOSFET channel length, obtained from Eq. (1) for a BiCMOS circuit shown in Figure 1.The typical MOSFET parameters used in the calculation are #ON 5 X 102/V-sec, Vth,N 0.8V, LOV-----0.13LEFF,Ecm 7x 104V/cm and VDD 5V.The corresponding transit frequency limit dependence on the channel length is shown in the Figure 4(b).Figure 4 can be used to obtain dimensions of BJTs and MOSFETs in a BiCMOS circuit designed to operate at the minimum delay.Figure 5 shows the simulated output voltage   -'-"- response of the BiCMOS buffer with the internal circuit.The step function input voltage which switches from 0 to 5 V is applied at a node 6.The circuit is simulated using SPICE3 (LEVEL 2) MOSFET model parameters.BJT and MOSFET model parameters are taken from the Ref. [10].
The load capacitance, CL is 5 pf.In Figure 5, V (4)   and V(2) are the voltage responses at nodes (4) and (2), respectively.In a group of V(4) plots l-V(4), Ref. [10] plot shows the output voltage response corresponding to device dimensions of Ref. [10] for the gate delay.The corresponding input voltage response at a node 2 is shown by 1-V(2), Ref. [10] plot.The MOSFET channel length is 2t.tm and BJT transit time is 20 ps for this set of curves.The plots 2-V(4) and 3-V(4) show the output voltage response for L-1.0 and 0.51am, respectively.Transit time (-v) parameters are obtained from the Figure 4(a).The corresponding input voltage response at a node 2 is shown by 2-V(2) and 3-V(2) curves.The plots l-V(4), Ref. [10], 2-V(4) and 3- V(4) are obtained using the AREA factor-14, 14   and 8 and -T 20, 55 and 20 ps, respectively for the BJT design.Figure 5 shows that the BiCMOS gate delay is further reduced from the value that is obtained for the optimized design described in Ref. [10].
Figure 6 compares the output current response corresponding to L 2 and 0.5 l.tm, respectively.The current response corresponding to L lam is not included in this figure.The plot 1-I, Ref. [10] shows the output (collector) current variation for the BiCMOS circuit design parameters of the Ref.
[10].The output current peaks at approximately 30mA and the AREA factor is 14.This plot is compared with the plot for 2-I for L 0.5 lm, and -T 20 ps obtained from the Figure 4(a).The AREA factor is 8 for this curve which provides nearly the same peak current as in the 1-I, Ref.
[10] curve.Figure 6   current peaks approximately at a half the time needed to reach the switching threshold Vs 2.5 V in plot 1-Ic Ref. [10].Thus, we can conclude from Figures 5 and 6 that the Eq. ( 1) gives a lower gate delay with the reduced BJT AREA factor under the same load condition.This is further shown in the Table I where the time intervals tl, t2, t3 and the total delay time td for the BiCMOS buffer stage are summarized.In Table I, delay time results are included for L 0.5 lam without using the Eq. ( 1) [10].SPICE3 (LEVEL 2) simulation results are also shown for comparison.In the Table I, results obtained from the use of the transit frequency relation (Eq. 1) for L 0.51am suggest that a minimum delay BiCMOS circuit can be designed even with the reduced BJT AREA factor.The presented design approach provides nearly the same maximum output current (Fig. 6, plot 2-Ic) to drive the same load (CL 5 pF) as in L 21m based design.

CONCLUSION
The BJT transit frequency limit dependence on MOSFET parameters and its direct relationship to BiCMOS delay time intervals give a minimum delay.The minimum delay is obtained with reduced BJT AREA factor and large maximum output current which is approximately to be the upper knee current.The high-current effects which start at the knee current, occur at the end of time interval t3 or the delay time td.Since the BiCMOS circuit operates below the knee current, high current effects such as degradation in current gain and base transit time are not included in the time delay analysis.This approach holds good for output voltage to rise to its switching threshold which is normally the case.The results and analysis of the present work suggest that the minimum delay BiCMOS digital circuits could be designed using BJT transit frequency limit criteria in relation to MOSFET parameters.

FIGURE 3
FIGURE3 Three time delay intervals in a BiCMOS circuit shown on output voltage waveforms.Note: Output current waveform is also included to show the maximum collector current.

FIGURE 4 (
FIGURE 4 (a): BJT transit time dependence on MOSFET channel length; (b): BJT transit frequency limit dependence on channel length.
also shows that the output current (collector current) response.