Accurate Interconnection Length Estimations for Predictions Early in the Design Cycle

Important layout properties of electronic circuits include space requirements and interconnection lengths. In the process of designing these circuits, a reliable pre-layout interconnection length estimation is essential for improving placement and routing techniques. Donath found an upper bound for the average interconnection length that follows the trends of experimentally observed average lengths. Yet, this upper bound deviates from the experimental value by a factor δ ≈ 2, which is not sufficiently accurate for some applications. We show that we obtain a significantly more accurate estimate by taking into account the inherent features of the optimal placement process.


INTRODUCTION
The production of VLSI and ULSI computer chips requires the layout (placement and routing) of the (logical) chip design onto a physical carrier.With the advent of high level description languages such as VHDL, with the extensive use of component libraries, and with the standardization of production parameters, more and more steps in the design cycle are being automated.In the early days of chip design, designing a chip manually was still feasible.Nowadays, computer aided design (CAD) tools are indispensable to cope with the complexity and the limited time resources.For the placement and routing phases, the quality requirements are particularly stringent.For the results of these phases to be good enough, accurate predictions of relevant post-layout circuit properties are an absolute necessity to limit the search in the vast solution space.Hence, CAD tools use estimator tools [1][2][3][4], usually based on partitioning meth- odologies [5].
The main circuit parameters that have to be estimated are the interconnection length in the placed design, area occupancy, attainable clock frequency, power dissipation, and (especially for *Corresponding author.Postdoctoral Fellow of the Fund for Scientific Research-Flanders (Belgium) (F.W.O.).e-mail: dstr @ elis.rug.ac.be some types of gate arrays) channel densities.The estimation is intended to be performed before the circuit is actually placed (a priori estimation) and is then used to obtain better layouts [3].The esti- mates also provide deeper insight in the placement properties of circuits on different carriers, e.g., three-dimensional architectures, where optical channels could be used for the third dimension interconnections [6][7][8].The possibilities of such architectures can be explored without the need to actually build the systems.
With physical feature sizes decreasing rapidly, the time delay of electrical signals travelling in the inter-connect between active devices and gates is approaching and even surpassing the delay through the devices and gates.The estimation of the interconnection length early in the design cycle therefore gains importance as an aid for floor- planning, placement, and routing tools.The accuracy of the estimates is of crucial importance to the final design result.A priori interconnection length estimation will become an essential step in designing systems that have to meet stringent performance criteria.
There have been a few attempts to predict interconnection lengths.A first upper bound for interconnection lengths has been found by Suther- land and Oestreicher [9].Since it is based on a random placement, it yields excessively large estimates.Donath [1,10] found that a hierarchical placement technique gives much better intercon- nection length estimates and his results have been used by several other researchers [3,[11][12][13][14][15].Recently, Van Marck and Stroobandt have exten- ded Donath's technique to three-dimensional and anisotropic architectures [7,8], Stroobandt and   Kurdahi have included models for multi-terminal nets [16,17], and Stroobandt has added the esti- mation of external interconnection lengths [18].
Comparable work has been done by Ozaktas  [19], who investigates optical architectures, based on interconnection models.Independently from Donath, Masaki and Yamada [20] derived the same interconnection length distributions and added three-dimensional extensions.Davis et al. [15] calculated Donath's wire length distribution in somewhat more detail.
Almost all recent papers on wire length esti- mates are based on Donath's pioneering research.They produce the same valuable results but they also have the same deficiencies.Donath estimates the average interconnection length using a model for the interconnection complexity of the circuit, known as Rent's rule [21].Experimentally mea- sured average interconnection lengths vary with the number of logic gates in a circuit and with the interconnection complexity of the circuit.Donath found that his theoretically obtained average interconnection length values appeared to follow these variations [1].However, Donath's calculated   average interconnection length and the actual one still differ by a factor 2. His method indeed results in an upper bound for the average inter- connection length.We would like to estimate the average interconnection length more accurately.Therefore, it is important to understand the under- lying mechanisms that cause the overestimation in Donath's calculation.
In this paper, we show that the discrepancy between the theoretical estimates and the experimentally measured values is primarily due to the lack of accuracy in the placement model used by Donath.We consider this issue in Section 4, and in Section 5, we present a way to introduce a new placement model efficiently.This leads to a better estimation for the average interconnection length (Section 6), as will be verified experimentally in Section 7.But first, we explain the circuit model and the key issues of Donath's placement technique.

MODEL FOR THE CIRCUIT, THE PARTITIONING PROCESS, AND THE PHYSICAL ARCHITECTURE
A circuit can be represented by a set of inter- connected blocks as in Figure (the blocks can be the representation of transistors, gates, or even entire circuits).An interconnection between blocks is called a net.A net that is connected to more than two blocks is called a multi-terminal net.Some of the nets are also connected to the outside of the circuit.These are called external nets (as opposed to internal nets which only connect to blocks within the circuit).In order to model these external nets properly, we introduce a new kind of block and call it a pin.A pin models the external terminal for the net.The other (internal) blocks are called logic blocks.Every external net is connected to exactly one pin.Note that the number of pins thus equals the number of external nets.Partitioning a circuit means dividing this circuit into disjoint subcircuits (called modules), each containing a subset of the blocks (Fig. 2).This partitioning is guided by some kind of criterion.Generally, the criterion is to minimize the number of nets crossing the borders of modules in the partition.Nets that are cut by module boundaries are shared between two or more modules and are said to be external to the modules.Therefore, the () Logic block net is split into a number of subnets, one for each module that shares the net.A new pin is assigned to each subnet.Each module can then itself be seen as a circuit and can be partitioned further.A partitioning process where the modules themselves are recursively partitioned is called a hierarchical partitioning method.
In partitioned circuits, a relationship exists between the number of elementary blocks B in a module and the number of the module's external connections (pins) P. It is known as Rent's rule [21]: where Tb is the average number of terminals per elementary block and r is called the Rent expo- nent.This exponent is a measure of the intercon- nection complexity of the circuit [19].Its value increases for increasing interconnection complexity.Generally, r varies from around 0.5 for simple regular circuits (such as Random Access Memo- ries), up to 0.75 for complex circuits (such as fast full custom VLSI circuits) [22].The validity of Rent's rule is related to the fact that designers tend to build their circuits hierarchically, roughly ex- hibiting the same complexity at each level of hier- archy.Rent's rule seems to apply to nearly all circuits.Figure 3 shows the results of a circuit lOO ISCAS89 benchmark 's9_5@ "o The size of the circles corresponds to the percentage of modules that has P pins and B blocks in a pool of modules around an average number of blocks.
partitioning according to the 'ratiocut' partitioning method [23].Rent's rule can be observed easily (especially when considering the average values) and the Rent exponent is found to be 0.68.1 The model for the circuit alone does not enable us to estimate interconnection lengths since these only get their meaning after the placement of the circuit in a physical architecture or carrier.The physical architecture often is a regular structure (in gate arrays and standard cell layout) or can be modelled as one (as a first order approximation).We therefore model it as a square (part of a) Manhattan grid (Fig. 4(b)).In this grid, each gridpoint (cell) corresponds to a location where one logic block of the circuit can be placed.The gridlines correspond to the channels in which the connections between the gates can be routed.All lengths are thus measured using a Manhattan metric.

DONATH'S TECHNIQUE
3.1.Hierarchical Placement Donath's technique to estimate the average inter- connection length is based on a hierarchical placement of the circuit into a square Manhattan grid [1].The circuit is partitioned hierarchically into subcircuits.Each subcircuit at a hierarchical level consists of four subcircuits (of equal size) at the next (lower) level of hierarchy (Fig. 4 (a)).We thus assume that the number of gates in the circuit is a power of 4 (there are 4/ gates, with K the number of hierarchical levels).The circuit is placed in a square Manhattan grid, which is also partitioned into four subsquares of equal size (Fig. 4 (b)).
In Donath's partitioning and placement scheme, each subcircuit is assigned recursively to a sub- square until all gates are assigned to exactly one grid location.The recursion levels will be ntm- bered K-1 (four subcircuits that constitute the entire circuit) down to 0 (four subcircuits consist- ing of only one logic gate).Note that external in- terconnections are not included in the estimations (these interconnections belong to level K and are considered in [18]).
The partitioning of the circuit into four sub- circuits of equal size should be done in such a way that the partition satisfies Rent's rule.That is, we want to keep the number of interconnections between the subcircuits as small as possible.This is a necessary condition if we want our placement scheme to be a good model for the optimal mapping (a) (b) FIGURE 4 Recursive partitioning scheme of the circuit (a) and the physical architecture (b).
The deviation from Rent's rule at the partitioning levels with very large module sizes is explained in [21,24].In this paper, we will not elaborate on this issue.
placement of the circuit.We define an optimal placement as one that minimizes the total inter- connection length.It is indeed obvious that such a placement tries to place densely interconnected logic gates as close as possible, resulting in clusters of such gates.Among clusters, there are fewer intercormections.A placement scheme that keeps the number of interconnections between the subcircuits as low as possible thus leads to many short interconnections and few long ones.This behaviour is modelled accurately by the module pin numbers following from Rent's rule.

Average Interconnection Length
Given the above model for the circuit, the physical architecture and Donath's placement, we want to find the average interconnection length.We can do this by calculating the average number of inter- connections Nk and the average length of the interconnections lk at every hierarchical level k (0 < k < K-1).The average interconnection length L (in number of cell pitches), computed over all hierarchical levels, is then given by L-EkL Nkl:. ( K-1 k=0 Nk The computations of Nk and lk are performed for point-to-point interconnections only (as in [1]).
This simplification is based on the knowledge that these nets outnumber all other nets in circuits and that multi-terminal nets can be modelled as a collection of point-to-point nets by pairwise connecting some of the net terminals until a path exists betveen every pair of terminals (possibly via other terminals).This simplification somewhat shortens the average wire length but it does not have too much influence on the average values computed in this section.In [16,17], Stroobandt   and Kurdahi present a possible way of including multi-terminal nets into the calculations.In order to keep the reasoning clear, we will not consider this extension in this paper.
The expected number of interconnections at each level of the hierarchy can be calculated using Rent's rule and can be seen to be [1] N CTb 4(1 --4r-1)4k(r-1), where, according to Donath, c 1/2 more or less models the presence of multi-terminal nets.
We now seek to find the average interconnection length l for point-to-point interconnections at hierarchical level k.The interconnections belonging to hierarchical level k are those interconnec- tions between logic blocks belonging to the same (k+ 1)-th level hierarchical subcircuit, but to different k-th level hierarchical subcircuits.Those interconnections thus connect two gates placed in different squares at hierarchical level k.Only two different combinations are possible: either the squares are adjacent or they are diagonally oppo- sed (Fig. 5).We will call the first combination an A-combination, the second one a D-combination.
For each of these combinations, we compute the average interconnection length (denoted as l,a for A-combinations, 1, a for D-combinations).For this, it is assumed that the starting points and the end- points of the interconnections between two squares are uniformly distributed over those squares (from now on, we indicate starting points and endpoints of interconnections as interconnection points).The enumeration of all possible lengths (distances between interconnection points) for the two combinations on every hierarchical level k, is straightforward.The distributions are given by [14] Sk,a(1) Two possible combinations at a hierarchical level k: an A-combination (a) and a D-combination (b).
for an A-combination, and for a D-combination.In these equations, the squares have size ,2 (Fig. 5) with A 2.
The expected value for the average length in a certain combination at a hierarchical level k then equals (with C E {a, d}) E2o s,(z) lk,c--_]oSk,c(1) (6) and results in 4A lk,a---3 3, (7) lk,a 2A, ( with A 2k.A more efficient way of calculating these average wire lengths makes use of generating polynomials and is presented in [25]. Since there are four A-combinations and two Dcombinations, the total average interconnection length lk at the hierarchical level k is given by /k 4/k,a + 2/,a 6 (9) Combining Eq. ( 2) through 9 yields with 14H(K,r, 1) 2H(K,r, 3) 9H(K,r, 2) (o) Note that this function should be extended continuously in the singular point r x/2.

Asymptotic Behaviour
The calculations from the previous section show a different scaling behaviour for different Rent exponents.With the total number of logic blocks (or gates) G equalling 4/, the scaling behaviour is given by LG 2, r>0.5 L log(G), r 0.5 L /(r), r < 0.5 (12) where f(r) is independent of the number of blocks G.The Rent exponent thus plays an important role.For complex circuits (r > 0.5), the average length increases with the size of the circuit, whereas it is independent of circuit size for circuits of modest complexity (r < 0.5). 4. A CRITIQUE OF DONATH'S APPROACH Donath reported a good resemblance between theoretical and experimental scaling behaviour but a more or less constant deviation between theory and experimental results of a factor of approximately 2 [1] (see Fig. 6).In order to be able to predict interconnection lengths more accurately, it is important to understand the underlying reasons for this.Donath's estimation technique is primarily based on his hierarchical placement scheme.Every Lexp for circuits of varying size (according to the data provided by Donath in [1]).
hierarchical level is treated separately without any knowledge on the length of interconnections from other levels of hierarchy.Donath simply assumes that the interconnection points are uniformly distributed over the gates of the square grid.It is nevertheless clear that an optimal placement strategy will place interconnected logic gates as elose as possible, regardless of the hierarchical level the interconnection belongs to.and 8 for the two combinations; the darker the zone, the higher the number of interconnection points).Consequently, the interconnections at lower levels (e.g., k-1) will be placed at the center ot the square at level k which is, again, the border of a square at level k-1.This clearly represents the optimal placement behaviour.Donath's technique does not take full account of this information.On the contrary, the assumption of a uniform distri- bution of interconnection points models a random placement at each level.The average intercon- nection length found by Donath therefore remains an upper bound for the real value.We define an interconnection length distribution as a collection of values, indicating, for each length l, how many interconnections have this length.The sum of these values over all lengths equals the total number of interconnections.The normalized distribution denotes, for each length l, the fraction of interconnections that has length I.The global distribution is defined as the interconnection length distribution of the entire circuit.The global dis- tribution contains information about all intercon- nections considered together.At each hierarchical level, we can also define a local distribution.Such a distribution only contains information about interconnections at a specified hierarchical level.
D. STROOBANDT AND J. g.CAMPENHOUT Square 1 Square 2 FIGURE 7 The placement of interconnection points in an A-combination (darker zones contain more points).

Square
Square 2 FIGURE 8 The placement of interconnection points in a D-combination (darker zones contain more points).

Stochastic Model of the Placement Process
A physical placement of a netlist 2 is a list of N pairs of points "PN ((P1, Ol),..., (PN, ON)) in the physical architecture (Manhattan grid).Each pair represents a connection to be routed.Both the number of pairs N and the exact value of their coordinates (Pi, Qi) can be considered random 2Again, we only consider point-to-point nets.
variables; 79N is a stochastic process.The joint distribution of N and 79N follows from the choice of a circuit out of the pool of all "meaningful" circuits and an optimal (possibly randomized) placement into the physical architecture.
Once the list 7u is known, both the wire lengths and the hierarchical level in Donath's partitioning model are fixed: they are functions of 79N through the length distribution of the architecture.We can thus write the length of a connection (Pi, Q;) as L (Pi, Qi) a= Li.The hierarchical level K (Pi, Qi) 6__ Ki also follows from the actual places of P and Q in the Manhattan grid.
We assume that the precise order of the elements of 79N is not important and we limit our scope to circuits with a preset number of connections N. On the basis of this assumption, we can assume that the distribution of the first connection (P1, Q1) characterizes the other interconnections (this does, however, not imply statistical independence be- tween pairs).Finally, we implicitly assume that the processT)u ((P1, Q1),..., (PN, QN)) possessescer- tain ergodic properties so that, for instance, the distribution of L (P1, Q1) can be estimated from the statistics of (L(P1, Q1), L(P2, Q2),..., L(PN, QN)) ofa "typical" circuit, valid for the entire population.
For N large enough, the expected values of the observed statistics for the interconnection length distributions are good estimates for the intercon- nection length distributions themselves.The global normalized wire length distribution g of a circuit, placed in a Manhattan grid, can then be estimated by the probability distribution of L1 gl P{L(P1, Q1) l} (13) and the global wire length distribution Dl by Dl Ngl NP{L(P1, Q1) l}. ( The local normalized wire length distribution (denoted by Adk,l) is the conditional distribution JMk,l P{L(P1, Q1) IIK(P1, Q1) k} and the local wire length distribution Ek,l at level k can be calculated by multiplying the normalized distribution by the expected value of the total num- ber of interconnections at level k (denoted as Nk).This expected value is given by which results in (16) NP{L(P1, Q1) l, K(P1, Q1) k} (17) 5.3.Structural Distribution and Occupancy Probability Donath's method for wire length estimations [1] is based on the enumeration of all possible inter- connections (pairs of points) in each adjacent combination and each diagonal combination and on all hierarchical levels.This way, one obtains a wire length distribution that only depends on the physical architecture the circuit will be placed in.We will call this distribution the structural distribution [26].The distributions Sk,a and Sk,d, calculated in Donath's method (Section 3), are the normalized structural distributions for a square Manhattan grid.
We can also assign to each pair of points the probability that an interconnection between the two points will be effectively laid out in an optimal placement of the circuit with preset Rent exponent.
This is what we call the occupancy probability.
Let ,4 be the set of all points in a square (finite) subregion of the Manhattan grid.The structural distribution $(l) is then determined by the enu- meration of all pairs (p, q) in the Manhattan grid, a distance L(p, q)= apart.If we call this set of pairs N'(l), then the structural distribution is given by the number of elements in that set

S(I) W(/)I (18)
with A/'(l) {(p, q) A x 4"L(p, q) l}. ( 19) The occupancyprobability ofa pair ofpoints (p, q) is the probability that the pair will effectively be connected by a wire in an optimal placement of the circuit in the physical architecture, and this probability is given by Pp,q P{ (P1, Q) (p, q)}. ( We can now write the global wire length distribution Dr, normalized on the total number of interconnections N, as P{L l} P{(P1, Q) N'(l)} Z P{(P' Q) (P'q)}" L(p,q)=l Since we only consider the wire length as criterion for an optimal placement, we can assume that P {(P1, Q1)= (P,q)} only depends on the length L(p, q) but not on the precise location of the points p and q.If we denote an arbitrary pair (p, q) with L(p, q) as (p, q)l, then follows Dl P{(P1 Q1) (P q)t) Z N L(p,q)=l The factor P{(P1, Q1)= (p,q)l} is the occupancy probability of the pair (p, q)l.As it only depends on the length, we denote it as f(l).The second factor on the RHS of the equation is the number of pairs with length l, available in the physical architecture.This factor thus equals the structural distribution S(l).Therefore we can write f(l) S(l).
By changing the distribution function of the interconnection points we actually change the occupancy probability f(l) for pairs of points, i.e., the probability that a pair of points in the Manhattan grid would be connected in a real placement procedure.We know that an optimal placement prefers shorter interconnections over longer ones.It thus seems acceptable to assume that most point pairs at the shortest distance will be occupied and less at longer distances.Intui- tively, we expect the occupancy probability to be a monotonically decreasing function of the wire length.On the other hand, we should also consider the fact that the interconnection complexity of the circuit restricts the possible choices so that not all interconnections can have the shortest length.It is not possible to place interconnected logic blocks close to each other if other blocks have already taken those positions.These restrictions increase for circuits of higher complexity.The occupancy probability therefore should depend on the Rent exponent in such a way that it decreases less (more) rapidly when the Rent exponent is larger (smaller).In the next section, we will suggest a possible expression for the occupancy probability.

Global Occupancy Probability
In [10] and [14], simple theoretical considerations are used to indicate that the normalized distribu- tion gl of interconnection lengths for a good two- dimensional placement in a square Manhattan grid should be of the form 1 " C 2r-3 (1 < </max) , 0 (1 >/max).
In this equation, C is a normalisation constant and /max is a constant related to the size of the square grid.In [3], Stroobandt et al., showed that the trend of gl (Eq.( 22)) mainly depends on the number of interconnections Nk (given by Eq. ( 3)) at each hierarchical level and not on the way these interconnections are distributed locally (i.e., per hierarchical level).Using Eqs.( 21) and ( 22), we can derive an approximated equation for the occupancy probability.Note that the approximation must be most accurate for small values of since these occur most frequently and dominate the distribution.The structural distribution S(1) can be found by the enumeration of all possible point pairs of length and is given by [4] A 2 (l =0) ]l(6A2-61A+l 2-1) ](2A-I-I)(2A-1)(2A-I+ I) (A</_<2A) otherwise (23) It can be seen that the structural distribution increases linearly with l for small values of 1.This can also be verified from Figure 9.We thus ap- proximate the structural distribution by a distribu- tion proportional to l.Therefore, the occupancy probability can be approximated by 12r-3 1 with C a normalization constant.This occupancy probability obeys the requirement of a monotoni- cally decreasing function of the wire length.It also takes into account the restrictions imposed by Rent's rule: the occupancy probability decreases less rapidly for higher values of r.Indeed, finding the placement of a complex circuit is a lot more difficult than finding the placement for a circuit Distance between cells FIGURE 9 The normalized structural distribution of a Manhattan grid of 1000 1000 cells in a log-log plot.Wirelength FIGURE 10 The global wire length distribution as a result of weighing the structural distribution by the occupancy prob- ability for a Manhattan grid of 1000 1000 cells.
that is less complex.The placement results in longer wires in the first case than in the second.
The approximation of the structural distribution (proportional to l) introduces a huge overestima- tion of the number of wires with length > A/2 (with A the side of the Manhattan grid).The result of this overestimation is an underestimation of the occupancy probability for these wire lengths.Yet, we should note that 1. the number of wires with such lengths is negl- igible compared to the total number of wires; 2. the global wire length distribution only follows 12r 3 until a certain value /, smaller than the maximum distance in the grid; for greater lengths, the distribution decreases much more rapidly (see Eq. ( 22)).
Figure 10 shows that, conversely, the global distribution, found as the product of the (approxi- mated) occupancy probability with the structural distribution, follows the behaviour observed by Donath (Eq.( 22)), even for large values of l.

Local Occupancy Probability
The local wire length distribution on each hier- archical level can also be expressed as the product of the structural distribution at that level and an occupancy probability.We can write the local wire length distribution Ek,t (normalized on N) as N P{L(P1, Q1) I,K(P1, Q1) k} P{(P1, Q1) (p, q)). (25) L(p,q)=l K(p,q)=k Also within one level, the wire length remains the only criterion for an optimal placement, so we can still assume P{(P, Q) (p, q)} to only depend on the length L(p, q), and not on the precise location ofp and q.We now denote an arbitrary pair (p, q) with length L(p,q)= at level K(p,q)= k as (P, q)l,k and we denote the set of all pairs at level k that have length as N'k(l).This then leads to k,l p{ The factor P{(P1, Q1) (p, q)t,k} is the occupancy probability of a pair (P,q)l,k.Since we assumed that it only depends on the length of the intercon- nection, it is also given by f(l).The second factor is the number of pairs (connections) at level k with length and thus equals the local structural distribution 8k(l).
Donath implicitly assumes a uniform occupancy probability (all pairs have equal probability of being 'occupied'): P{(P,Q)= (P,q),k} is inde- pendent of p and q (and thereby also independent of the length and the level).For the local normal- ized distribution Adk, this means, according to Donath, jkD, P{L(P, Q I The normalized local wire length distribution in Donath's method thus equals (as we already know from Section 3) the normalized structural distribu- tion.
We already observed Donath's model not to be a good model for an optimal placement within one hierarchical level.Therefore we introduce, at each hierarchical level, our non-uniform occupancy probability f(l)-C12r-4 for each separate pair of points (p, q)t,k.In the next section, we calculate the average wire length by making use of this occupancy probability f(l). 6.NEW AVERAGE WIRE LENGTH   We assume that all local occupancy probabilities are given by f(l)= C/2r-4 (Eq.( 24)).That way, we introduce information on the optimal placement of the entire circuit in each hierarchical level.
The local distribution at hierarchical level k is to be found by weighing the structural distribution Sk, c (CE {a,d} Eqs.( 4) and ( 5)) with the occu- pancy probability f(l)= C 2r-4 (Eq. ( 24)).The expected value for the average length in a certain combination at a hierarchical level k then equals (with C E {a, d}) lk c ']o lSk,c(1)f(l) (28) 4A El=0 Sk,c(l) 12r-3 20 Sk,c(l) 12r-4 (29) The average interconnection length at hierarch- ical level k is then given by Eq. ( 9): 4lk,a + 21k,a The sums in Eq.(29) can not be computed analytically without knowing the value for A 2 .
Yet, if we want to compare our results with those of Donath, both numerically and theoretically, an analytical form of the average interconnection length is needed.A way around this problem is to approximate the discrete distributions by contin- uous ones.One can easily verify that the continuous form of the Eqs.( 4) and ( 5) is given by S k,a([)-- A substitution of the sums in Eq. ( 29) by integrals, for a Manhattan grid with an infinite number of points in each dimension and size A x A for each submodule at hierarchical level k, yields o A SCk,c(1)12r-3dl lk,c f:A SC,c(l)12r_4d (32) For r > 0.5, this results in lk,a--Ra(l') (33) (2r-3) 42r-32r+l -+-322r- Ra(r) (2r + 1)42r-1 32r + 322r-1 (36) and lk-AR(r), (37 The sum over all hierarchical levels (Eq.( 2) H(K,; with H(K,r,x) 22r-x- The integral in the denominator of Eq. (32) does not converge at the lower bound for r < 0.5.This means that it is fully dominated by the values around 0, an area where the value should be zero in the discrete case (sums).The error introduced by the continuous approximation then becomes extremely high but the divergence of the integral shows that the average length no longer scales with A, but remains constant.We will not elaborate on the details here.Since the conver- gence still exists for the diagonal combination, the average length will be fully dominated by it and it follows that L Rd(r) H(K, r, l) (r < 1/2).(40 (2r-3)32r+1 (2r + 7)22r + (4r + 5) (2r+ 1) 32r-(r + 3)22r + (4r + 3) (35) 7. DISCUSSION AND RESULTS
The main difference between our estimates and Donath's estimates lies in the multiplicative con- stant (R(r) versus 14/9) (Fig. 11).The factor R(r) increases with increasing r, corresponding to the fact that more complex circuits (with a higher r) tend to have longer interconnections.The value of R(r) is approximately 7/9, which is half the value found by Donath, for rather complex circuits with r < 0.8.This corresponds to our knowledge that Donath's estimates differ from experimental values in a factor 2. In all cases (0 < r < 1), our esti- mation of the average interconnection length is more accurate than the one found by Donath.

Comparison of Our Wire Length
Distributions with Donath's Figures 12 and 13 show the global distribution (filled line) as the sum of the various local distributions (point lines), for Donath's method and our method, respectively.They both follow the expected trend 12r-3 (dashed line) but our method follows this trend better for the small wire lengths (note that, due to the logarithmic scale, our , , , , 100 1000 10000 Wire length FIGURE 13 The normalized global wire length distribution, composed of local wire length distributions, calculated with our method. overestimation of the number of nets with length 2 only seems to be much larger than the under- estimation of the number of nets of unit length, but that this is not the case in reality; the order of magnitude is comparable).The improvement in the model for the optimal placement has resulted in boosting the local distributions for low values of 1.The fact that, even at higher levels, short interconnections are still abundant indeed coin- cides with the intuitive notion of an optimal placement.
The difference between our method and Donath's is also shown on Figure 14.Our approx- imation obviously is much better, especially at unit length.It is only slightly worse than Donath's for lengths 2. The fact that there still exists a deviation in our method (at very small lengths) is the result of the fact that we still treat adjacent and diagonal combinations in the same way, although their average lengths are not the same, especially not at the lowest level (1 compared to 2).A differentia- tion in the number of interconnections assigned to adjacent or diagonal combinations would re- quire an extension of Rent's rule to a second order equation.This has not been accomplished yet.
Our wire length estimation uses a better model for an optimal placement than Donath's model.This can also be seen from the following thought experiment (Fig. 15)" cut the Manhattan grid in two parts by a vertical cut.Next, count the number of interconnections that traverse the cut, assuming that a circuit with a given Rent exponent is placed according to Donath's placement model.Let the cut move from left to right and, for each cut position, count the number of crossing wires.In Figure 15, the interconnections numbered and 2 .6 Donath Our method -0.5 0 .3 0 .4 " , , , , are counted when the cut takes position 1, the interconnections 3 and 4 when the cut takes position 2.After we have done the same for a placement according to our model, based on the occupancy probability, we observe the results of our count in Figure 16.The number of counted wires (shown in Fig. 16 in % of the total number of wires, as a function of the cut position) is always smaller in our case than with Donath's model.Also the variation of this number over all cut positions is smaller.This implies that our method models an optimal placement better as an optimal placement results in shorter wires and hence a lower chance of a wire being cut.

Experimental Verification
In order to verify our model for the placement of a circuit in a Manhattan grid, we performed several experiments on benchmark circuits with our own placement program, based on simulated annealing [27].The resulting wire length distribution for one Cut position FIGURE 16 The number ofinterconnections (in % ofthe total number of interconnections in the circuit) for successive cuts and a circuit with Rent exponent 0.6 in a Manhattan grid of 256 256 cells.Comparison of Donath's placement model to our extension with a non-uniform occupancy probability.
of the benchmark circuits ('c1908') is shown in Figure 17.Also the theoretical estimates, based on Donath's technique (dashed line) and our own method (filled line), are shown in the figure.Our model, taking into account the occupancy prob- ability, obviously matches the experimental results more closely, especially for wires of lengths and 2 (which are the most important ones for the calculation of the average wire length).Wirelength FIGURE 17 The wire length distribution after placement of the ISCAS85 benchmark circuit 'c1908 nr'.
In Tables I, II, and III, the results are shown for all benchmarks.Table I shows the results for the benchmark circuits used by Donath in [1].In this table, our wire length estimates are much lower than Donath's and are related to the experimental values more closely than Donath's.
Tables II and III show the results of our own experiments with the ISCAS benchmark circuits.
These results are also shown in Figures 18 and 19, as a function of the number of logic blocks and the Rent exponent, respectively.In these figures, we have connected the corresponding points for clar- ity.The rough appearance of the curves is due to the strong dependency of the average length on both the number oflogic blocks and the Rent expon- ent.Only one of these dependencies is shown in the figures.
In Table II, we can again observe that our estimates are much lower than Donath's and that they generally follow the experimental values more closely.In some cases, we appear to underestimate the wire length.This is partly due to the fact that the occupancy probability underestimates the number of long wires at the higher levels.For circuits that are large enough, this has no real influence on the average wire length, because the number of long interconnections is relatively small.For smaller circuits this influence is no longer negligible and for those circuits we should actually change the approximation of the occupancy probability at the higher levels.Yet, it is clear, both from the tables and the figures, that the circuits for which we underestimate the average length, also lead to low estimates with Donath's technique.For these circuits, also Donath's estimates are much lower than we would expect, since we know that Donath overestimates average lengths by a factor of approximately 2 [1].The experimental value thus appears too high.This could be a consequence of not too good a placement, or it could be the result of a bad estimate of the Rent exponent.The phenomenon is even stronger in Table III   Average wire length for a placement of Donath's benchmark circuits [1].Donath's estimates (Lz) and our estimates, based on the occupancy probability (L), compared to experimentally measured values (Lexp).G is the number of logic blocks in the circuit, N the number of nets and r the Rent exponent (data copied from [1]    Donath's own results [1]).The cause of this more likely is the fact that the ISCAS89 benchmarks contain a lot of nets with very high net degree.
Multi-terminal nets are not included in the model yet.In the experimental placements, however, nets with high net degrees are very long.In normal circuits, the number of nets with high net degree is too small to cause a significant deviation in the average length [4].This is not the case for the ISCAS89 benchmark circuits.Figure 20 shows, for instance, the wire length distribution after place- ment of the ISCAS89 circuit 's832' (more figures to show this is also true for the other benchmarks, can be found in [28]).The figure clearly shows an excess of long wires compared to the general trend.These wires are all multi-terminal nets with high net degrees.Since the total number of wires is not very large, these nets do have a significant influence on the average wire length.If we do not include these 'exceptional' nets, we find a much better corre- spondence between the theoretical and the experi- mental values (for convenience, only the first 10 values of the distribution are taken into account).
These experimental values are shown in the column L10 of Table III.A comparison between those values and our theoretical estimate L gives a relative difference of less than 20% for 19 circuits out of 24.Figures 18 and 19 show that the experimentally obtained average wire length values, based only on the first 10 values of the distribution, generally are much lower than the original experi- mental values.Moreover, they are closely related to our theoretical estimates, especially when we also compare both to Donath's estimates.Although omitting the long wires obviously influences the whole experiment and the results should be discussed with great care, we can conclude that our model for wire length estimates resembles experimentally measured lengths quite good, but that our model does not take into account specific properties of nets with high net degree.This has been the subject of our latest research work [16,17].

CONCLUSION
In this paper, we have presented a modification of Donath's technique for a priori wire length esti- mation, introducing the occupancy probability as a better model for an optimal placement.This way, we have obtained a new average interconnection length estimation corresponding more closely to the experimental values than the upper bound found by Donath.Our new accurate a priori inter- connection length estimation technique can have a large impact in future CAD tools for floorplan- ning and placement, in particular in view of the increasing importance of wires in digital circuits.

FIGURE 2
FIGURE 2 Partitioning the circuit of Figure into modules.

FIGURE 3
FIGURE3 Number of pins P versus number of blocks B for every partition during the 'ratiocut' partitioning of the ISCAS89 benchmark circuit 's953', compared to Rent's rule.The size of the circles corresponds to the percentage of modules that has P pins and B blocks in a pool of modules around an

FIGURE 6
FIGURE 6 Comparison between Donath's average wire length Lth and experimentally measured average wire lengths Lexp for circuits of varying size (according to the data provided

FIGURE 12
FIGURE12 The normalized global wire length distribution, composed of local wire length distributions, calculated with Donath's method.

FIGURE 14 FIGURE 15
FIGURE 14 The global wire length distributions according to Donath's method and our method, compared to the 'ideal' distribution (normalized on the range[1... 1024]).Only the first 10 values are shown.

FIGURE 19
FIGURE 19 Our estimates (L) and Donath's (Ln), compared to the experimental values (Lexp and L10): average wire length of the ISCAS benchmark circuits as a function of the Rent exponent r.

FIGURE 20
FIGURE 20 Illustration of the existence of exceptionally large interconnections in the placed ISCAS89 benchmark circuits.
and in Figures 18 and 19.Our estimates are almost always too low and even Donath often underestimates the average length (which does not correspond to

TABLE II
Average wire length for a placement of the ISCAS85 benchmark circuits.Donath's estimates (Lz) and our estimates, based on the occupancy probability (L), compared to experimentally measured values (Lexp).G is the number of logic blocks in the circuit and the Rent exponent

TABLE III
Average wire length for a placement of the ISCAS89 benchmark circuits.Donath's estimates (Lz) and our estimates, based on the occupancy probability (L), compared to experimentally measured values (Lexp).The experimental value L0 only takes the first 10 values into account.G is the number of logic blocks in the circuit and r the Rent exponent Our estimates (L) and Donath's (Lo), compared to the experimental values (Lexp and L10): average wire length of the ISCAS benchmark circuits as a function of the number of logic blocks G.