A New Method For Low Power Design Of Two-Level Logic Circuits

A new method for implementing two-level logic circuits, which exhibit minimal power 
dissipation, is introduced. Switching activity reduction of the logic network nodes is 
achieved by adding extra input signals to specific gates. Employing the statistic properties 
of the primary inputs, a new concept for grouping the input variables with similar 
features is introduced. Appropriate input variables are chosen for reducing the 
switching activity of a logic circuit. For that purpose, an efficient synthesis algorithm, 
which generates the set of all groups of the variables and solves the minimum covering 
problem for each group is developed. The comparison of the results, produced by the 
proposed method, and those from ESPRESSO shows that a substantial power reduction 
can be achieved.


INTRODUCTION
The modern design techniques require to take into consideration in addition to the two traditional design parameters, area and speed, a third one, power dissipation [1,2,3].The wide spread use of portable and wireless communication systems increases the demand for the extension of battery life.Because the current advances in battery technology are insufficient as the applications require, low-power design of integrated circuits becomes a challenging problem [1,2,3].Also, reasons related with energy problems oblige the designers to tend at systems that dissipate less energy.
The power dissipation of a CMOS circuit consists of three factors, namely the static, the short-circuit, and the dynamic power dissipation.The prominent factor is the last one and is directly related with the switching activity of the circuit.Different logic implementations of the same Boolean function result in circuits with different switching activities.
Applying the well-known CAD tools ESPRESSO [4,5,6] , ESPRESSO Exact [5,7], and ESPRESSO Signatures [5,8] two-level logic synthesis can be performed.All the above techniques aim to the optimization of a cost function related with the area minimization.Recently new methods for minimizing the power dissipation of a logic function have been presented in [9,10,11,12].In particular, Shen, et.al [9] presented a method where the power cost of a function of the primes was used to solve an ESPRESSO-like procedure.This procedure did not, however, consider including nonprime implicants in the cover although these implicants can lead to more power reduction.In [10], Vrudhula and Xie proposed a method for two-level implementations called modified-EXPAND, using the statistic characteristics of the signals.However, it has been assumed that all input signals: i) have static probability equal to 0.5, ii) are not spatiotemporally correlated, and iii) their corresponding power dissipation is not taken into account.In contrast, Iman and Pedram in [11,12] considered signals with random probabilities and took the transitions of the primary input signals into account.Also, they defined a new notation called Power Prime Implicants (PPI).These PPI's specify the set of all implicants that are sufficient and necessary for obtaining a minimum power solution.Based on the static probabilities of the function variables, they proposed an algorithm that generates all the PPIs, which are necessary to solve the minimum covering problem.Power savings up to 4% can be achieved.However, it is assumed that all signals are not spatiotemporally correlated and therefore, inaccurate power estimation takes place.
In this paper a new method for implementing low power two-level logic circuits using the static and transition probabilities of the inputs signals (i.e.temporal correlation), is introduced.The temporal correlation has been chosen to be studied first in our research, among the remaining types of correlations, since this type of correlation occurs always in all input signals.Without loss of generality, if we have random signals, it can be considered that there is no spatial correlation and thus, the temporal correlation has the dominant role in power dissipation.In other words, the temporal correlation does not depend on the configuration of the input signals, while the spatial correlation does on.
The proposed work embodies fundamental principles from the ESPRESSO environment.Switching activity reduction of the logic network nodes is achieved by adding additional input signals to specific gates.These signals force the first level gate outputs in logic level zero for a number of combinations of the input signals.A formal method for the determination and classification of these signals is described.A synthesis tool for designing two-level logic circuits in terms of power, which selects the appropriate input variables and uses the main routines of ESPRESSO is implemented.Given the user-specified average power consumption per gate and the number of the partitions of the whole boolean space, a circuit with minimal power consumption can be achieved.The experimental results for different statistic features of the primary inputs and logic circuits indicate that proposed method achieves substantial power savings.This paper is organized as follows : In section 2 the power model is presented.Starting from an example, the proposed method is described in section 3. Results and conclusions are presented in sections 4 and 5, respectively.

POWER DISSIPATION MODEL
The dynamic power dissipation of a digital CMOS circuit can be expressed by the total number of transitions of its nodes.The dynamic power dissipation for an intermediate gate is given by : ( ) where C x i the capacitance of the i-th input, V is the operation voltage, f is the clock frequency, and ( ) E x i the transition probability of the i-th input.Hence, the total dynamic power dissipation of a complex logic circuit consisting of cascaded gates, is calculated by: where P out is the dynamic power dissipation consumed for charging and discharging the output load.
A signal x i of the logic function, ( ) ( ) , ,... , can be described precisely with two attributes, namely the static probability, p x i ( ) , and the transition probability, E x i ( ) [11,12,13].More specifically, the static probability is defined as the percentage of the time in which the signal is high and, the transition probability is defined as the probability of the signal to make a transition during two successive clock cycles.
Adopting the power model proposed in [13], it is assumed that the primary inputs are mutually-independent and each primary input is first-order temporally-dependent.Given a logic function ( ) ( ) , ,... , the associated Transition function (Tf ) [13] is defined as: where ( ) f x 0 and ( )  [13].
We deal with logic functions implemented by two-level circuits, where the first level consists of AND gates and the second one consists of an OR gate.Based on [13] the calculation of the transition probability of a n-input AND gate, y x x x n = 1 2 ... , is expressed as: ( ) where ( ) ( ) are the probabilities of the signal x i to make the transitions 1→ 0 and 1→ 1 within two successive clock cycles, respectively.The factor 2 is arisen by the fact that ( ) ( ) ( ) and thus, the derived combinations are multiplied by 2.
Eventually, the total power dissipation is given by: ( ) ( ) where x i is the i-th input of the first level, q is the total number of the inputs of the first level, y j is the j-th output of the first level, m is the number of the AND gates, C and is the input capacitance of an AND gate, C or is the input capacitance of an OR gate and P out is the power dissipation at the external load.

Description of the New Idea
The basic principles of the proposed method employing a certain logic function are presented first, while the formal description follows.For the logic function 1 4 , let us assume that the input signal x 4 exhibits low-transition probability and high static-1 probability and, the signals x 1 , x 2 , and x 3 are characterized by high-transition probabilities.The logic circuit of the function F is shown in Fig. 1.
%% Please Insert Figure 1 When x 4 1 = , the function can be expressed as F this time interval the value of the logic function depends only on the value of the internal node n 3 .More specifically, if x 1 =1, the logic value of F equals 1 for any logic value of the nodes n1 and n2.Hence, the corresponding power consumption of the nodes n1 and n2 can be reduced, i.e., we can conserve energy.Using the complement form of the signal x 4 in the first two terms of the logic function, the new logic expression, , is obtained, as it is shown in Fig. 2. In this circuit, if x 4 =1, the nodes n1 and n2 become zero and thus, they do not make any transition.The functionality of the original circuit is preserved since %% Please Insert Figure 3 %% Please Insert Figure 4 Let assume P 1 and P 2 be the total power dissipation of the two aforementioned logic functions F and ′ F , respectively.Applying eq. ( 5) for each logic form, the corresponding total power dissipations are given by: Assuming ( ) ( ) ( ) ( ) = ., ( ) p x 4 1 0 9 = = ., ( ) E x 4 0 2 = .and using eq.( 5), it can be obtained that ( ) ( ) ( ) ( ) substituting the above values of the transition probabilities into eq.( 6) and ( 7), the associated total power dissipations can be calculated by: respectively.Hence, the expected total number of the transitions (over all nodes of the circuit) per clock cycle of the corresponding logic circuit are: respectively.Apparently, the second logic implementation exhibits reduced transition activity compared with the first one.Eventually, using equations ( 10) and (11), the resulting amount of the power saving is proportional to The above observation is the stimulus for the proposed method.The formal methodology for power optimization of a Boolean function expressed in minterms taking into account the statistic properties of the input signals will be presented in the next section.
Exploiting the statistics of the input signals and using the main routines of ESPRESSO, a two level power minimization tool is developed.

Description of the Proposed Method
The goal of the introduced method is to reduce the switching activity of a two-level logic circuit.For that purpose, certain primary input signals with appropriate characteristics, as it has been presented in section 3.1, must appear in the power-optimized logic expression.The selection of all logic variables (i.e., blocking variables) with the appropriate statistic features is the first step of the proposed methodology.Then, these variables are used in the logic optimization process for reducing the switching activity as many as possible AND gates of a logic circuit.Also, it is possible to have input variables with identical or similar statistic features, which can be grouped into a number of sets, called classes hereafter.The fundamental principle that exists behind the class' notion is the partitioning of the Boolean space occupied by a logic function.Then, each partition (or class) will be optimized in terms of the power (i.e. blocking variables) and area employing the proposed method.Here, it should be stressed that area minimization is a critical issue in logic-level synthesis methods, since large logic circuits with respect to area lead to increased power dissipation [11,12].The final logic circuit results as the union of the area/power optimized partitions.
For the sake of clarity, an "informal" presentation of the basic principles of the introduced method has been done in the above paragraphs.Thus, before starting the detailed discussion of the proposed method, the precise definitions of the used principles have to be put forward.
Definition 1.The set is defined as is defined as a class of the input logic variables.The term ε is a very small positive real number or zero specified by the designer.
The lower bound of classes number is equal to one, which implies that ( ) , , while the upper bound is equal to n, which means that ( ) Apparently, the above definition implies an ordered list of classes and provides a measure of the switching activity of each class.Also, the ordering specifies the "trajectory" of the optimization process through the logic variables.
Definition 4. Working Classes, k, is defined as the number of classes, which are used for partitioning of the boolean space.
All the above definitions are necessary for the blocking variables order.In other words, using the statistics of variables we select those variables which lead to optimal power synthesis.
A new synthesis tool for designing two-level logic circuits with minimal power dissipation is developed.The tool uses as input parameters the Boolean description ( ) , ,..., of the primary inputs.
The minterms expression is chosen as the starting logic form, since it is a "primitive" form.This implies that no transformations (for instance area minimization) have not been applied on the logic function.Starting power optimization process from a different but logically-equivalent boolean form, a number of transformations would have been already applied.

step 5:
--Output circuit creation and power calculation The total power dissipation of ′ F and the average power dissipation per gate (average_esrepsso) is calculated using the power model proposed in Section 2.
Step 2: Based on the input statistics, the Transition Probability List (TPL) is derived.

Using this list the function
, ,..., , where p TPL = .All minterms of each F i contain at least one blocking variable of the class c i .
Step 3: The AVERAGE coefficient (which determines the percentage of the average_espresso mean power dissipation) and the number k of the working classes are specified by the designer.In addition, a set of k sub-functions , ,..., is derived and the power threshold is calculated (based on the AVERAGE coefficient).
Step 4, power optimization of each sub-function F i results into the function F i ' (function optimized in terms of area).The power consumption, P c j , of each cube c j of F i ' is compared with the power threshold, power_threshold.In particular, if P c j ≤ power_threshold the cube c j remains in the current class C i , while if P c j > power_threshold, the cube c j is removed from the current class C i and reduced to two cubes.One of them is inserted in the class C m , while the other in the class C n , where Cubes reduction aims at increasing the Boolean space that corresponds to the sub-functions F j , where i j k < ≤ .
Step 5: The form ′′ F is obtained by the union of the ′ F i s and thus, the total power dissipation is calculated.

Finally, in
Step 6 the user is prompted for new values of AVERAGE and k if the resulted function ′′ F dissipates more power than ′ F .

RESULTS.
The proposed method for minimizing power dissipation of a function F is implemented by a new synthesis tool, which can be considered as a modified ESPRESSO.The tool takes as inputs the statistic information of the primary inputs and the Boolean expression of the function F.
In order to study the effectiveness of the proposed method a large number of logic functions have been optimized.More specifically, logic circuits of n=7, 8,...,10 primary inputs have been chosen for optimization.For each n, three different on-set ratios {0.4,0.7 ,0.9} and for each on-set ratio value five different circuits are considered.Furthermore, for each number n of primary inputs, ten different randomly-distributed statistics files, which contain the static and transitions probabilities, have been taken into account.
For the calculation of the power dissipation it is assumed that: C or =2 C g for OR inputs, C and =1 C g for AND inputs, C INV = 1 C g for inverted inputs of an AND gate, and Tables I and II show the experimental results for two different AVERAGE coefficients.
Each table row (i.e., specific n) represents 50 (i.e., {5 circuits}×{10 statistics files}) generated logic circuits for each combination of n, on-set-ratio, and statistics.More specifically, Columns 3 and 6 give the normalized power dissipation of the outputs of the first level and the total power dissipation, respectively, when the ESPRESSO tool (i.e.area optimization) is used.
Columns 4 and 7 give the normalized power dissipation outputs of the first level and the total power dissipation derived from the proposed method.
From Table I it can be noticed that a power reduction of the total power dissipation can be achieved applying the proposed method.Moreover, the selection of the AVERAGE=100 results into a "balanced" power dissipation and reduction between the total power dissipation and the power dissipation at the first level outputs.Using the values of Table I, the relation of the power and area reduction (or increase) of a logic circuit (or logic circuits) with the corresponding power consumption and area after ESPRESSO execution is shown Fig. 5.It can be noticed that the curve of "area" follows the curve of "power".Generally, the use of the blocking variables do not increase the area of the power-optimized two-level logic circuit.It should be stressed that the mean variation of the area ranges from -2.4% to +0.6%.

%% Please Insert Table I
%% Please Insert Figure 5 The Table II shows the maximum values of the power savings among the fifty (50) logic circuits of each row of Table I.It can be easily seen that the half number of the logic circuits exhibit power savings ranging from 12% and 20%, while the remaining circuits achieve gains ranging from 5% to 10%.Therefore, the obtained power savings imply that the proposed method can approaches the theoretical boundaries satisfactorily (for logic level design is about 20% [1,2,3]).
If the designer requires large power reduction only in the outputs of the first level, a large AVERAGE (e.g.AVERAGE=1000) should be chosen.Table III indicates significant power savings in the nodes of the first level, while the total power consumption is increased comparing with the associated power consumption of the area-optimized function.The increased power consumption comes the fact that all cubes (i.e., AND gate) remain in their class.Each cube has a lot blocking variables resulting into an output with low activity.
Although the choice of a large AVERAGE value results into increased power consumption, this can be used in multilevel circuits, which have nodes with large fanouts.Therefore, the reduction of the activity becomes extremely important factor of the total consumption, due to high capacitance of the node.It is apparent that the above design approach cannot be used as a two-level approach but as a technique in a multilevel design process.

%% Please Insert Table II
%% Please Insert Table III

CONCLUSIONS
In this paper, a new synthesis algorithm for minimizing the power dissipation of twolevel logic functions is presented.Using the statistical properties of the primary inputs, appropriate variables have been selected for reducing power dissipation.The introduced synthesis method achieves remarkable reduction of the total power and/or the first level outputs power dissipation, depending on the selected AVERAGE and the number of working classes values (parameters).Future research work in this area will include the impact of using the blocking variables in a multilevel logic synthesis environment.

2 Using 3 )
selecting the signal x 4 as blocking variable (definition in Section 3.2), the logic operation remains unchanged but the nodes n 1 and n 2 dissipate less power compared with the starting form of the logic function F. %% Please Insert Figure and applying the twolevel optimization tool ESPRESSO, three groups of the minterms {12,13,15,14}, {13,15,9,11}, and {15,14,11,10} are obtained, as it is depicted in Karnaugh-map of Fig. 3. Since we would like to exploit the statistic characteristics of the input signals, the complement signal, x 4 , must appear as many times as possible in the terms of the function F. It can be proved that the subsets of the minterms {9,11,13,15}, {12,14}, and {10,14}, result into the power-optimized logic function ′ = + + F x x x x x x x x as it is shown in Fig. 4.

F
= espresso(F); --′ F is the output of ESPRESSO tool.espresso_power = power_estimation( ′ F ); --average_espresso is the average power per gate --of ′ F , n_esp is the number of cubes of ′ F average_espresso = espresso_power / n_esp; of power threshold and selection of "working" classes read (AVERAGE); --power_threshold is the power threshold of each cube.power_threshold = average_espresso * ( AVERAGE/100); read(k); --Work with the first k classes of TPL where 1 ≤ k ≤ p. the remaining minterms go to the class F k +1 .step 4: --Optimization and power calculation in each working class

Figure 1 .Figure 2 .Figure 3 .
Figure 1.The logic circuit of function F Figure 2. The Logic circuit of the modified function ′ F

Figure 4 .Figure 5 .
Figure 4. Karnaugh map of function ′ F for power reduction Figure 5.Comparison of the power and area reduction (or increase) of the proposed method with the corresponding power consumption and area after ESPRESSO execution.
x T are the values of the function at the time instances t=0 and t=T, . Each member x i of the set C l is called blocking variable.
Let C 1 , C 2 , ..., C p , 1 ≤ ≤ p n be the different classes of the function F, taking into account the statistics properties of the primary inputs.Definition 3. Transition Probability List (TPL) is defined as the set

-definition of power threshold and working classes if
(our_power ≥ espresso_power) then --Ask for new values of AVERAGE and k if (prompt_for_new_iteration( )= TRUE ) then goto step 3); --Run steps 3 to 6 again.else return ( ′ F ); --If there is no better power-solution, return ′ F .else return ( ′′ F ); --else there is a better power-solution, return ′′ F .end Power_Logic_Synthesis function; Step 1: The function F is optimized by ESPRESSO tool and a new form ′ F is derived.

Table I :
Comparison results of ESPRESSO and the proposed method in terms of the first level outputs and total (normalized) power dissipation , with AVERAGE = 100 and k

Table II :
Minimum Power Dissipation for AVERAGE=100.

Table III :
Comparison results of ESPRESSO and the proposed method in terms of the first level outputs and total (normalized) power dissipation, with AVERAGE = 1000 and k

Table I :
Comparison results of ESPRESSO and the proposed method in terms of the first level outputs and total (normalized) power dissipation , with AVERAGE = 100 and k

Table II :
Minimum Power Dissipation for AVERAGE=100.

Table III :
Comparison results of ESPRESSO and the proposed method in terms of the first level outputs and total (normalized) power dissipation, with AVERAGE = 1000 and k